Merge keystone/mirror-android-mainline into keystone/android-mainline-keystone-qcom-dev

* keystone/mirror-android-mainline:
  ANDROID: fix up broken dm-table.c out-of-tree code.
  ANDROID: hung_task: Add vendor hook for hung task detect
  Revert "ANDROID: GKI: Add ‘kunit.enable’ module parameter"
  Revert "ANDROID: GKI: Return ERROR value on KUnit load fail"
  ANDROID: GKI: export thermal_cdev_update
  ANDROID: sched: Fix deadlock in sched_blocked_reason tracepoint
  Revert "ANDROID: PCI: dwc: revert dwc 32-bit DMA mask for MSI address requirement"
  Revert "ANDROID: Sched: Add hooks for scheduler"
  Revert "ANDROID: sched: Add vendor hooks for find_energy_efficient_cpu"
  Revert "ANDROID: sched: add em_cpu_energy vendor hook"
  Revert "ANDROID: sched: Make uclamp changes depend on CAP_SYS_NICE"
  ANDROID: GKI: remove CONFIG_ARM_CPUIDLE=y
  ANDROID: Incremental fs: fix setxattr callbacks due to upstream changes
  ata: sata_mv: Fixes expected number of resources now IRQs are gone
  fs: remove the NULL get_block case in mpage_writepages
  fs: don't call ->writepage from __mpage_writepage
  fs: remove the nobh helpers
  jfs: stop using the nobh helper
  ext2: remove nobh support
  ntfs3: refactor ntfs_writepages
  mm/folio-compat: Remove migration compatibility functions
  fs: Remove aops->migratepage()
  secretmem: Convert to migrate_folio
  hugetlb: Convert to migrate_folio
  aio: Convert to migrate_folio
  f2fs: Convert to filemap_migrate_folio()
  ubifs: Convert to filemap_migrate_folio()
  btrfs: Convert btrfs_migratepage to migrate_folio
  mm/migrate: Add filemap_migrate_folio()
  mm/migrate: Convert migrate_page() to migrate_folio()
  nfs: Convert to migrate_folio
  btrfs: Convert btree_migratepage to migrate_folio
  mm/migrate: Convert expected_page_refs() to folio_expected_refs()
  mm/migrate: Convert buffer_migrate_page() to buffer_migrate_folio()
  mm/migrate: Convert writeout() to take a folio
  mm/migrate: Convert fallback_migrate_page() to fallback_migrate_folio()
  fs: Add aops->migrate_folio
  mm: Convert all PageMovable users to movable_operations
  secretmem: Remove isolate_page
  ext2: Use a folio in ext2_get_page()
  gfs2: Convert gfs2_jhead_process_page() to use a folio
  ocfs2: Convert ocfs2_read_folio() to use a folio
  freevxfs: Convert vxfs_immed_read_folio() to use a folio
  coda: Convert coda_symlink_filler() to use a folio
  befs: Convert befs_symlink_read_folio() to use a folio
  block: Convert read_part_sector() to use a folio
  block: Use PAGE_SECTORS_SHIFT
  block: Handle partition read errors more consistently
  block: Simplify read_part_sector()
  cramfs: read_mapping_page() is synchronous
  ocfs2: Use filemap_write_and_wait_range() in ocfs2_cow_sync_writeback()
  hostfs: Handle page write errors correctly
  squashfs: Return the actual error from squashfs_read_folio()
  buffer: Don't test folio error in block_read_full_folio()
  PCI: imx6: Support more than Gen2 speed link mode
  PCI: imx6: Set PCIE_DBI_RO_WR_EN before writing DBI registers
  PCI: imx6: Reformat suspend callback to keep symmetric with resume
  PCI: imx6: Move the imx6_pcie_ltssm_disable() earlier
  PCI: imx6: Disable clocks in reverse order of enable
  PCI: imx6: Do not hide PHY driver callbacks and refine the error handling
  PCI: imx6: Reduce resume time by only starting link if it was up before suspend
  PCI: imx6: Mark the link down as non-fatal error
  PCI: imx6: Move regulator enable out of imx6_pcie_deassert_core_reset()
  PCI: imx6: Turn off regulator when system is in suspend mode
  PCI: imx6: Call host init function directly in resume
  PCI: imx6: Disable i.MX6QDL clock when disabling ref clocks
  PCI: imx6: Propagate .host_init() errors to caller
  PCI: imx6: Collect clock enables in imx6_pcie_clk_enable()
  PCI: imx6: Factor out ref clock disable to match enable
  PCI: imx6: Move imx6_pcie_clk_disable() earlier
  PCI: imx6: Move imx6_pcie_enable_ref_clk() earlier
  PCI: imx6: Move PHY management functions together
  PCI: imx6: Move imx6_pcie_grp_offset(), imx6_pcie_configure_type() earlier
  PCI: imx6: Convert to NOIRQ_SYSTEM_SLEEP_PM_OPS()
  PCI: exynos: Correct generic PHY usage
  phy: samsung: phy-exynos-pcie: sanitize init/power_on callbacks
  dt-bindings: PCI: qcom: Support additional MSI vectors
  PCI: dwc: Handle MSIs routed to multiple GIC interrupts
  PCI: dwc: Convert struct pcie_port.msi_irq to an array
  PCI: dwc: Split MSI IRQ parsing/allocation to a separate function
  PCI: dwc: Correct msi_irq condition in dw_pcie_free_msi()
  PCI: dwc: Use the bitmap API to allocate bitmaps
  PCI: dwc: Fix MSI msi_msg DMA mapping
  PCI: dwc: Check iATU in/outbound range setup status
  PCI: dwc: Validate iATU outbound mappings against hardware constraints
  PCI: dwc: Add iATU regions size detection procedure
  PCI: dwc: Simplify in/outbound iATU setup methods
  PCI: dwc: Drop enum dw_pcie_region_type in favor of PCIE_ATU_REGION_DIR_IB/OB
  PCI: dwc: Drop enum dw_pcie_as_type in favor of PCIE_ATU_TYPE_MEM/IO
  PCI: dwc: Add dw_pcie_ops.host_deinit() callback
  PCI: tegra194: Drop manual DW PCIe controller version setup
  PCI: intel-gw: Drop manual DW PCIe controller version setup
  PCI: dwc: Add macros to compare Synopsys IP core versions
  PCI: dwc: Read DWC IP core version from register
  PCI: dwc: Use native DWC IP core version representation
  PCI: dwc: Detect iATU settings after getting "addr_space" resource
  PCI: dwc: Log link speed and width if it comes up
  smack: Remove the redundant lsm_inode_alloc
  smack: Replace kzalloc + strncpy with kstrndup
  affs: use memcpy_to_page and remove replace kmap_atomic()
  rseq: Kill process when unknown flags are encountered in ABI structures
  rseq: Deprecate RSEQ_CS_FLAG_NO_RESTART_ON_* flags
  fs/dcache: Move wakeup out of i_seq_dir write held region.
  fs/dcache: Move the wakeup from __d_lookup_done() to the caller.
  fs/dcache: Disable preemption on i_dir_seq write side on PREEMPT_RT
  d_add_ci(): make sure we don't miss d_lookup_done()
  random: correct spelling of "overwrites"
  PCI: qcom: Allow ASPM L1 and substates for 2.7.0
  sparc: Use generic pci_mmap_resource_range()
  PCI: Remove pci_mmap_page_range() wrapper
  PCI: Stub __pci_ioport_map() for arches that don't support it at all
  MAINTAINERS: add spi support to GXP
  spi: dt-bindings: add documentation for hpe,gxp-spifi
  spi: spi-gxp: Add support for HPE GXP SoCs
  pwm: lpc18xx: Fix period handling
  pwm: lpc18xx: Convert to use dev_err_probe()
  pwm: twl-led: Document some limitations and link to the reference manual
  MAINTAINERS: Remove myself as PWM maintainer
  MAINTAINERS: Add include/dt-bindings/pwm to PWM SUBSYSTEM
  dt-bindings: pwm: mediatek: Add compatible string for MT8195
  pwm: Add clock based PWM output driver
  dt-bindings: pwm: Document clk based PWM controller
  pwm: sifive: Shut down hardware only after pwmchip_remove() completed
  pwm: sifive: Ensure the clk is enabled exactly once per running PWM
  pwm: sifive: Simplify clk handling
  pwm: sifive: Enable clk only after period check in .apply()
  pwm: sifive: Reduce time the controller lock is held
  pwm: sifive: Fold pwm_sifive_enable() into its only caller
  pwm: sifive: Simplify offset calculation for PWMCMP registers
  crypto: tcrypt - Remove the static variable initialisations to NULL
  crypto: arm64/poly1305 - fix a read out-of-bound
  crypto: hisilicon/zip - Use the bitmap API to allocate bitmaps
  crypto: hisilicon/sec - fix auth key size error
  crypto: ccree - Remove a useless dma_supported() call
  crypto: ccp - Add support for new CCP/PSP device ID
  crypto: inside-secure - Add missing MODULE_DEVICE_TABLE for of
  crypto: hisilicon/hpre - don't use GFP_KERNEL to alloc mem during softirq
  dm: verity-loadpin: Drop use of dm_table_get_num_targets()
  dm: fix dm-raid crash if md_handle_request() splits bio
  dm raid: fix address sanitizer warning in raid_resume
  dm raid: fix address sanitizer warning in raid_status
  dm: Start pr_preempt from the same starting path
  dm: Fix PR release handling for non All Registrants
  dm: Start pr_reserve from the same starting path
  dm: Allow dm_call_pr to be used for path searches
  dm: return early from dm_pr_call() if DM device is suspended
  Documentation: KUnit: Fix example with compilation error
  tools/power turbostat: version 2022.07.28
  tools/power turbostat: do not decode ACC for ICX and SPR
  tools/power turbostat: fix SPR PC6 limits
  tools/power turbostat: cleanup 'automatic_cstate_conversion_probe()'
  tools/power turbostat: separate SPR from ICX
  tools/power turbosstat: fix comment
  tools/power turbostat: Support RAPTORLAKE P
  tools/power turbostat: add support for ALDERLAKE_N
  tools/power turbostat: dump secondary Turbo-Ratio-Limit
  tools/power turbostat: simplify dump_turbo_ratio_limits()
  tools/power turbostat: dump CPUID.7.EDX.Hybrid
  tools/power turbostat: update turbostat.8
  tools/power turbostat: Show uncore frequency
  tools/power turbostat: Fix file pointer leak
  tools/power turbostat: replace strncmp with single character compare
  tools/power turbostat: print the kernel boot commandline
  tools/power turbostat: Introduce support for RaptorLake
  cgroup: Skip subtree root in cgroup_update_dfl_csses()
  docs: efi-stub: Fix paths for x86 / arm stubs
  Docs/zh_CN: Update the translation of sched-stats to 5.19-rc8
  Docs/zh_CN: Update the translation of pci to 5.19-rc8
  Docs/zh_CN: Update the translation of pci-iov-howto to 5.19-rc8
  Docs/zh_CN: Update the translation of usage to 5.19-rc8
  Docs/zh_CN: Update the translation of testing-overview to 5.19-rc8
  Docs/zh_CN: Update the translation of sparse to 5.19-rc8
  Docs/zh_CN: Update the translation of kasan to 5.19-rc8
  Docs/zh_CN: Update the translation of iio_configfs to 5.19-rc8
  doc:it_IT: align Italian documentation
  thermal/of: Initialize trip points separately
  thermal/of: Use thermal trips stored in the thermal zone
  thermal/core: Add thermal_trip in thermal_zone
  thermal/core: Rename 'trips' to 'num_trips'
  thermal/core: Move thermal_set_delay_jiffies to static
  thermal/core: Remove unneeded EXPORT_SYMBOLS
  thermal/of: Move thermal_trip structure to thermal.h
  thermal/of: Remove the device node pointer for thermal_trip
  thermal/of: Replace device node match with device node search
  thermal/core: Remove duplicate information when an error occurs
  thermal/core: Avoid calling ->get_trip_temp() unnecessarily
  thermal/tools/tmon: Fix typo 'the the' in comment
  thermal/tools/tmon: Include pthread and time headers in tmon.h
  thermal/ti-soc-thermal: Fix comment typo
  thermal/drivers/qcom/spmi-adc-tm5: Register thermal zones as hwmon sensors
  thermal/drivers/qcom/temp-alarm: Register thermal zones as hwmon sensors
  thermal/drivers/u8500: Remove unnecessary print function dev_err()
  thermal/drivers/rzg2l: Fix comments
  thermal/drivers/sun8i: Fix typo in comment
  thermal/drivers/k3_j72xx_bandgap: Make k3_j72xx_bandgap_j721e_data and k3_j72xx_bandgap_j7200_data static
  thermal/drivers/k3_j72xx_bandgap: Fix array underflow in prep_lookup_table()
  thermal/drivers/k3_j72xx_bandgap: Fix ref_table memory leak during probe
  thermal/core: Remove DROP_FULL and RAISE_FULL
  thermal/core: Use clamp() helper in the stepwise governor
  thermal/drivers/u8500: Remove the get_trend function
  thermal/drivers/tegra: Remove get_trend function
  thermal/drivers/qcom: Remove get_trend function
  dt-bindings: thermal: rcar-gen3-thermal: Add r8a779f0 support
  dt-bindings: thermal: rcar-gen3-thermal: use positive logic
  dt-bindings: thermal: qcom,spmi-temp-alarm: convert to dtschema
  drivers/thermal/rcar_gen3_thermal: Improve logging during probe
  MAINTAINERS: add include/dt-bindings/thermal to THERMAL
  drivers/thermal/devfreq_cooling: Extend the devfreq_cooling_device with ops
  drivers/thermal/cpufreq_cooling: Update outdated comments
  drivers/thermal/cpufreq_cooling : Refactor thermal_power_cpu_get_power tracing
  drivers/thermal/cpufreq_cooling: Use private callback ops for each cooling device
  wait: Fix __wait_event_hrtimeout for RT/DL tasks
  exec: Call kmap_local_page() in copy_string_kernel()
  kasan: test: Silence GCC 12 warnings
  ACPI/PCI: Remove useless NULL pointer checks
  drivers: lkdtm: fix clang -Wformat warning
  selftests/seccomp: Fix compile warning when CC=clang
  cgroup: remove "no" prefixed mount options
  PCI: Convert to new *_PM_OPS macros
  PCI: brcmstb: Rename .map_bus() functions to end with 'map_bus'
  PCI: brcmstb: Disable/enable regulators in suspend/resume
  PCI: brcmstb: Enable child bus device regulators from DT
  PCI: brcmstb: Split post-link up initialization to brcm_pcie_start_link()
  PCI: brcmstb: Prevent config space access when link is down
  PCI: brcmstb: Remove unnecessary forward declarations
  clocksource/drivers/sun5i: Remove unnecessary (void*) conversions
  dt-bindings: timer: allwinner,sun4i-a10-timer: Add D1 compatible
  dt-bindings: timer: ingenic,tcu: use absolute path to other schema
  clocksource/drivers/sun4i: Remove unnecessary (void*) conversions
  dt-bindings: timer: renesas,cmt: Fix R-Car Gen4 fall-out
  clocksource/drivers/tegra186: Put Kconfig option 'tristate' to 'bool'
  clocksource/drivers/timer-ti-dm: Make driver selection bool for TI K3
  clocksource/drivers/timer-ti-dm: Add compatible for am6 SoCs
  clocksource/drivers/timer-ti-dm: Make timer selectable for ARCH_K3
  clocksource/drivers/timer-ti-dm: Move inline functions to driver for am6
  io_uring: notification completion optimisation
  io_uring: export req alloc from core
  dt-bindings: soc: bcm: use absolute path to other schema
  dt-bindings: soc: bcm: drop quotes when not needed
  arm64: defconfig: Sync some configs with savedefconfig
  hwmon: (aquacomputer_d5next) Add support for Aquacomputer Quadro fan controller
  hwmon: (dell-smm) Improve documentation
  regulator: core: Allow drivers to define their init data as const
  regulator: core: Allow specifying an initial load w/ the bulk API
  regulator: mt6380: Fix unused array warning
  perf/x86/ibs: Add new IBS register bits into header
  Add Seth Forshee as co-maintainer for idmapped mounts
  dt-bindings: soc: microchip: use absolute path to other schema
  dt-bindings: soc: microchip: drop quotes when not needed
  ARM: dts: lan966x: keep lan966 entries alphabetically sorted
  hwmon: (nct6775) add ASUS TUF GAMING B550-PLUS WIFI II
  Makefile: replace headers_install with headers for kselftest
  Documentation: kunit: Add CLI args for kunit_tool
  x86/cyrix: include header linux/isa-dma.h
  powercap: RAPL: Add Power Limit4 support for Alder Lake-N and Raptor Lake-P
  ACPI: CPPC: Do not prevent CPPC from working in the future
  ACPI: PM: x86: Print messages regarding LPS0 idle support
  PM: QoS: Add check to make sure CPU freq is non-negative
  PM: hibernate: defer device probing when resuming from hibernation
  ublk_drv: fix double shift bug
  spi: a3700: support BE for AC5 SPI driver
  hwmon: (occ) Replace open-coded variant of %*phN specifier
  hwmon: (sht15) Fix wrong assumptions in device remove callback
  hwmon: (aquacomputer_d5next) Add support for reading the +12V voltage sensor on D5 Next
  spi/panel: dt-bindings: drop CPHA and CPOL from common properties
  ARM: dts: lan966x: add support for pcb8309
  intel_idle: make SPR C1 and C1E be independent
  cpufreq: ondemand: Use cpumask_var_t for on-stack cpu mask
  cpufreq: loongson2: fix Kconfig "its" grammar
  btrfs: don't call btrfs_page_set_checked in finish_compressed_bio_read
  btrfs: fix repair of compressed extents
  btrfs: remove the start argument to check_data_csum and export
  btrfs: pass a btrfs_bio to btrfs_repair_one_sector
  btrfs: simplify the pending I/O counting in struct compressed_bio
  io_uring/net: use unsigned for flags
  io_uring/net: make page accounting more consistent
  io_uring/net: checks errors of zc mem accounting
  io_uring/net: improve io_get_notif_slot types
  btrfs: repair all known bad mirrors
  btrfs: merge btrfs_dev_stat_print_on_error with its only caller
  btrfs: join running log transaction when logging new name
  btrfs: simplify error handling in btrfs_lookup_dentry
  btrfs: send: always use the rbtree based inode ref management infrastructure
  btrfs: send: fix sending link commands for existing file paths
  btrfs: send: introduce recorded_ref_alloc and recorded_ref_free
  btrfs: zoned: wait until zone is finished when allocation didn't progress
  btrfs: zoned: write out partially allocated region
  btrfs: zoned: activate necessary block group
  btrfs: zoned: activate metadata block group on flush_space
  btrfs: zoned: disable metadata overcommit for zoned
  btrfs: zoned: introduce space_info->active_total_bytes
  btrfs: zoned: finish least available block group on data bg allocation
  btrfs: let can_allocate_chunk return error
  btrfs: use fs_info->max_extent_size in get_extent_max_capacity()
  btrfs: convert count_max_extents() to use fs_info->max_extent_size
  btrfs: replace BTRFS_MAX_EXTENT_SIZE with fs_info->max_extent_size
  btrfs: zoned: revive max_zone_append_bytes
  block: add bdev_max_segments() helper
  btrfs: add optimized btrfs_ino() version for 64 bits systems
  btrfs: set the objectid of the btree inode's location key
  btrfs: replace kmap_atomic() with kmap_local_page()
  btrfs: zlib: replace kmap() with kmap_local_page() in zlib_decompress_bio()
  btrfs: zlib: replace kmap() with kmap_local_page() in zlib_compress_pages()
  btrfs: zstd: replace kmap() with kmap_local_page()
  highmem: Make __kunmap_{local,atomic}() take const void pointer
  btrfs: don't fallback to buffered IO for NOWAIT direct IO writes
  btrfs: use enum for btrfs_block_rsv::type
  btrfs: switch btrfs_block_rsv::failfast to bool
  btrfs: switch btrfs_block_rsv::full to bool
  btrfs: do not return errors from btrfs_submit_dio_bio
  btrfs: handle allocation failure in btrfs_wq_submit_bio gracefully
  btrfs: simplify sync/async submission in btrfs_submit_data_write_bio
  btrfs: raid56: transfer the bio counter reference to the raid submission helpers
  btrfs: do not return errors from raid56_parity_recover
  btrfs: do not return errors from raid56_parity_write
  btrfs: do not return errors from btrfs_map_bio
  btrfs: return proper mapped length for RAID56 profiles in __btrfs_map_block()
  btrfs: raid56: use fixed stripe length everywhere
  btrfs: remove the inode cache check at btrfs_is_free_space_inode()
  btrfs: sysfs: remove BIG_METADATA feature files
  btrfs: sysfs: remove MIXED_BACKREF feature file
  btrfs: don't print 'has skinny extents' anymore on mount
  btrfs: don't print 'flagging with big metadata' anymore on mount
  btrfs: clean up chained assignments
  btrfs: merge calculations for simple striped profiles in btrfs_rmap_block
  btrfs: use mask for all RAID1* profiles in btrfs_calc_avail_data_space
  btrfs: properly flag filesystem with BTRFS_FEATURE_INCOMPAT_BIG_METADATA
  btrfs: print checksum type and implementation at mount time
  btrfs: reset block group chunk force if we have to wait
  btrfs: send: add new command FILEATTR for file attributes
  btrfs: send: add OTIME as utimes attribute for proto 2+ by default
  btrfs: output mirror number for bad metadata
  btrfs: replace unnecessary goto with direct return at cow_file_range()
  btrfs: fix error handling of fallback uncompress write
  btrfs: extend btrfs_cleanup_ordered_extents for NULL locked_page
  btrfs: ensure pages are unlocked on cow_file_range() failure
  btrfs: sysfs: export commit stats
  btrfs: collect commit stats, count, duration
  btrfs: remove extent writepage address space operation
  btrfs: send: use boolean types for current inode status
  btrfs: send: remove old TODO regarding ERESTARTSYS
  btrfs: send: simplify includes
  btrfs: send: drop __KERNEL__ ifdef from send.h
  btrfs: increase direct io read size limit to 256 sectors
  btrfs: raid56: don't trust any cached sector in __raid56_parity_recover()
  btrfs: remove the finish_func argument to btrfs_mark_ordered_io_finished
  btrfs: batch up release of reserved metadata for delayed items used for deletion
  btrfs: warn about dev extents that are inside the reserved range
  btrfs: use named constant for reserved device space
  btrfs: remove unused typedefs get_extent_t and btrfs_work_func_t
  btrfs: sink iterator parameter to btrfs_ioctl_logical_to_ino
  btrfs: simplify parameters of backref iterators
  btrfs: call inode_to_path directly and drop indirection
  btrfs: use ncopies from btrfs_raid_array in btrfs_num_copies()
  btrfs: use btrfs_raid_array to calculate number of parity stripes
  btrfs: use btrfs_chunk_max_errors() to replace tolerance calculation
  btrfs: remove parameter dev_extent_len from scrub_stripe()
  btrfs: unify tree search helper returning prev and next nodes
  btrfs: make tree search for insert more generic and use it for tree_search
  btrfs: open code inexact rbtree search in tree_search
  btrfs: remove node and parent parameters from insert_state
  btrfs: add fast path for extent_state insertion
  btrfs: pass bits by value not by pointer for extent_state helpers
  btrfs: lift start and end parameters to callers of insert_state
  btrfs: open code rbtree search in insert_state
  btrfs: open code rbtree search in split_state
  btrfs: raid56: avoid double for loop inside raid56_parity_scrub_stripe()
  btrfs: raid56: avoid double for loop inside raid56_rmw_stripe()
  btrfs: raid56: avoid double for loop inside alloc_rbio_essential_pages()
  btrfs: raid56: avoid double for loop inside __raid56_parity_recover()
  btrfs: raid56: avoid double for loop inside finish_rmw()
  btrfs: tree-log: make the return value for log syncing consistent
  btrfs: add tracepoints for ordered extents
  btrfs: sysfs: advertise zoned support among features
  btrfs: split discard handling out of btrfs_map_block
  btrfs: stop looking at btrfs_bio->iter in index_one_bio
  btrfs: reject log replay if there is unsupported RO compat flag
  btrfs: make btrfs_super_block::log_root_transid deprecated
  btrfs: pass the btrfs_bio_ctrl to submit_one_bio
  btrfs: merge end_write_bio and flush_write_bio
  btrfs: don't use bio->bi_private to pass the inode to submit_one_bio
  btrfs: remove redundant check in up check_setget_bounds
  btrfs: replace kmap() with kmap_local_page() in lzo.c
  btrfs: replace kmap() with kmap_local_page() in inode.c
  btrfs: do not allocate a btrfs_bio for low-level bios
  btrfs: factor stripe submission logic out of btrfs_map_bio
  btrfs: remove btrfs_end_io_wq
  btrfs: centralize setting REQ_META
  btrfs: don't use btrfs_bio_wq_end_io for compressed writes
  btrfs: don't double-defer bio completions for compressed reads
  btrfs: defer I/O completion based on the btrfs_raid_bio
  btrfs: split btrfs_submit_data_bio to read and write parts
  btrfs: simplify code flow in btrfs_submit_dio_bio
  btrfs: move more work into btrfs_end_bioc
  btrfs: send: enable support for stream v2 and compressed writes
  btrfs: send: send compressed extents with encoded writes
  btrfs: send: get send buffer pages for protocol v2
  btrfs: send: write larger chunks when using stream v2
  btrfs: send: add stream v2 definitions
  btrfs: send: explicitly number commands and attributes
  btrfs: send: remove unused send_ctx::{total,cmd}_send_size
  btrfs: sysfs: add force_chunk_alloc trigger to force allocation
  btrfs: sysfs: export chunk size in space infos
  btrfs: store chunk size in space-info struct
  btrfs: do not batch insert non-consecutive dir indexes during log replay
  btrfs: reduce amount of reserved metadata for delayed item insertion
  btrfs: set delayed item type when initializing it
  btrfs: do not BUG_ON() on failure to reserve metadata for delayed item
  btrfs: improve batch insertion of delayed dir index items
  btrfs: assert that delayed item is a dir index item when adding it
  btrfs: improve batch deletion of delayed dir index items
  btrfs: refactor the delayed item deletion entry point
  btrfs: deal with deletion errors when deleting delayed items
  btrfs: add assertions when deleting batches of delayed items
  btrfs: balance btree dirty pages and delayed items after clone and dedupe
  btrfs: free the path earlier when creating a new inode
  btrfs: balance btree dirty pages and delayed items after a rename
  btrfs: add trace event for submitted RAID56 bio
  btrfs: update stripe_sectors::uptodate in steal_rbio
  btrfs: remove redundant calls to flush_dcache_page
  btrfs: only write the sectors in the vertical stripe which has data stripes
  btrfs: use integrated bitmaps for scrub_parity::dbitmap and ebitmap
  btrfs: use integrated bitmaps for btrfs_raid_bio::dbitmap and finish_pbitmap
  btrfs: use btrfs_try_lock_balance in btrfs_ioctl_balance
  btrfs: introduce btrfs_try_lock_balance
  btrfs: use btrfs_bio_for_each_sector in btrfs_check_read_dio_bio
  btrfs: add a helper to iterate through a btrfs_bio with sector sized chunks
  btrfs: factor out a btrfs_csum_ptr helper
  btrfs: refactor end_bio_extent_readpage code flow
  btrfs: factor out a helper to end a single sector buffer I/O
  btrfs: remove duplicated parameters from submit_data_read_repair()
  btrfs: introduce a data checksum checking helper
  btrfs: quit early if the fs has no RAID56 support for raid56 related checks
  btrfs: use PAGE_ALIGNED instead of IS_ALIGNED
  btrfs: zoned: fix comment description for sb_write_pointer logic
  btrfs: fix typos in comments
  spi: bcm2835: enable shared interrupt support
  random: handle archrandom with multiple longs
  arm64: Delay initialisation of cpuinfo_arm64::reg_{zcr,smcr}
  irqchip/mmp: Declare init functions in common header file
  x86/purgatory: Omit use of bin2c
  x86/purgatory: Hard-code obj-y in Makefile
  dt-bindings: arm: at91: add lan966 pcb8309 board
  selftests/io_uring: test zerocopy send
  io_uring: enable managed frags with register buffers
  io_uring: add zc notification flush requests
  io_uring: rename IORING_OP_FILES_UPDATE
  io_uring: flush notifiers after sendzc
  io_uring: sendzc with fixed buffers
  io_uring: allow to pass addr into sendzc
  io_uring: account locked pages for non-fixed zc
  io_uring: wire send zc request type
  io_uring: add notification slot registration
  io_uring: add rsrc referencing for notifiers
  io_uring: complete notifiers in tw
  io_uring: cache struct io_notif
  io_uring: add zc notification infrastructure
  io_uring: export io_put_task()
  io_uring: initialise msghdr::msg_ubuf
  mm: honor FGP_NOWAIT for page cache page allocation
  xfs: Add async buffered write support
  xfs: Specify lockmode when calling xfs_ilock_for_iomap()
  io_uring: Add tracepoint for short writes
  io_uring: fix issue with io_write() not always undoing sb_start_write()
  io_uring: Add support for async buffered writes
  fs: Add async write file modification handling.
  fs: Split off inode_needs_update_time and __file_update_time
  fs: add __remove_file_privs() with flags parameter
  fs: add a FMODE_BUF_WASYNC flags for f_mode
  iomap: Return -EAGAIN from iomap_write_iter()
  iomap: Add async buffered write support
  iomap: Add flags parameter to iomap_page_create()
  mm: Add balance_dirty_pages_ratelimited_flags() function
  mm: Move updates of dirty_exceeded into one place
  mm: Move starting of background writeback into the main balancing loop
  io_uring: ensure REQ_F_ISREG is set async offload
  net: fix compat pointer in get_compat_msghdr()
  io_uring: Don't require reinitable percpu_ref
  io_uring: fix types in io_recvmsg_multishot_overflow
  io_uring: Use atomic_long_try_cmpxchg in __io_account_mem
  io_uring: support multishot in recvmsg
  net: copy from user before calling __get_compat_msghdr
  net: copy from user before calling __copy_msghdr
  io_uring: support 0 length iov in buffer select in compat
  io_uring: fix multishot ending when not polled
  io_uring: add netmsg cache
  io_uring: impose max limit on apoll cache
  io_uring: add abstraction around apoll cache
  io_uring: move apoll cache to poll.c
  io_uring: consolidate hash_locked io-wq handling
  io_uring: clear REQ_F_HASH_LOCKED on hash removal
  io_uring: don't race double poll setting REQ_F_ASYNC_DATA
  io_uring: don't miss setting REQ_F_DOUBLE_POLL
  io_uring: disable multishot recvmsg
  io_uring: only trace one of complete or overflow
  io_uring: fix io_uring_cqe_overflow trace format
  io_uring: multishot recv
  io_uring: fix multishot accept ordering
  io_uring: fix multishot poll on overflow
  io_uring: add allow_overflow to io_post_aux_cqe
  io_uring: add IOU_STOP_MULTISHOT return code
  io_uring: clean up io_poll_check_events return values
  io_uring: recycle buffers on error
  io_uring: allow iov_len = 0 for recvmsg and buffer select
  io_uring: restore bgid in io_put_kbuf
  io_uring: allow 0 length for buffer select
  io_uring: let to set a range for file slot allocation
  io_uring: add support for passing fixed file descriptors
  io_uring: split out fixed file installation and removal
  io_uring: replace zero-length array with flexible-array member
  io_uring: remove ctx->refs pinning on enter
  io_uring: don't check file ops of registered rings
  io_uring: remove extra TIF_NOTIFY_SIGNAL check
  io_uring: fuse fallback_node and normal tw node
  io_uring: improve io_fail_links()
  io_uring: move POLLFREE handling to separate function
  io_uring: kbuf: inline io_kbuf_recycle_ring()
  io_uring: optimise submission side poll_refs
  io_uring: refactor poll arm error handling
  io_uring: change arm poll return values
  io_uring: add a helper for apoll alloc
  io_uring: remove events caching atavisms
  io_uring: clean poll ->private flagging
  io_uring: add sync cancelation API through io_uring_register()
  io_uring: add IORING_ASYNC_CANCEL_FD_FIXED cancel flag
  io_uring: have cancelation API accept io_uring_task directly
  io_uring: kbuf: kill __io_kbuf_recycle()
  io_uring: trace task_work_run
  io_uring: add trace event for running task work
  io_uring: batch task_work
  io_uring: introduce llist helpers
  io_uring: lockless task list
  io_uring: remove __io_req_task_work_add
  io_uring: remove priority tw list optimisation
  io_uring: dedup io_run_task_work
  io_uring: move list helpers to a separate file
  io_uring: improve io_run_task_work()
  io_uring: optimize io_uring_task layout
  io_uring: add a warn_once for poll_find
  io_uring: consistent naming for inline completion
  io_uring: move io_import_fixed()
  io_uring: opcode independent fixed buf import
  io_uring: add io_commit_cqring_flush()
  io_uring: introduce locking helpers for CQE posting
  io_uring: hide eventfd assumptions in eventfd paths
  io_uring: fix io_poll_remove_all clang warnings
  io_uring: improve task exit timeout cancellations
  io_uring: fix multi ctx cancellation
  io_uring: remove ->flush_cqes optimisation
  io_uring: move io_eventfd_signal()
  io_uring: reshuffle io_uring/io_uring.h
  io_uring: remove extra io_commit_cqring()
  io_uring: move a few private types to local headers
  io_uring: clean up tracing events
  io_uring: make io_uring_types.h public
  io_uring: kill extra io_uring_types.h includes
  io_uring: change ->cqe_cached invariant for CQE32
  io_uring: deduplicate io_get_cqe() calls
  io_uring: deduplicate __io_fill_cqe_req tracing
  io_uring: introduce io_req_cqe_overflow()
  io_uring: don't inline __io_get_cqe()
  io_uring: don't expose io_fill_cqe_aux()
  io_uring: kbuf: add comments for some tricky code
  io_uring: mutex locked poll hashing
  io_uring: propagate locking state to poll cancel
  io_uring: introduce a struct for hash table
  io_uring: pass hash table into poll_find
  io_uring: add IORING_SETUP_SINGLE_ISSUER
  io_uring: use state completion infra for poll reqs
  io_uring: clean up io_ring_ctx_alloc
  io_uring: limit the number of cancellation buckets
  io_uring: clean up io_try_cancel
  io_uring: pass poll_find lock back
  io_uring: switch cancel_hash to use per entry spinlock
  io_uring: poll: remove unnecessary req->ref set
  io_uring: don't inline io_put_kbuf
  io_uring: refactor io_req_task_complete()
  io_uring: kill REQ_F_COMPLETE_INLINE
  io_uring: rw: delegate sync completions to core io_uring
  io_uring: remove unused IO_REQ_CACHE_SIZE defined
  io_uring: don't set REQ_F_COMPLETE_INLINE in tw
  io_uring: remove check_cq checking from hot paths
  io_uring: never defer-complete multi-apoll
  io_uring: inline ->registered_rings
  io_uring: explain io_wq_work::cancel_seq placement
  io_uring: move small helpers to headers
  io_uring: refactor ctx slow data placement
  io_uring: better caching for ctx timeout fields
  io_uring: move defer_list to slow data
  io_uring: make reg buf init consistent
  io_uring: deprecate epoll_ctl support
  io_uring: add support for level triggered poll
  io_uring: move opcode table to opdef.c
  io_uring: move read/write related opcodes to its own file
  io_uring: move remaining file table manipulation to filetable.c
  io_uring: move rsrc related data, core, and commands
  io_uring: split provided buffers handling into its own file
  io_uring: move cancelation into its own file
  io_uring: move poll handling into its own file
  io_uring: add opcode name to io_op_defs
  io_uring: include and forward-declaration sanitation
  io_uring: move io_uring_task (tctx) helpers into its own file
  io_uring: move fdinfo helpers to its own file
  io_uring: use io_is_uring_fops() consistently
  io_uring: move SQPOLL related handling into its own file
  io_uring: move timeout opcodes and handling into its own file
  io_uring: move our reference counting into a header
  io_uring: move msg_ring into its own file
  io_uring: split network related opcodes into its own file
  io_uring: move statx handling to its own file
  io_uring: move epoll handler to its own file
  io_uring: add a dummy -EOPNOTSUPP prep handler
  io_uring: move uring_cmd handling to its own file
  io_uring: split out open/close operations
  io_uring: separate out file table handling code
  io_uring: split out fadvise/madvise operations
  io_uring: split out fs related sync/fallocate functions
  io_uring: split out splice related operations
  io_uring: split out filesystem related operations
  io_uring: move nop into its own file
  io_uring: move xattr related opcodes to its own file
  io_uring: handle completions in the core
  io_uring: set completion results upfront
  io_uring: add io_uring_types.h
  io_uring: define a request type cleanup handler
  io_uring: unify struct io_symlink and io_hardlink
  io_uring: convert iouring_cmd to io_cmd_type
  io_uring: convert xattr to use io_cmd_type
  io_uring: convert rsrc_update to io_cmd_type
  io_uring: convert msg and nop to io_cmd_type
  io_uring: convert splice to use io_cmd_type
  io_uring: convert epoll to io_cmd_type
  io_uring: convert file system request types to use io_cmd_type
  io_uring: convert madvise/fadvise to use io_cmd_type
  io_uring: convert open/close path to use io_cmd_type
  io_uring: convert timeout path to use io_cmd_type
  io_uring: convert cancel path to use io_cmd_type
  io_uring: convert the sync and fallocate paths to use io_cmd_type
  io_uring: convert net related opcodes to use io_cmd_type
  io_uring: remove recvmsg knowledge from io_arm_poll_handler()
  io_uring: convert poll_update path to use io_cmd_type
  io_uring: convert poll path to use io_cmd_type
  io_uring: convert read/write path to use io_cmd_type
  io_uring: add generic command payload type to struct io_kiocb
  io_uring: move req async preparation into opcode handler
  io_uring: move to separate directory
  io_uring: define a 'prep' and 'issue' handler for each opcode
  arm64: refresh defconfig file
  irqchip/mips-gic: Check the return value of ioremap() in gic_of_init()
  cgroup: Make !percpu threadgroup_rwsem operations optional
  cgroup: Add "no" prefixed mount options
  cgroup: Elide write-locking threadgroup_rwsem when updating csses on an empty subtree
  asm-generic: Add new pci.h and use it
  csky: PCI: Define ARCH_GENERIC_PCI_MMAP_RESOURCE
  PCI: Move isa_dma_bridge_buggy out of asm/dma.h
  PCI: Remove pci_get_legacy_ide_irq() and asm-generic/pci.h
  PCI: tegra194: Add Tegra234 PCIe support
  PCI: tegra194: Extend Endpoint mode support
  PCI: tegra194: Fix link up retry sequence
  PCI: tegra194: Clean up the exit path for Endpoint mode
  PCI: tegra194: Enable support for 256 Byte payload
  PCI: tegra194: Clear bandwidth management status
  PCI: tegra194: Fix Root Port interrupt handling
  PCI: tegra194: Find RAS DES PCIe capability offset
  Revert "PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie"
  PCI: Disable MSI for Tegra234 Root Ports
  dt-bindings: PCI: tegra234: Add schema for tegra234 Endpoint mode
  dt-bindings: PCI: tegra234: Add schema for tegra234 Root Port mode
  dt-bindings: PCI: tegra194: Convert to json-schema
  net: fix uninitialised msghdr->sg_from_iter
  s390/pci: allow zPCI zbus without a function zero
  PCI: Extend isolated function probing to s390
  PCI: Move jailhouse's isolated function handling to pci_scan_slot()
  PCI: Split out next_ari_fn() from next_fn()
  PCI: Clean up pci_scan_slot()
  PCI/ACPI: Update link to PCI firmware specification
  intel: thermal: PCH: Drop ACPI_FADT_LOW_POWER_S0 check
  MAINTAINERS: Add Xilinx Versal CPM Root Port maintainers
  PCI: xilinx-cpm: Add support for Versal CPM5 Root Port
  spi: dt-bindings: spi-controller: correct example indentation
  dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
  kcsan: test: Add a .kunitconfig to run KCSAN tests
  ublk_drv: make sure that correct flags(features) returned to userspace
  ublk_drv: fix error handling of ublk_add_dev
  ARM: dts: lan966x: Enable network driver on pcb8291
  MAINTAINERS: rectify entry for ARM/NUVOTON NPCM ARCHITECTURE
  ARM: cns3xxx: add CONFIG_UNUSED_BOARD_FILES dependency
  ARM: iop32x: mark as unused
  ARM: s3c: mark most board files as unused
  ARM: omap1: add Kconfig dependencies for unused boards
  ARM: sa1100: mark most boards as unused
  ARM: footbridge: mark cats board for removal
  ARM: mmp: mark all board files for removal
  ARM: ep93xx: mark most board files as unused
  ARM: davinci: mark all ATAGS board files as unused
  ARM: orion: add ATAGS dependencies
  ARM: pxa: add Kconfig dependencies for ATAGS based boards
  ARM: add CONFIG_UNUSED_BOARD_FILES
  ARM: add ATAGS dependencies to non-DT platforms
  ARM: defconfig: kill remnants of CONFIG_LEDS
  ARM: defconfig: remove broken CONFIG_THUMB disables
  ARM: defconfig: address renamed CONFIG_DEBUG_INFO=y
  ARM: defconfig: remove stale CONFIG_ZBOOT_ROM entries
  ARM: defconfig: remove irda remnants
  ARM: refresh defconfig files
  ARM: dts: lan966x: Disable can0 on pcb8291
  ARM: dts: lan966x: Add gpio-restart
  crypto: testmgr - some more fixes to RSA test vectors
  cyrpto: powerpc/aes - delete the rebundant word "block" in comments
  hwrng: via - Fix comment typo
  crypto: twofish - Fix comment typo
  crypto: rmd160 - fix Kconfig "its" grammar
  crypto: keembay-ocs-ecc - Drop if with an always false condition
  Documentation: qat: rewrite description
  Documentation: qat: Use code block for qat sysfs example
  rcu: Add irqs-disabled indicator to expedited RCU CPU stall warnings
  rcu: Diagnose extended sync_rcu_do_polled_gp() loops
  rcu: Put panic_on_rcu_stall() after expedited RCU CPU stall warnings
  rcutorture: Test polled expedited grace-period primitives
  rcu: Add polled expedited grace-period primitives
  rcutorture: Verify that polled GP API sees synchronous grace periods
  rcu: Make Tiny RCU grace periods visible to polled APIs
  rcu: Make polled grace-period API account for expedited grace periods
  rcu: Switch polled grace-period APIs to ->gp_seq_polled
  ublk_drv: fix lockdep warning
  PCI: loongson: Work around LS7A incorrect Interrupt Pin registers
  block: remove __blk_get_queue
  block: call blk_mq_exit_queue from disk_release for never added disks
  blk-mq: fix error handling in __blk_mq_alloc_disk
  ublk: defer disk allocation
  ublk: rewrite ublk_ctrl_get_queue_affinity to not rely on hctx->cpumask
  ublk: fold __ublk_create_dev into ublk_ctrl_add_dev
  ublk: cleanup ublk_ctrl_uring_cmd
  ublk: simplify ublk_ch_open and ublk_ch_release
  ublk: remove the empty open and release block device operations
  ublk: remove UBLK_IO_F_PREFLUSH
  ublk: add a MAINTAINERS entry
  ACPI: resource: skip IRQ override on AMD Zen platforms
  Documentation: ACPI: EINJ: Fix obsolete example
  hwmon: (tps23861) fix byte order in current and voltage registers
  hwmon: (aspeed-pwm-tacho) increase fan tach period (again)
  hwmon: (aquacomputer_d5next) Add D5 Next fan control support
  x86/extable: Fix ex_handler_msr() print condition
  x86,nospec: Simplify {JMP,CALL}_NOSPEC
  sched/core: Fix the bug that task won't enqueue into core tree when update cookie
  nohz/full, sched/rt: Fix missed tick-reenabling bug in dequeue_task_rt()
  dt-bindings: arm: aspeed: add Aspeed Evaluation boards
  docs: Remove spurious tag from admin-guide/mm/overcommit-accounting.rst
  Documentation: process: Update email client instructions for Thunderbird
  docs: ABI: correct QEMU fw_cfg spec path
  arm64: dts: qcom: Add support for Xiaomi Mi Mix2s
  dt-bindings: arm: qcom: Add Xiaomi Mi Mix2s bindings
  dt-bindings: arm: qcom: Document lg,judyln and lg,judyp devices
  dt-bindings: arm: qcom: add missing SM6350 board compatibles
  dt-bindings: arm: qcom: add missing SM6125 board compatibles
  dt-bindings: arm: qcom: add missing SDM845 board compatibles
  dt-bindings: arm: qcom: add missing SDM636 board compatibles
  dt-bindings: arm: qcom: add missing SDM630 board compatibles
  dt-bindings: arm: qcom: add missing QCS404 board compatibles
  spi: dt-bindings: qcom,spi-geni-qcom: allow three interconnects
  soc: a64fx-diag: disable modular build
  spi: npcm-fiu: Add NPCM8XX support
  dt-binding: spi: Add npcm845 compatible to npcm-fiu document
  spi: npcm-fiu: Modify direct read dummy configuration
  hwmon: (k10temp): Add support for new family 17h and 19h models
  x86/amd_nb: Add AMD PCI IDs for SMN communication
  dt-bindings: arm: qcom: add missing MSM8992 board compatibles
  dt-bindings: arm: qcom: add missing MSM8998 board compatibles
  dt-bindings: vendor-prefixes: add Shift GmbH
  dt-bindings: arm: qcom: add missing SM8350 board compatibles
  dt-bindings: arm: qcom: add missing SM8250 board compatibles
  dt-bindings: arm: qcom: add missing SM8150 board compatibles
  dt-bindings: arm: qcom: add missing MSM8994 board compatibles
  dt-bindings: arm: qcom: add missing MSM8916 board compatibles
  dt-bindings: arm: qcom: fix MSM8994 boards compatibles
  dt-bindings: arm: qcom: fix MSM8916 MTP compatibles
  dt-bindings: arm: qcom: fix Longcheer L8150 compatibles
  dt-bindings: arm: qcom: fix Alcatel OneTouch Idol 3 compatibles
  dt-bindings: soc: qcom: qcom,smd-rpm: add power-controller
  dt-bindings: soc: qcom: aoss: document qcom,sm8450-aoss-qmp
  dt-bindings: soc: qcom,rpmh-rsc: simplify qcom,tcs-config
  arm64: fix KASAN_INLINE
  genirq: Use for_each_action_of_desc in actions_show()
  regulator: Add missing type for 'regulator-microvolt-offset'
  block: don't allow the same type rq_qos add more than once
  mm/slab_common: move generic bulk alloc/free functions to SLOB
  mm/sl[au]b: use own bulk free function when bulk alloc failed
  irqchip / ACPI: Introduce ACPI_IRQ_MODEL_LPIC for LoongArch
  irqchip: Add LoongArch CPU interrupt controller support
  irqchip: Add Loongson Extended I/O interrupt controller support
  irqchip/loongson-liointc: Add ACPI init support
  irqchip/loongson-pch-msi: Add ACPI init support
  irqchip/loongson-pch-pic: Add ACPI init support
  irqchip: Add Loongson PCH LPC controller support
  LoongArch: Prepare to support multiple pch-pic and pch-msi irqdomain
  LoongArch: Use ACPI_GENERIC_GSI for gsi handling
  genirq/generic_chip: Export irq_unmap_generic_chip
  ACPI: irq: Allow acpi_gsi_to_irq() to have an arch-specific fallback
  APCI: irq: Add support for multiple GSI domains
  LoongArch: Provisionally add ACPICA data structures
  arm64/hwcap: Support FEAT_EBF16
  arm64/cpufeature: Store elf_hwcaps as a bitmap rather than unsigned long
  arm64/hwcap: Document allocation of upper bits of AT_HWCAP
  arm64: enable THP_SWAP for arm64
  ARM: at91: setup outer cache .write_sec() callback if needed
  ARM: at91: add sam_linux_is_optee_available() function
  crypto: lib - add module license to libsha1
  ARM: dts: lan966x: add clock gating register
  arm64: dts: qcom: qrb5165-rb5: Fix 'dtbs_check' error for led nodes
  arm64: dts: qcom: qrb5165-rb5: Fix 'dtbs_check' error for lpg nodes
  ARM: dts: aspeed: centriq2400: drop the board
  tcp: support externally provided ubufs
  ipv6/udp: support externally provided ubufs
  ipv4/udp: support externally provided ubufs
  net: introduce __skb_fill_page_desc_noacc
  net: introduce managed frags infrastructure
  net: Allow custom iter handler in msghdr
  skbuff: carry external ubuf_info in msghdr
  x86/cpu: Use MSR_IA32_MISC_ENABLE constants
  rcu/nocb: Avoid polling when my_rdp->nocb_head_rdp list is empty
  rcu/nocb: Add option to opt rcuo kthreads out of RT priority
  rcu: Add nocb_cb_kthread check to rcu_is_callbacks_kthread()
  rcu/nocb: Add an option to offload all CPUs on boot
  rcu/nocb: Fix NOCB kthreads spawn failure with rcu_nocb_rdp_deoffload() direct call
  rcu/nocb: Invert rcu_state.barrier_mutex VS hotplug lock locking order
  rcu/nocb: Add/del rdp to iterate from rcuog itself
  rcu/tree: Add comment to describe GP-done condition in fqs loop
  rcu: Initialize first_gp_fqs at declaration in rcu_gp_fqs()
  rcu/kvfree: Remove useless monitor_todo flag
  rcu: Cleanup RCU urgency state for offline CPU
  rcu: tiny: Record kvfree_call_rcu() call stack for KASAN
  locking/csd_lock: Change csdlock_debug from early_param to __setup
  rcu: Forbid RCU_STRICT_GRACE_PERIOD in TINY_RCU kernels
  rcu: Immediately boost preempted readers for strict grace periods
  rcu: Add rnp->cbovldmask check in rcutree_migrate_callbacks()
  rcu: Avoid tracing a few functions executed in stop machine
  rcu: Decrease FQS scan wait time in case of callback overloading
  arm64/mm: use GENMASK_ULL for TTBR_BADDR_MASK_52
  arm64: errata: Remove AES hwcap for COMPAT tasks
  arm64: numa: Don't check node against MAX_NUMNODES
  drivers/perf: arm_spe: Fix consistency of SYS_PMSCR_EL1.CX
  regulator: core: Fix off-on-delay-us for always-on/boot-on regulators
  perf: RISC-V: Add of_node_put() when breaking out of for_each_of_cpu_node()
  PCI: fu740: Remove unnecessary include files
  intel_idle: Add a new flag to initialize the AMX state
  x86/fpu: Add a helper to prepare AMX state for low-power CPU idle
  x86/mm/tlb: Ignore f->new_tlb_gen when zero
  irqdomain: Use hwirq_max instead of revmap_size for NOMAP domains
  irqdomain: Report irq number for NOMAP domains
  arm64: defconfig: Add Nuvoton NPCM family support
  arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
  arm64: dts: nuvoton: Add initial NPCM8XX device tree
  arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
  dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
  dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
  dt-bindings: arm: npcm: Add maintainer
  reset: npcm: Add NPCM8XX support
  dt-bindings: reset: npcm: Add support for NPCM8XX
  reset: npcm: using syscon instead of device data
  ARM: dts: nuvoton: add reset syscon property
  dt-bindings: reset: npcm: add GCR syscon property
  dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
  dt-bindings: watchdog: npcm: Add npcm845 compatible string
  dt-bindings: timer: npcm: Add npcm845 compatible string
  arm64: marvell: enable the 98DX2530 pinctrl driver
  arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board
  irqchip/gic-v3: Fix comment typo
  dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/V2L SoC
  arm64: dts: qcom: sdm845-db845c: Specify a i2c bus clocks
  arm64: dts: qcom: sdm845-db845c: Enable gpi_dma1
  arm64: dts: qcom: sdm845: Fill in GENI DMA references
  skbuff: add SKBFL_DONT_ORPHAN flag
  skbuff: don't mix ubuf_info from different sources
  ipv6: avoid partial copy for zc
  ipv4: avoid partial copy for zc
  ARM: dts: qcom: add rpmcc missing clocks for apq/ipq8064 and msm8660
  arm64: dts: qcom: sc7280: delete vdda-1p2 and vdda-0p9 from both dp and edp
  arm64: defconfig: Demote Qualcomm USB PHYs to modules
  arm64: dts: sdm850: Remove unnecessary turbo-mode
  ARM: mach-qcom: Add support for MSM8909
  dt-bindings: arm: cpus: Document "qcom,msm8909-smp" enable-method
  soc: qcom: spm: Add CPU data for MSM8909
  dt-bindings: soc: qcom: spm: Add MSM8909 CPU compatible
  soc: qcom: rpmpd: Add compatible for MSM8909
  dt-bindings: power: qcom-rpmpd: Add MSM8909 power domains
  soc: qcom: smd-rpm: Add compatible for MSM8909
  dt-bindings: soc: qcom: smd-rpm: Add MSM8909
  arm64: dts: qcom: sc8280xp: add missing 300MHz
  soc: qcom: icc-bwmon: Remove unnecessary print function dev_err()
  clocksource/drivers/sh_cmt: Add R-Car Gen4 support
  dt-bindings: timer: renesas,cmt: R-Car V3U is R-Car Gen4
  dt-bindings: timer: renesas,cmt: Add r8a779f0 and generic Gen4 CMT support
  mmc: fix disk/queue leak in case of adding disk failure
  ublk_drv: fix an IS_ERR() vs NULL check
  ublk: remove UBLK_IO_F_INTEGRITY
  ublk_drv: remove unneeded semicolon
  ublk_drv: fix missing error return code in ublk_add_dev()
  um: seed rng using host OS rng
  random: use try_cmpxchg in _credit_init_bits
  timekeeping: contribute wall clock to rng on time change
  x86/rdrand: Remove "nordrand" flag in favor of "random.trust_cpu"
  random: remove CONFIG_ARCH_RANDOM
  spi: atmel: remove #ifdef CONFIG_{PM, SLEEP}
  spi: dt-bindings: Add compatible for MediaTek MT8188
  spi: dt-bindings: mediatek,spi-mtk-nor: Update bindings for nor flash
  regmap: permit to set reg_update_bits with bulk implementation
  soc: fujitsu: Add A64FX diagnostic interrupt driver
  dt-bindings: marvell: Document the AC5/AC5X compatibles
  ARM: dts: turris-omnia: enable LED controller node
  ARM: dts: turris-omnia: configure LED[0] pin function to link/activity
  ARM: Marvell: Update PCIe fixup
  ARM: dts: qcom: msm8974: Disable remoteprocs by default
  ARM: dts: qcom: ipq8064: add missing smem compatible
  ARM: dts: qcom: ipq8064: add missing hwlock
  ARM: dts: qcom: ipq8064: add speedbin efuse nvmem node
  ARM: dts: qcom: ipq8064: fix and add some missing gsbi node
  ARM: dts: qcom: ipq8064: reduce pci IO size to 64K
  ARM: dts: qcom: ipq8064: disable usb phy by default
  ARM: dts: qcom: ipq8064: add missing snps,dwmac compatible for gmac
  ARM: dts: qcom: ipq8064: add specific dtsi with smb208 rpm regulators
  ARM: dts: qcom: ipq8064: add gsbi6 missing definition
  ARM: dts: qcom: ipq8064: add multiple missing pin definition
  ARM: dts: qcom: msm8974-hammerhead: Add notification LED
  ARM: dts: qcom: msm8974-FP2: Add notification LED
  ARM: dts: qcom: msm8974-sony: Enable LPG
  ARM: dts: qcom: Add LPG node to pm8941
  ARM: dts: qcom: sdx65: reorder USB interrupts
  arm64: dts: qcom: reorder USB interrupts
  arm64: dts: qcom: sc7280: reorder USB interrupts
  arm64: dts: qcom: sc8280xp: fix USB interrupts
  arm64: dts: qcom: sc8280xp: fix USB clock order and naming
  arm64: dts: qcom: sc8280xp: fix usb_1 ssphy irq
  arm64: dts: qcom: sc8280xp: Fix PMU interrupt
  arm64: dts: qcom: sc8280xp: fix the smmu interrupt values
  arm64: dts: qcom: qcs404: Fix incorrect USB2 PHYs assignment
  arm64: dts: qcom: sc7280: drop unused clocks from eDP node
  arm64: dts: qcom: sc7280: drop address/size-cells from eDP node
  arm64: dts: qcom: sc7280: drop #clock-cells from displayport-controller
  arm64: dts: qcom: sc7280: split register block for DP controller
  arm64: dts: qcom: sc7180: drop #clock-cells from displayport-controller
  arm64: dts: qcom: sc7180: split register block for DP controller
  arm64: dts: qcom: sc7280: Move wcd specific pin conf to common file
  arm64: dts: qcom: msm8998: Make regulator voltages multiple of step-size
  arm64: dts: qcom: sm6350: Replace literal rpmhpd indices with constants
  arm64: dts: qcom: ipq8074: add interrupt-parent to DTSI
  arm64: dts: qcom: ipq8074: add #size/address-cells to DTSI
  arm64: dts: qcom: sm8250: rename DPU device node
  arm64: dts: qcom: sc7180: rename DPU device node
  arm64: dts: qcom: sdm845: rename DPU device node
  arm64: dts: qcom: ipq8074: add APCS node
  soc: qcom: socinfo: Fix the id of SA8540P SoC
  soc: qcom: Make QCOM_RPMPD depend on PM
  fs: remove no_llseek
  fs: check FMODE_LSEEK to control internal pipe splicing
  vfio: do not set FMODE_LSEEK flag
  dma-buf: remove useless FMODE_LSEEK flag
  fs: do not compare against ->llseek
  fs: clear or set FMODE_LSEEK based on llseek function
  ublk_drv: fix build warning with -Wmaybe-uninitialized and one sparse warning
  pinctrl: ocelot: Make irq_chip immutable
  fs-verity: mention btrfs support
  clocksource/drivers/timer-microchip-pit64b: Fix compilation warnings
  clocksource/drivers/timer-microchip-pit64b: Use mchp_pit64b_{suspend, resume}
  clocksource/drivers/timer-microchip-pit64b: Remove suspend/resume ops for ce
  thermal/drivers/rcar_gen3_thermal: Add r8a779f0 support
  clocksource/drivers/timer-mediatek: Implement CPUXGPT timers
  dt-bindings: timer: mediatek: Add CPUX System Timer and MT6795 compatible
  clocksource/drivers/timer-tegra186: Add support for Tegra234 SoC
  clocksource: Add Tegra186 timers support
  clocksource/drivers/arm_global_timer: Fix Kconfig "its" grammar
  dt-bindings: arm: Add Asus GT-AX6000 based on BCM4912
  dm thin: fix use-after-free crash in dm_sm_register_threshold_callback
  ARM: bcmbca: Include full family name in Kconfig
  arm64: bcmbca: Include full family name in Kconfig
  arm64: make ARCH_BCM4908 select ARCH_BCMBCA
  dt-bindings: PCI: qcom: Fix reset conditional
  dt-bindings: PCI: qcom: Fix description typo
  PCI: qcom: Add IPQ60xx support
  PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_*
  PCI: dwc: Move GEN3_RELATED DBI definitions to common header
  PCI: qcom: Drop manual pipe_clk_src handling
  Revert "ovl: turn of SB_POSIXACL with idmapped layers temporarily"
  ovl: handle idmappings in ovl_get_acl()
  acl: make posix_acl_clone() available to overlayfs
  acl: port to vfs{g,u}id_t
  acl: move idmapped mount fixup into vfs_{g,s}etxattr()
  mnt_idmapping: add vfs[g,u]id_into_k[g,u]id()
  blktrace: Fix the blk_fill_rwbs() kernel-doc header
  fs/buffer: Fix the ll_rw_block() kernel-doc header
  LSM: SafeSetID: add setgroups() testing to selftest
  LSM: SafeSetID: Add setgroups() security policy handling
  security: Add LSM hook to setgroups() syscall
  ACPI: video: Use native backlight on Dell Inspiron N4010
  ACPI: PM: s2idle: Use LPS0 idle if ACPI_FADT_LOW_POWER_S0 is unset
  Revert "ACPI / PM: LPIT: Register sysfs attributes based on FADT"
  hwmon: (mcp3021) improve driver support for newer hwmon interface
  LSM: SafeSetID: add GID testing to selftest
  LSM: SafeSetID: selftest cleanup and prepare for GIDs
  LSM: SafeSetID: fix userns bug in selftest
  pm-graph v5.9
  cpufreq: Warn users while freeing active policy
  cpufreq: scmi: Support the power scale in micro-Watts in SCMI v3.1
  firmware: arm_scmi: Get detailed power scale from perf
  Documentation: EM: Switch to micro-Watts scale
  PM: EM: convert power field to micro-Watts precision and align drivers
  kexec, KEYS, s390: Make use of built-in and secondary keyring for signature verification
  arm64: kexec_file: use more system keyrings to verify kernel image signature
  kexec, KEYS: make the code in bzImage64_verify_sig generic
  kexec: clean up arch_kexec_kernel_verify_sig
  kexec: drop weak attribute from functions
  kexec_file: drop weak attribute from functions
  regulator: of: Fix refcount leak bug in of_get_regulation_constraints()
  crypto: lib - make the sha1 library optional
  crypto: lib - move lib/sha1.c into lib/crypto/
  crypto: fips - make proc files report fips module name and version
  crypto: x86/blowfish - remove redundant assignment to variable nytes
  crypto: sa2ul - Check engine status before enabling
  crypto: sa2ul - Set the supported_algos bits individually
  crypto: atmel-tdes - initialize tdes_dd while declaring
  crypto: atmel-sha - initialize sha_dd while declaring
  crypto: caam/qi2 - switch to netif_napi_add_tx_weight()
  crypto: s5p-sss - Drop if with an always false condition
  crypto: omap-sham - Drop if with an always false condition
  crypto: omap-des - Drop if with an always false condition
  crypto: omap-aes - Drop if with an always false condition
  crypto: atmel-tdes - Drop if with an always false condition
  crypto: atmel-sha - Drop if with an always false condition
  crypto: atmel-aes - Drop if with an always false condition
  crypto: ccree - Add missing clk_disable_unprepare() in cc_pm_resume()
  crypto: testmgr - add ARIA testmgr tests
  crypto: aria - Implement ARIA symmetric cipher algorithm
  PM / devfreq: tegra30: Add error message for devm_devfreq_add_device()
  PM / devfreq: imx-bus: use NULL to pass a null pointer rather than zero
  PM / devfreq: shut up kernel-doc warnings
  dt-bindings: interconnect: samsung,exynos-bus: convert to dtschema
  PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
  dt-bindings: interconnect: Add MediaTek CCI dt-bindings
  doc/zh_CN: remove submitting-driver reference from docs
  docs: zh_TW: align to submitting-drivers removal
  docs: zh_CN: align to submitting-drivers removal
  docs: ko_KR: howto: remove reference to removed submitting-drivers
  docs: ja_JP: howto: remove reference to removed submitting-drivers
  docs: it_IT: align to submitting-drivers removal
  docs: process: remove outdated submitting-drivers.rst
  docs: admin: devices: drop confusing outdated statement on Latex
  docs: kernel-docs: add a reference mentioned in submitting-drivers.rst
  docs: kernel-docs: reflect that it is community-maintained
  docs: kernel-docs: shorten the lengthy doc title
  docs: kernel-docs: order reference from newest to oldest
  arm64: dts: Add base DTS file for bcmbca device Asus GT-AX6000
  selftests/landlock: drop deprecated headers dependency
  selftests: timers: clocksource-switch: adapt to kselftest framework
  selftests: timers: clocksource-switch: add 'runtime' command line parameter
  selftests: timers: clocksource-switch: add command line switch to skip sanity check
  selftests: timers: clocksource-switch: sort includes
  selftests: timers: clocksource-switch: fix passing errors from child
  selftests: timers: inconsistency-check: adapt to kselftest framework
  selftests: timers: nanosleep: adapt to kselftest framework
  selftests: timers: fix declarations of main()
  selftests: timers: valid-adjtimex: build fix for newer toolchains
  ARM: bcm: NSP: Removed forced thermal selection
  PCI: loongson: Don't access non-existent devices
  PCI: loongson: Add ACPI init support
  dm writecache: count number of blocks discarded, not number of discard bios
  dm writecache: count number of blocks written, not number of write bios
  dm writecache: count number of blocks read, not number of read bios
  dm writecache: return void from functions
  dm kcopyd: use __GFP_HIGHMEM when allocating pages
  dm writecache: set a default MAX_WRITEBACK_JOBS
  PM: domains: Ensure genpd_debugfs_dir exists before remove
  ACPI: video: Shortening quirk list by identifying Clevo by board_name only
  ACPI: video: Force backlight native for some TongFang devices
  regulator: pwm: Update Lee Jones' email address
  regulator: max597x: Don't return uninitialized variable in .probe
  fs/zonefs: Use the enum req_op type for tracing request operations
  fs/xfs: Use the enum req_op and blk_opf_t types
  PM: Use the enum req_op and blk_opf_t types
  fs/ocfs2: Use the enum req_op and blk_opf_t types
  fs/ntfs3: Use enum req_op where appropriate
  fs/nilfs2: Use the enum req_op and blk_opf_t types
  fs/nfs: Use enum req_op where appropriate
  fs/jbd2: Fix the documentation of the jbd2_write_superblock() callers
  fs/iomap: Use the new blk_opf_t type
  fs/hfsplus: Use the enum req_op and blk_opf_t types
  fs/gfs2: Use the enum req_op and blk_opf_t types
  fs/f2fs: Use the enum req_op and blk_opf_t types
  fs/ext4: Use the new blk_opf_t type
  fs/btrfs: Use the enum req_op and blk_opf_t types
  fs/mpage: Use the new blk_opf_t type
  fs/direct-io: Reduce the size of struct dio
  fs/buffer: Combine two submit_bh() and ll_rw_block() arguments
  fs/buffer: Use the new blk_opf_t type
  mm: Use the new blk_opf_t type
  scsi/target: Use the new blk_opf_t type
  scsi/ufs: Rename a 'dir' argument into 'op'
  scsi/device_handlers: Use the new blk_opf_t type
  scsi/core: Use the new blk_opf_t type
  scsi/core: Change the return type of scsi_noretry_cmd() into bool
  scsi/core: Improve static type checking
  nvme/target: Use the new blk_opf_t type
  nvme/host: Use the enum req_op and blk_opf_t types
  md/raid5: Use the enum req_op and blk_opf_t types
  md/raid10: Use the new blk_opf_t type
  md/raid1: Use the new blk_opf_t type
  md/bcache: Combine two prio_io() arguments
  md/bcache: Combine two uuid_io() arguments
  md/core: Combine two sync_page_io() arguments
  dm/dm-zoned: Use the enum req_op type
  dm/zone: Use the enum req_op type
  dm-snap: Combine request operation type and flags
  dm mirror log: Use the new blk_opf_t type
  dm/dm-integrity: Combine request operation and flags
  dm/dm-flakey: Use the new blk_opf_t type
  dm/ebs: Change 'int rw' into 'enum req_op op'
  dm/core: Combine request operation type and flags
  dm/core: Rename kcopyd_job.rw into kcopyd.op
  dm/core: Reduce the size of struct dm_io_request
  um: Use enum req_op where appropriate
  nvdimm-btt: Use the enum req_op type
  block/zram: Use enum req_op where appropriate
  xen-blkback: Use the enum req_op and blk_opf_t types
  block/rnbd: Use blk_opf_t where appropriate
  block/floppy: Fix a sparse warning
  block/drbd: Combine two drbd_submit_peer_request() arguments
  block/drbd: Use the enum req_op and blk_opf_t types
  block/brd: Use the enum req_op type
  blktrace: Use the new blk_opf_t type
  blktrace: Trace remapped requests correctly
  block/kyber: Use the new blk_opf_t type
  block/mq-deadline: Use the new blk_opf_t type
  block/bfq: Use the new blk_opf_t type
  block: Use the new blk_opf_t type
  block: Introduce the type blk_opf_t
  block: Change the type of req_op() and bio_op() into enum req_op
  block: Change the type of the last .rw_page() argument
  block: Use enum req_op where appropriate
  treewide: Rename enum req_opf into enum req_op
  PCI: loongson: Use generic 8/16/32-bit config ops on LS2K/LS7A
  PCI/ACPI: Guard ARM64-specific mcfg_quirks
  PCI: qcom: Remove unnecessary pipe_clk handling
  kunit: executor: Fix a memory leak on failure in kunit_filter_tests
  clk: explicitly disable CONFIG_UML_PCI_OVER_VIRTIO in .kunitconfig
  block: remove bdevname
  ext4: only initialize mmp_bdevname once
  ocfs2/cluster: remove the hr_dev_name field from struct o2hb_region
  rnbd-srv: remove the name field from struct rnbd_dev
  pktcdvd: stop using bdevname in pkt_new_dev
  pktcdvd: stop using bdevname in pkt_seq_show
  drbd: stop using bdevname in drbd_report_io_error
  block: stop using bdevname in __blkdev_issue_discard
  block: stop using bdevname in bdev_write_inode
  ublk_drv: fix request queue leak
  ublk_drv: support to complete io command via task_work_add
  ublk_drv: add io_uring based userspace block driver
  spi: dt-bindings: atmel,at91rm9200-spi: convert to json-schema
  ARM: dts: qcom: apq8064: create tsens device node
  arm64: defconfig: Enable Qualcomm SC8280XP providers
  arm64: dts: qcom: sc8280xp: Add lost ranges for timer
  docs/zh_CN: Add a new translation of reporting-regressions.rst
  Documentation: hyperv: Add overview of clocks and timers
  Documentation: hyperv: Add overview of VMbus
  Documentation: hyperv: Add overview of Hyper-V enlightenments
  Documentation/translations/zh_CN/mm/page_owner.rst: adjust some words
  docs/zh_CN: core-api: Add watch_queue Chinese translation
  Documentation: siphash: Fix typo in the name of offsetofend macro
  MAINTAINERS: mark linux-doc-tw-discuss mailing list moderated
  PCI: qcom: Power on PHY before DBI register accesses
  PCI: qcom: Power on PHY before IPQ8074 DBI register accesses
  PCI: qcom: Set up rev 2.1.0 PARF_PHY before enabling clocks
  PCI/AER: Iterate over error counters instead of error strings
  PCI/AER: Enable error reporting when AER is native
  PCI/portdrv: Don't disable AER reporting in get_port_device_capability()
  hwmon: (asus-ec-sensors) add definitions for ROG ZENITH II EXTREME
  hwmon: (aquacomputer_d5next) Move device-specific data into struct aqc_data
  hwmon: (asus-ec-sensors) add missing sensors for X570-I GAMING
  hwmon: (drivetemp) Add module alias
  hwmon: (asus_wmi_sensors) Save a few bytes of memory
  hwmon: (lm90) Use worker for alarm notifications
  hwmon: (asus-ec-sensors) add support for Maximus XI Hero
  hwmon: (dell-smm) Improve assembly code
  hwmon: (pmbus/ltc2978) Set voltage resolution
  hwmon: (pmbus) Add list_voltage to pmbus ops
  hwmon: (pmbus) Introduce and use cached vout margins
  hwmon: (gsc-hwmon) Add missing of_node_put()
  hwmon: (dell-smm) Add Dell G5 5590 to DMI table
  hwmon: (dell-smm) Add Dell XPS 13 7390 to fan control whitelist
  hwmon: (nct6775) Drop duplicate NULL check in ->init() and ->exit()
  hwmon: (pmbus) fix build error unused-function
  hwmon: (lm90) Read the channel's temperature offset from device-tree
  hwmon: (lm90) Add support for 2nd remote channel's offset register
  hwmon: (occ) Delete unnecessary NULL check
  hwmon: (lm90) Read the channel's label from device-tree
  hwmon: (lm90) Define maximum number of channels that are supported
  hwmon: (lm90) Add compatible entry for adt7481
  dt-bindings: hwmon: Allow specifying channels for lm90
  dt-bindings: hwmon: Add compatible string for ADT7481 in lm90
  hwmon: Allow to compile ASB100 and FSCHMD on !X86
  hwmon: (pmbus) add MFR_* registers to debugfs
  hwmon: (pmbus) add a function to check the presence of a block register
  hwmon: (asus-ec-sensors) add support for Strix Z690-a D4
  hwmon: (sch56xx-common) Add DMI override table
  hwmon: (lm75) Replace kernel.h with the necessary inclusions
  hwmon: (f71882fg) Add support for F71858AD (0x0903)
  hwmon: (pmbus) Add support for Analog Devices LT7182S
  dt-bindings: trivial-devices: Add lt7182s
  hwmon: (pmbus) Add IEEE 754 half precision support to PMBus core
  hwmon: (lm90) Support temp_samples attribute
  hwmon: (lm90) Add table with supported Analog/ONSEMI devices
  hwmon: (lm90) Add support and detection of Philips/NXP NE1618
  hwmon: (lm90) Add explicit support for ADM1020
  hwmon: (lm90) Only disable alerts if not already disabled
  hwmon: (lm90) Add support for ADT7421
  hwmon: (lm90) Add support for ON Semiconductor NCT218
  hwmon: (lm90) Add support for ON Semiconductor NCT214 and NCT72
  hwmon: (lm90) Add explicit support for NCT210
  hwmon: (lm90) Combine lm86 and lm90 configuration
  hwmon: (lm90) Add remaining chips supported by adm1021 driver
  hwmon: (lm90) Add support for ADM1021, ADM1021A, and ADM1023
  hwmon: (lm90) Support MAX1617 and LM84
  hwmon: (lm90) Introduce 16-bit register write function
  hwmon: (lm90) Let lm90_read16() handle 8-bit read operations
  hwmon: (lm90) Add support for MAX6642
  hwmon: (lm90) Add flag to indicate conversion rate support
  hwmon: (lm90) Add flag to indicate support for minimum temperature limits
  hwmon: (lm90) Add support for MAX6690
  hwmon: (lm90) Strengthen chip detection for ADM1032, ADT7461(A), and NCT1008
  hwmon: (lm90) Add support for ADT7481, ADT7482, and ADT7483
  hwmon: (lm90) Add explicit support for MAX6648/MAX6692
  hwmon: (lm90) Add flag to indicate 'alarms' attribute support
  hwmon: (lm90) Fix/Add detection of G781-1
  hwmon: (lm90) Add support for additional chip revision of NCT1008
  hwmon: (lm90) Rework detect function
  hwmon: (lm90) Use single flag to indicate extended temperature support
  hwmon: (lm90) Support multiple temperature resolutions
  hwmon: (lm90) Only re-read registers if volatile
  hwmon: (lm90) Add support for unsigned and signed temperatures
  hwmon: (lm90) Enable full PEC support for ADT7461A
  hwmon: (lm90) Add partial PEC support for ADT7461
  hwmon: (lm90) Improve PEC support
  hwmon: (lm90) Stop using R_/W_ register prefix
  hwmon: (lm90) Move status register bit shifts to compile time
  hwmon: (lm90) Use BIT macro
  hwmon: (lm90) Reorder chip enumeration to be in alphabetical order
  hwmon: (lm90) Reorder include files in alphabetical order
  hwmon: (lm90) Rework alarm/status handling
  hwmon: (lm90) Generate sysfs and udev events for all alarms
  hwmon: (pmbus) Move pec attribute to I2C device
  evm: Use IS_ENABLED to initialize .enabled
  spi: tegra20-slink: fix UAF in tegra_slink_remove()
  spi: Fix simplification of devm_spi_register_controller
  spi: microchip-core: switch to use dev_err_probe()
  spi: microchip-core: switch to use devm_spi_alloc_master()
  spi: microchip-core: fix UAF in mchp_corespi_remove()
  spi: dw: Add support for Intel Thunder Bay SPI controller
  spi: dw: Add support for master mode selection for DWC SSI controller
  spi: Add bindings for Intel Thunder Bay SOC
  spi: dw: Fix IP-core versions macro
  sched/core: Always flush pending blk_plug
  sched/fair: fix case with reduced capacity CPU
  blk-cgroup: Use atomic{,64}_try_cmpxchg
  blk-iolatency: Use atomic{,64}_try_cmpxchg
  block: Use try_cmpxchg in update_io_ticks
  block/rq_qos: Use atomic_try_cmpxchg in atomic_inc_below
  thermal: intel: x86_pkg_temp_thermal: Drop duplicate 'is' from comment
  PCI/ASPM: Unexport pcie_aspm_support_enabled()
  PCI: endpoint: Enable DMA tests for endpoints with DMA capabilities
  PCI/ASPM: Remove pcie_aspm_pm_state_change()
  blk-mq: don't create hctx debugfs dir until q->debugfs_dir is created
  m68k: defconfig: Update defconfigs for v5.19-rc1
  m68k: Add common forward declaration for show_registers()
  m68k: mac: Remove forward declaration for mac_nmi_handler()
  ARM: dts: kswitch-d10: enable the USB device port
  Makefile: add headers_install to kselftest targets
  selftests: drop KSFT_KHDR_INSTALL make target
  selftests: stop using KSFT_KHDR_INSTALL
  selftests: drop khdr make target
  PCI/doc: Convert examples to generic power management
  mmc: sdhci-of-aspeed: test: Use kunit_test_suite() macro
  nitro_enclaves: test: Use kunit_test_suite() macro
  thunderbolt: test: Use kunit_test_suite() macro
  kunit: flatten kunit_suite*** to kunit_suite** in .kunit_test_suites
  kunit: unify module and builtin suite definitions
  selftest: Taint kernel when test module loaded
  module: panic: Taint the kernel when selftest modules load
  Documentation: kunit: fix example run_kunit func to allow spaces in args
  PCI/AER: Configure ECRC for every device
  tty: serial: bcm63xx: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA
  spi: bcm63xx-hsspi: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA
  spi: remove duplicate parameters check in acpi_spi_add_resource()
  spi: propagate error code to the caller of acpi_spi_device_alloc()
  spi: Return deferred probe error when controller isn't yet available
  regulator: qcom,spmi-regulator: add PMP8074 PMIC
  regulator: qcom,spmi-regulator: Convert to dtschema
  regulator: qcom_spmi: add support for PMP8074 regulators
  regulator: qcom_spmi: add support for HT_P600
  regulator: qcom_spmi: add support for HT_P150
  regulator: max597x: Remove unused including <linux/version.h>
  genirq: Allow irq_set_chip_handler_name_locked() to take a const irq_chip
  gpio: thunderx: Don't directly include asm-generic/msi.h
  x86/setup: Use rng seeds from setup_data
  x86/build: Remove unused OBJECT_FILES_NON_STANDARD_test_nx.o
  x86/Kconfig: Fix CONFIG_CC_HAS_SANE_STACKPROTECTOR when cross compiling with clang
  clk: bcm: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA
  hwrng: bcm2835: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA
  IDR: Note that the IDR API is deprecated
  XArray: Add calls to might_alloc()
  irqchip/sifive-plic: Separate the enable and mask operations
  irqchip/sifive-plic: Make better use of the effective affinity mask
  pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt
  dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document the properties to handle GPIO IRQ
  gpio: gpiolib: Allow free() callback to be overridden
  irqchip: Add RZ/G2L IA55 Interrupt Controller driver
  dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller
  gpio: Remove dynamic allocation from populate_parent_alloc_arg()
  arm64: dts: allwinner: h616: Add X96 Mate TV box support
  arm64: dts: allwinner: h616: Add OrangePi Zero 2 board support
  dt-bindings: arm: sunxi: Add two H616 board compatible strings
  dt-bindings: pinctrl: sunxi: allow vcc-pi-supply
  arm64: dts: allwinner: Add Allwinner H616 .dtsi file
  dt-bindings: pinctrl: sunxi: Make interrupts optional
  dt-bindings: arm: sunxi: Add H616 EMAC0 compatible
  arm64: dts: freescale: add initial device tree for TQMa8MPQL with i.MX8MP
  dt-bindings: arm: add TQMa8MPxL board
  arm64: dts: qcom: sc8280xp: fix DP PHY node unit addresses
  arm64: dts: qcom: sc8280xp: fix usb_0 HS PHY ref clock
  phy: brcm-sata: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA
  i2c: brcmstb: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA
  ata: ahci_brcm: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA
  ARM: debug: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA
  arm: bcmbca: Add BCMBCA sub platforms
  arm: bcmbca: Move BCM63138 ARCH_BCM_63XX to ARCH_BCMBCA
  arm64: dts: qcom: sc7280: fix PCIe clock reference
  ARM: multi_v7_defconfig: Update configs for BCM63138
  MAINTAINERS: Move BCM63138 to bcmbca arch entry
  docs: arm: index.rst: add google/chromebook-boot-flow
  ARM: dts: Add BCM63138 generic board dts
  ARM: dts: update dts files for bcmbca SoC BCM63138
  ARM: dts: Move BCM963138DVT board dts to ARCH_BCMBCA
  dt-bindings: arm: add BCM63138 SoC
  MAINTAINERS: update the LSM maintainer info
  PM: runtime: Extend support for wakeirq for force_suspend|resume
  Documentation: PM: Drop pme_interrupt reference
  x86: mm: refer to the intended config STRICT_DEVMEM in a comment
  dm: verity-loadpin: Use CONFIG_SECURITY_LOADPIN_VERITY for conditional compilation
  LoadPin: Enable loading from trusted dm-verity devices
  dm: Add verity helpers for LoadPin
  Documentation: kunit: Cleanup run_wrapper, fix x-ref
  kunit: test.h: fix a kernel-doc markup
  kunit: tool: Enable virtio/PCI by default on UML
  kunit: tool: make --kunitconfig repeatable, blindly concat
  selftests: drivers/dma-buf: Improve message in selftest summary
  selftests/kcmp: Make the test output consistent and clear
  arm64: dts: allwinner: pinephone: Enable internal HMIC bias
  dt-bindings: arm: sunxi: Add several MBUS compatibles
  dt-bindings: arm: sunxi: Default to the full MBUS binding
  arm64: tegra: Fix SDMMC1 CD on P2888
  arm64: tegra: Update compatible for Tegra234 GPCDMA
  arm64: tegra: Add Host1x and VIC on Tegra234
  arm64: tegra: Add Host1x context stream IDs on Tegra186+
  arm64: tegra: Enable native timers on Tegra234
  arm64: tegra: Enable native timers on Tegra194
  arm64: tegra: Enable native timers on Tegra186
  arm64: tegra: Add node for CBB 2.0 on Tegra234
  arm64: tegra: Add node for CBB 1.0 on Tegra194
  arm64: tegra: Align gpio-keys node names with dtschema
  arm64: tegra: Mark BPMP channels as no-memory-wc
  arm64: tegra: Add Tegra234 GPCDMA device tree node
  arm64: tegra: Adjust whitespace around '='
  arm64: tegra: Enable OPE on various platforms
  arm64: tegra: Add OPE device on Tegra210 and later
  firmware: tegra: Fix error check return value of debugfs_create_file()
  dt-bindings: tegra-ccplex-cluster: Remove status from required properties
  dt-bindings: Add headers for Host1x and VIC on Tegra234
  dt-bindings: timer: Add Tegra186 & Tegra234 Timer
  ARM: dts: Add Sunplus SP7021-Demo-V3 board device tree
  ARM: sp7021_defconfig: Add Sunplus SP7021 defconfig
  ARM: sunplus: Add initial support for Sunplus SP7021 SoC
  irqchip: Add Sunplus SP7021 interrupt controller driver
  dt-bindings: interrupt-controller: Add bindings for SP7021 interrupt controller
  dt-bindings: clock: Add bindings for SP7021 clock driver
  reset: Add Sunplus SP7021 reset driver
  dt-bindings: reset: Add bindings for SP7021 reset driver
  dt-bindings: arm: sunplus: Add bindings for Sunplus SP7021 SoC boards
  regmap: add WARN_ONCE when invalid mask is provided to regmap_field_init()
  arm64: dts: freescale: imx8qxp: Fix the keys node name
  arm64: dts: freescale: imx8: Fix the system-controller node name
  arm64: dts: freescale: imx8qxp: Fix the ocotp node name
  arm64: dts: freescale: imx8qxp: Add fallback compatible for clock controller
  arm64: dts: freescale: imx8: Fix power controller name
  arm64: dts: freescale: imx8qxp: Remove unnecessary clock related entries
  dt-bindings: firmware: Add fsl,scu yaml file
  dt-bindings: watchdog: Add fsl,scu-wdt yaml file
  dt-bindings: thermal: Add fsl,scu-thermal yaml file
  dt-bindings: rtc: Add fsl,scu-rtc yaml file
  dt-bindings: power: Add fsl,scu-pd yaml file
  dt-bindings: nvmem: Add fsl,scu-ocotp yaml file
  dt-bindings: input: Add fsl,scu-key yaml file
  dt-bindings: pinctrl: imx: Add fsl,scu-iomux yaml file
  dt-bindings: clk: imx: Add fsl,scu-clk yaml file
  memory: tegra: Add MGBE memory clients for Tegra234
  soc: mediatek: mutex: Simplify with devm_platform_get_and_ioremap_resource()
  soc: mediatek: pm-domains: Add support for Helio X10 MT6795
  dt-bindings: power: Add MediaTek Helio X10 MT6795 power domains
  dt-bindings: arm: tegra: Add NVIDIA Tegra234 CBB 2.0 binding
  dt-bindings: arm: tegra: Add NVIDIA Tegra194 AXI2APB binding
  dt-bindings: arm: tegra: Add NVIDIA Tegra194 CBB 1.0 binding
  dt-bindings: memory: Add Tegra234 MGBE memory clients
  dt-bindings: Add Tegra234 MGBE clocks and resets
  dt-bindings: power: Add Tegra234 MGBE power domains
  arm64: dts: imx8mp: add NoC node
  PCI: hv: Take a const cpumask in hv_compose_msi_req_get_cpu()
  crypto: testmgr - populate RSA CRT parameters in RSA test vectors
  crypto: inside-secure - fix packed bit-field result descriptor
  crypto: hisilicon - Kunpeng916 crypto driver don't sleep when in softirq
  crypto: hisilicon/sec - don't sleep when in softirq
  crypto: hisilicon/sec - fix inconsistent argument
  crypto: nx - Hold the reference returned by of_find_compatible_node
  crypto: amcc - Hold the reference returned by of_find_compatible_node
  crypto: vmx - Fix warning on p8_ghash_alg
  crypto: qat - expose device config through sysfs for 4xxx
  crypto: qat - relocate and rename adf_sriov_prepare_restart()
  crypto: qat - change behaviour of adf_cfg_add_key_value_param()
  crypto: qat - expose device state through sysfs for 4xxx
  kunit: add coverage_uml.config to enable GCOV on UML
  kunit: tool: refactor internal kconfig handling, allow overriding
  kunit: tool: introduce --qemu_args
  kunit: tool: simplify creating LinuxSourceTreeOperations
  kunit: tool: cosmetic: don't specify duplicate kernel cmdline options
  kunit: tool: refactoring printing logic into kunit_printer.py
  kunit: tool: redo how we construct and mock LinuxSourceTree
  kunit: tool: drop unused load_config argument
  kunit: use kmemdup in kunit_filter_tests(), take suite as const
  MAINTAINERS: update nvidia,tegra20-host1x.yaml reference
  dt-bindings: mfd: update dlg,da9063.yaml reference
  tegra194-hte.rst: fix reference to its binding
  arch: m68k: q40: README: drop references to IDE driver
  objtool: update objtool.txt references
  Documentation: KVM: update s390-diag.rst reference
  Documentation: KVM: update msr.rst reference
  Documentation: KVM: update amd-memory-encryption.rst references
  Documentation: KVM: update s390-pv.rst reference
  Documentation: update watch_queue.rst references
  docs: zh_CN/vm/zsmalloc.rst: fix a typo
  docs: zh_CN/vm: fix a typo for page reporting ReST file
  docs: zh_CN: fix a broken reference
  docs: zh_CN/devicetree: fix typos
  docs: zh_CN: page_frags.rst: fix a broken reference
  docs: filesystems: update netfs-api.rst reference
  docs: netdev: update maintainer-netdev.rst reference
  docs: automarkup: do not look up symbols twice
  docs: automarkup: track failed cross-reference attempts
  docs: tegra194-hte.rst: don't include gpiolib.c twice
  scripts: sphinx-pre-install: place a warning for Sphinx >= 3.0
  scripts: sphinx-pre-install: provide both venv and package installs
  scripts: sphinx-pre-install: check for PDF min version later on
  scripts: sphinx-pre-install: report broken venv
  scripts: sphinx-pre-install: fix venv version check logic
  Documentation: dm writecache: Render status list as list
  Documentation: dm writecache: add blank line before optional parameters
  x86/mm: Refer to the intended config STRICT_DEVMEM in a comment
  dm snapshot: fix typo in snapshot_map() comment
  dm raid: remove redundant "the" in parse_raid_params() comment
  dm cache: fix typo in 2 comment blocks
  dm verity: fix checkpatch close brace error
  dm table: rename dm_target variable in dm_table_add_target()
  dm table: audit all dm_table_get_target() callers
  dm table: remove dm_table_get_num_targets() wrapper
  dm: add two stage requeue mechanism
  dm: add dm_bio_rewind() API to DM core
  arm64: dts: mt8183: Add panel rotation
  arm64: dts: mt7622: fix BPI-R64 WPS button
  arm64: dts: mt8173: Fix nor_flash node
  arm64: dts: mediatek: cherry: Add I2C-HID touchscreen on I2C4
  arm64: dts: mediatek: cherry: Enable support for the SPI NOR flash
  arm64: dts: mediatek: cherry: Enable MT6360 sub-pmic on I2C7
  arm64: dts: mediatek: cherry: Enable T-PHYs and USB XHCI controllers
  arm64: dts: mediatek: cherry: Enable I2C and SPI controllers
  arm64: dts: mediatek: cherry: Document gpios and add default pin config
  arm64: dts: mediatek: cherry: Add support for internal eMMC storage
  arm64: dts: mediatek: cherry: Assign interrupt line to MT6359 PMIC
  arm64: dts: mediatek: cherry: Add platform regulators layout and config
  arm64: dts: mediatek: Introduce MT8195 Cherry platform's Tomato
  dt-bindings: arm: mediatek: Add MT8195 Cherry Tomato Chromebooks
  arm64: dts: mediatek: asurada: Add SPI NOR flash memory
  arm64: dts: mediatek: asurada: Enable SCP
  arm64: dts: mediatek: asurada: Enable MMC
  arm64: dts: mediatek: asurada: Add SPMI regulators
  arm64: dts: mediatek: asurada: Add MT6359 PMIC
  arm64: dts: mediatek: asurada: Enable PCIe and add WiFi
  arm64: dts: mediatek: asurada: Enable XHCI
  arm64: dts: mediatek: spherion: Add keyboard backlight
  arm64: dts: mediatek: asurada: Add I2C touchscreen
  arm64: dts: mediatek: asurada: Add Elan eKTH3000 I2C trackpad
  arm64: dts: mediatek: asurada: Add Cr50 TPM
  arm64: dts: mediatek: asurada: Add keyboard mapping for the top row
  arm64: dts: mediatek: asurada: Add ChromeOS EC
  arm64: dts: mediatek: asurada: Enable and configure I2C and SPI busses
  arm64: dts: mediatek: asurada: Add system-wide power supplies
  arm64: dts: mediatek: asurada: Document GPIO names
  arm64: dts: mediatek: Introduce MT8192-based Asurada board family
  dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-hayato
  dt-bindings: arm64: dts: mediatek: Add mt8192-asurada-spherion
  regulator: Fix MFD_MAX597X dependency
  docs: perf: Include hns3-pmu.rst in toctree to fix 'htmldocs' WARNING
  soc: mediatek: SVS: Use DEFINE_SIMPLE_DEV_PM_OPS for svs_pm_ops
  soc: mediatek: mtk-pm-domains: Allow probing vreg supply on two MFGs
  arm64: kasan: Revert "arm64: mte: reset the page tag in page->flags"
  mm: kasan: Skip page unpoisoning only if __GFP_SKIP_KASAN_UNPOISON
  mm: kasan: Skip unpoisoning of user pages
  mm: kasan: Ensure the tags are visible before the tag in page->flags
  arm64: dts: mediatek: mt8183-kukui: Assign sram supply to mfg_async pd
  arm64: dts: renesas: Add panel overlay for Draak and Ebisu boards
  arm64: dts: renesas: Add panel overlay for Salvator-X(S) boards
  arm64: dts: renesas: Prepare AA1024XD12 panel .dtsi for overlay support
  dt-bindings: hwinfo: renesas,prr: move from soc directory
  genirq: Provide an IRQ affinity mask in non-SMP configs
  genirq: Return a const cpumask from irq_data_get_affinity_mask
  genirq: Add and use an irq_data_update_affinity helper
  genirq: Refactor accessors to use irq_data_get_affinity_mask
  genirq: Drop redundant irq_init_effective_affinity
  genirq: GENERIC_IRQ_EFFECTIVE_AFF_MASK depends on SMP
  genirq: GENERIC_IRQ_IPI depends on SMP
  irqchip/mips-gic: Only register IPI domain when SMP is enabled
  irqchip/stm32-exti: Simplify irq description table
  irqchip/stm32-exti: Read event trigger type from event_trg register
  irqchip/stm32-exti: Tag emr register as undefined for stm32mp15
  irqchip/stm32-exti: Prevent illegal read due to unbounded DT value
  irqchip/stm32-exti: Fix irq_mask/irq_unmask for direct events
  irqchip/stm32-exti: Fix irq_set_affinity return value
  genirq: Don't return error on missing optional irq_request_resources()
  arm64: dts: qcom: msm8996: clean up PCIe PHY node
  arm64: dts: qcom: msm8996: use non-empty ranges for PCIe PHYs
  arm64: dts: qcom: sm8450: drop UFS PHY clock-cells
  arm64: dts: qcom: sm8250: drop UFS PHY clock-cells
  arm64: dts: qcom: sc8280xp: drop UFS PHY clock-cells
  arm64: dts: qcom: sm8450: drop USB PHY clock index
  arm64: dts: qcom: sm8350: drop USB PHY clock index
  arm64: dts: qcom: msm8998: drop USB PHY clock index
  arm64: dts: qcom: ipq8074: drop USB PHY clock index
  arm64: dts: qcom: ipq6018: drop USB PHY clock index
  arm64: dts: qcom: sm8250: add missing PCIe PHY clock-cells
  arm64: dts: qcom: sc7280: drop PCIe PHY clock index
  Revert "arm64: dts: qcom: Fix 'reg-names' for sdhci nodes"
  arm64: dts: qcom: sc7180-idp: add vdds supply to the DSI PHY
  arm64: dts: qcom: sc7280: use constants for gpucc clocks and power-domains
  arm64: dts: qcom: msm8996: add missing DSI clock assignments
  arm64: dts: qcom: ipq8074: add reset to SDHCI
  arm64: dts: qcom: sdm845: Add CPU BWMON
  arm64: dts: qcom: ipq8074: move ARMv8 timer out of SoC node
  arm64: dta: qcom: sc7180: delete vdda-1p2 and vdda-0p9 from mdss_dp
  arm64: dts: qcom: sdm845: Switch PSCI cpu idle states from PC to OSI
  arm64: dts: qcom: extend scm compatible strings
  arm64: dts: qcom: add device tree for LG G7 and LG V35
  arm64: dts: qcom: msm8996: add xo clock source to rpmcc
  arm64: dts: qcom: msm8996: add GCC's optional clock sources
  arm64: dts: qcom: msm8996: correct #clock-cells for QMP PHY nodes
  arm64: dts: qcom: sdm845-shift-axolotl: Enable pmi9889 LPG LED
  soc: ti: pruss: Enable support for PRUSS-M subsystem on K3 AM62x SoCs
  dt-bindings: soc: ti: pruss: Update bindings for K3 AM62x SoCs
  dt-bindings: soc: ti: pruss: Re-arrange "compatible" in alphabetic order
  arm64: dts: ti: k3-am62-main: Enable crypto accelerator
  first_iovec_segment(): just return address
  arm64: dts: ti: k3-am625-sk: Enable ramoops
  arm64: dts: ti: k3-am642-sk: Add pinmux corresponding to main_uart0
  apparmor: test: Remove some casts which are no-longer required
  zonefs: Call page_address() on page acquired with GFP_KERNEL flag
  iov_iter: massage calling conventions for first_{iovec,bvec}_segment()
  iov_iter: first_{iovec,bvec}_segment() - simplify a bit
  ARM: dts: qcom: msm8974: rename GPU's OPP table node
  ARM: dts: qcom: apq8064: disable DSI and DSI PHY by default
  ARM: dts: qcom: apq8064: rename DSI PHY iface clock
  arm64: defconfig: enable Qualcomm Bandwidth Monitor
  soc: qcom: icc-bwmon: Add bandwidth monitoring driver
  dt-bindings: interconnect: qcom,msm8998-cpu-bwmon: add BWMON device
  ARM: dts: qcom: extend scm compatible to match dt-schema
  iov_iter: lift dealing with maxpages out of first_{iovec,bvec}_segment()
  arm64: dts: qcom: sm6125: Add DLL/DDR configuration on SDHCI 1/2
  arm64: dts: qcom: sm6125: Append -state suffix to pinctrl nodes
  arm64: dts: qcom: sm6125: Move sdc2 pinctrl from seine-pdx201 to sm6125
  iov_iter_get_pages{,_alloc}(): cap the maxsize with MAX_RW_COUNT
  iov_iter_bvec_advance(): don't bother with bvec_iter
  PCI: endpoint: Don't stop controller when unbinding endpoint function
  arm64: dts: qcom: db820c: Add user LEDs
  arm64: dts: qcom: pmi8994: Define MPP block
  arm64: dts: qcom: sdm845: Enable user LEDs on DB845c
  arm64: dts: qcom: Add LPG to pm8916, pm8994, pmi8994 and pmi8998
  arm64: dts: qcom: sm8350: Replace integers with rpmpd defines
  arm64: dts: qcom: sm8350: Add DISPCC node
  arm64: dts: qcom: sm8450: Add description of camera clock controller
  dt-bindings: clock: add QCOM SM8450 camera clock bindings
  dt-bindings: clock: Add Qcom SM8350 DISPCC bindings
  dt-bindings: clock: Add Qcom SM8350 GPUCC bindings
  PCI: Drop of_match_ptr() to avoid unused variables
  step_into(): move fetching ->d_inode past handle_mounts()
  lookup_fast(): don't bother with inode
  follow_dotdot{,_rcu}(): don't bother with inode
  step_into(): lose inode argument
  namei: stash the sampled ->d_seq into nameidata
  namei: move clearing LOOKUP_RCU towards rcu_read_unlock()
  dt-bindings: soc: samsung: exynos-pmu: add reboot-mode
  dt-bindings: soc: samsung: exynos-pmu: use abolute ref paths
  dt-bindings: soc: samsung: exynos-pmu: cleanup assigned clocks
  dt-bindings: samsung: document preferred compatible naming
  spi: amd: Add struct and enum kernel-doc comments
  spi: amd: Drop io_base_addr member from struct amd_spi
  spi: amd: Make use of dev_err_probe()
  spi: amd: Make use of devm_spi_alloc_master()
  block: move zone related fields to struct gendisk
  block: remove blk_queue_zone_sectors
  dm-zoned: cleanup dmz_fixup_devices
  nvmet:: use bdev based helpers in nvmet_bdev_zone_mgmt_emulate_all
  block: use bdev based helpers in blkdev_zone_mgmt{,all}
  block: replace blkdev_nr_zones with bdev_nr_zones
  block: pass a gendisk to blk_queue_max_open_zones and blk_queue_max_active_zones
  block: remove queue_max_open_zones and queue_max_active_zones
  block: pass a gendisk to blk_queue_free_zone_bitmaps
  block: pass a gendisk to blk_queue_clear_zone_settings
  block: pass a gendisk to blk_queue_set_zoned
  block: simplify blk_check_zone_append
  block: simplify blk_mq_plug
  block: use bdev_is_zoned instead of open coding it
  block: call blk_queue_free_zone_bitmaps from disk_release
  block: remove a superflous ifdef in blkdev.h
  blk-mq: Drop local variable for reserved tag
  blk-mq: Drop 'reserved' arg of busy_tag_iter_fn
  scsi: fnic: Drop reserved request handling
  blk-mq: Drop blk_mq_ops.timeout 'reserved' arg
  blk-mq: Add a flag for reserved requests
  scsi: core: Remove reserved request time-out handling
  m68k: virt: Fix missing platform_device_unregister() on error in virt_platform_init()
  m68k: virt: Use RNG seed from bootinfo block
  m68k: bitops: Change __fls to return and accept unsigned long
  m68k: Kconfig.machine: Add endif comment
  m68k: Kconfig.debug: Replace single quotes
  m68k: Kconfig.cpu: Fix indentation and add endif comments
  drivers/perf: hisi: add driver for HNS3 PMU
  drivers/perf: hisi: Add description for HNS3 PMU driver
  drivers/perf: riscv_pmu_sbi: perf format
  perf/arm-cci: Use the bitmap API to allocate bitmaps
  drivers/perf: riscv_pmu: Add riscv pmu pm notifier
  PCI: dwc-plat: Drop dw_plat_pcie_of_match[] forward declaration
  PCI: dwc-plat: Drop unused regmap pointer
  PCI: dwc-plat: Simplify dw_plat_pcie_probe() return values
  PCI: dwc: Rename struct pcie_port to dw_pcie_rp
  PCI: dwc: Move io_cfg_atu_shared to struct pcie_port
  PCI: dwc: Add start_link/stop_link inlines
  PCI: dwc: Reuse local pointer to the resource data
  PCI: dwc: Organize local variable usage
  PCI: dwc: Convert dw_pcie_link_up() to use dw_pcie_readl_dbi()
  PCI: dwc: Simplify unrolled iATU detection
  PCI: dwc: Add newlines to log messages
  PCI: dwc: Add braces to multi-line if-else statements
  PCI: dwc: Always enable CDM check if "snps,enable-cdm-check" exists
  PCI: dwc: Deallocate EPC memory on dw_pcie_ep_init() errors
  PCI: dwc: Set INCREASE_REGION_SIZE flag based on limit address
  PCI: dwc: Disable outbound windows only for controllers using iATU
  PCI: dwc: Add unroll iATU space support to dw_pcie_disable_atu()
  PCI: dwc: Stop link on host_init errors and de-initialization
  PCI: Clear PCI_STATUS when setting up device
  context_tracking: Use arch_atomic_read() in __ct_state for KASAN
  MAINTAINERS: Add Paul as context tracking maintainer
  context_tracking: Convert state to atomic_t
  rcu/context-tracking: Remove unused and/or unecessary middle functions
  rcu/context-tracking: Move RCU-dynticks internal functions to context_tracking
  rcu/context-tracking: Move deferred nocb resched to context tracking
  rcu/context_tracking: Move dynticks_nmi_nesting to context tracking
  rcu/context_tracking: Move dynticks_nesting to context tracking
  rcu/context_tracking: Move dynticks counter to context tracking
  rcu/context-tracking: Remove rcu_irq_enter/exit()
  context_tracking: Take NMI eqs entrypoints over RCU
  context_tracking: Take IRQ eqs entrypoints over RCU
  context_tracking: Take idle eqs entrypoints over RCU
  switch try_to_unlazy_next() to __legitimize_mnt()
  follow_dotdot{,_rcu}(): change calling conventions
  namei: get rid of pointless unlikely(read_seqcount_retry(...))
  __follow_mount_rcu(): verify that mount_lock remains unchanged
  soc: sunxi: mbus: Only build the driver on ARM/ARM64
  PCI: iproc: Use bitmap API to allocate bitmaps
  dt-bindings: usb: generic-ohci: Add Allwinner D1 compatible
  dt-bindings: usb: generic-ehci: Add Allwinner D1 compatible
  dt-bindings: usb: sunxi-musb: Add Allwinner D1 compatible
  arm64: dts: allwinner: a100: Update I2C controller fallback
  dt-bindings: i2c: mv64xxx: Add variants with offload support
  ARM: dts: sun8i-r40: Add thermal trip points/cooling maps
  ARM: dts: sun8i-r40: add opp table for cpu
  ARM: dts: sun8i-r40: Add "cpu-supply" node for sun8i-r40 based board
  powercap: intel_rapl: Add support for RAPTORLAKE_P
  regulator: Fix parameter declaration and spelling mistake.
  PM: wakeup: Unify device_init_wakeup() for PM_SLEEP and !PM_SLEEP
  ACPI: PM: s2idle: Add support for upcoming AMD uPEP HID AMDI008
  ACPI: VIOT: Fix ACS setup
  soc/qcom: Make QCOM_RPMPD select PM_GENERIC_DOMAINS/_OF
  regulator: max597x: Add support for max597x regulator
  arm64: mm: Remove assembly DMA cache maintenance wrappers
  regmap-irq: Fix bug in regmap_irq_get_irq_reg_linear()
  ARM: dts: aspeed: correct gpio-keys properties
  ARM: dts: aspeed: align gpio-key node names with dtschema
  arm64: errata: Add Cortex-A510 to the repeat tlbi list
  arm64/sysreg: Convert ID_AA64ZFR0_EL1 to automatic generation
  arm64/sysreg: Convert ID_AA64SMFR0_EL1 to automatic generation
  arm64/sysreg: Convert LORID_EL1 to automatic generation
  arm64/sysreg: Convert LORC_EL1 to automatic generation
  arm64/sysreg: Convert LORN_EL1 to automatic generation
  arm64/sysreg: Convert LOREA_EL1 to automatic generation
  arm64/sysreg: Convert LORSA_EL1 to automatic generation
  arm64/sysreg: Convert ID_AA64ISAR2_EL1 to automatic generation
  arm64/sysreg: Convert ID_AA64ISAR1_EL1 to automatic generation
  arm64/sysreg: Convert GMID to automatic generation
  arm64/sysreg: Convert DCZID_EL0 to automatic generation
  arm64/sysreg: Convert CTR_EL0 to automatic generation
  arm64/sysreg: Add _EL1 into ID_AA64ISAR2_EL1 definition names
  arm64/sysreg: Add _EL1 into ID_AA64ISAR1_EL1 definition names
  arm64/sysreg: Remove defines for RPRES enumeration
  arm64/sysreg: Standardise naming for ID_AA64ZFR0_EL1 fields
  arm64/sysreg: Standardise naming for ID_AA64SMFR0_EL1 enums
  arm64/sysreg: Standardise naming for WFxT defines
  arm64/sysreg: Make BHB clear feature defines match the architecture
  arm64/sysreg: Align pointer auth enumeration defines with architecture
  arm64/mte: Standardise GMID field name definitions
  arm64/sysreg: Standardise naming for DCZID_EL0 field names
  arm64/sysreg: Standardise naming for CTR_EL0 fields
  arm64/cache: Restrict which headers are included in __ASSEMBLY__
  arm64/sysreg: Add SYS_FIELD_GET() helper
  arm64/sysreg: Allow leading blanks on comments in sysreg file
  arm64/idreg: Fix tab/space damage
  arm64/cpuinfo: Remove references to reserved cache type
  arm64/mm: Define defer_reserve_crashkernel()
  arm64: dts: exynosautov9: add usi device tree nodes
  arm64: dts: exynosautov9: prepare usi0 changes
  arm64: dts: exynosautov9: add pdma0 device tree node
  dt-bindings: soc: samsung: usi: add exynosautov9-usi compatible
  arm64: dts: exynosautov9: correct spi11 pin names
  ARM: dts: stm32: Add ST MIPID02 bindings to AV96
  ARM: dts: stm32: Add alternate pinmux for RCC pin
  ARM: dts: stm32: Add alternate pinmux for DCMI pins
  ARM: dts: stm32: Add DHCOR based DRC Compact board
  ARM: dts: stm32: Add alternate pinmux for UART5 pins
  ARM: dts: stm32: Add alternate pinmux for UART4 pins
  ARM: dts: stm32: Add alternate pinmux for UART3 pins
  ARM: dts: stm32: Add alternate pinmux for SPI2 pins
  ARM: dts: stm32: Add alternate pinmux for CAN1 pins
  dt-bindings: arm: stm32: Add compatible string for DH electronics DHCOR DRC Compact
  ARM: dts: stm32: Fix SPI2 pinmux pin comments on stm32mp15
  ARM: dts: lan966x: Add UDPHS support
  dt-bindings: usb: atmel: Add Microchip LAN9662 compatible string
  ARM: dts: stm32: add optee reserved memory on stm32mp135f-dk
  ARM: dts: stm32: add RCC on STM32MP13x SoC family
  ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP13
  dt-bindings: rcc: stm32: select the "secure" path for stm32mp13
  ARM: dts: stm32: correct vcc-supply for eeprom on stm32mp15xx-osd32
  ARM: dts: stm32: fix missing internally connected voltage regulator for OSD32MP1
  ARM: dts: stm32: adjust whitespace around '=' on MCU boards
  ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSI
  ARM: dts: stm32: remove the IPCC "wakeup" IRQ on stm32mp151
  ARM: dts: lan966x: Cleanup flexcom3 usart pinctrl settings.
  arm64: dts: renesas: spider-cpu: Fix scif0/scif3 sort order
  ARM: shmobile: rcar-gen2: Increase refcount for new reference
  arm64: dts: qcom: msm8996: Add interconnect support
  arm64: dts: Add SFP node for TA 3.0 devices
  arm64: dts: layerscape: Add SFP node for TA 2.1 devices
  ARM: dts: layerscape: Add SFP node for TA 2.1 devices
  soc: fsl: guts: check return value after calling of_iomap() in fsl_guts_get_soc_uid()
  soc: fsl: guts: fix return value check in fsl_guts_init()
  ARM: dts: ux500: Drop unused i2c power domain supply
  arm64: defconfig: Enable Allwinner built in CODECs
  arm64: dts: allwinner: a64: orangepi-win: Fix LED node name
  m68k: q40: Align '*' in comments
  spi: dt-bindings: zynqmp-qspi: add missing 'required'
  spi: dt-bindings: cadence: add missing 'required'
  mm: slab: optimize memcg_slab_free_hook()
  mm/tracing: add 'accounted' entry into output of allocation tracepoints
  tools/vm/slabinfo: Handle files in debugfs
  mm/slub: Simplify __kmem_cache_alias()
  arm64: dts: rockchip: enable hdmi tx audio on rock-3a
  arm64: dts: rockchip: enable hdmi tx audio on rk3568-evb1-v10
  mm, slab: fix bad alignments
  firmware: arm_scmi: Use fast channel tracing
  include: trace: Add SCMI fast channel tracing
  firmware: arm_scmi: Add SCMI v3.1 powercap fast channels support
  firmware: arm_scmi: Generalize the fast channel support
  firmware: arm_scmi: Add SCMI v3.1 powercap protocol basic support
  dt-bindings: firmware: arm,scmi: Add support for powercap protocol
  firmware: arm_scmi: Add SCMI System Power Control driver
  firmware: arm_scmi: Add devm_protocol_acquire helper
  firmware: arm_scmi: Add SCMI v3.1 System Power extensions
  firmware: arm_scmi: Support only one single system power device
  firmware: arm_scmi: Use new SCMI full message tracing
  include: trace: Add SCMI full message tracing
  firmware: arm_scpi: Ensure scpi_info is not assigned if the probe fails
  arm64: fix oops in concurrently setting insn_emulation sysctls
  soc: bcm: bcm2835-power: Bypass power_on/off() calls
  soc: bcm: bcm2835-power: Add support for BCM2711's RPiVid ASB
  soc: bcm: bcm2835-power: Resolve ASB register macros
  soc: bcm: bcm2835-power: Refactor ASB control
  mfd: bcm2835-pm: Add support for BCM2711
  mfd: bcm2835-pm: Use 'reg-names' to get resources
  perf/x86/intel: Fix PEBS data source encoding for ADL
  perf/x86/intel: Fix PEBS memory access info encoding for ADL
  sched/core: Use try_cmpxchg in set_nr_{and_not,if}_polling
  sched/core: add forced idle accounting for cgroups
  ARM: dts: lan966x: Add mcan1 node.
  ARM: dts: at91: sama7g5: add reset-controller node
  ARM: dts: at91: use generic name for reset controller
  ARM: dts: at91: sama5d2: fix compilation warning
  ARM: dts: at91: sama5d2: fix compilation warning
  selftests:timers: globals don't need initialization to 0
  ARM: dts: qcom: Fix sdhci node names - use 'mmc@'
  arm64: dts: qcom: sc7180-trogdor: Split out keyboard node and describe detachables
  arm64: dts: qcom: ipq8074: fix NAND node name
  arm64: dts: qcom: msm8916: add xo clocks to rpmcc and a53pll
  arm64: dts: qcom: msm8996: add second DSI interface
  arm64: dts: qcom: add mdp_clk clock to the MDSS device
  arm64: dts: qcom: sm8250: Enable per-process page tables.
  arm64: dts: qcom: msm8916-samsung-a2015: Add touchscreen pinctrl
  arm64: dts: qcom: msm8996: drop phy-names from HDMI device node
  arm64: dts: qcom: msm8994: add required ranges to OCMEM
  arm64: dts: qcom: sdm845: add dedicated IMEM and syscon compatibles
  arm64: dts: qcom: sdm630: add dedicated IMEM and syscon compatibles
  arm64: dts: qcom: sc7280: add simple-mfd to IMEM
  arm64: dts: qcom: sc7180: add dedicated IMEM and syscon compatibles
  arm64: dts: qcom: qcs404: add dedicated IMEM and syscon compatibles
  arm64: dts: qcom: use generic sram as name for imem and ocmem nodes
  arm64: dts: qcom: sdm845-db845c: add function and color to LED nodes
  arm64: dts: qcom: sc7280-herobrine: add function to LED node
  arm64: dts: qcom: sc7180-trogdor: add function to LED node
  arm64: dts: qcom: qrb5165-rb5: add function and color to LED nodes
  arm64: dts: qcom: apq8016-sbc: add function and color to LED nodes
  arm64: dts: qcom: sm8250: Move qup-opp-table out of soc node
  arm64: dts: qcom: sm8350: Move qup-opp-tables out of soc node
  arm64: dts: qcom: sm8450: rename interconnect nodes
  arm64: dts: qcom: msm8996-xiaomi-natrium: Add support for Xiaomi Mi 5s Plus
  dt-bindings: arm: qcom: Document xiaomi,natrium board
  arm64: dts: qcom: ipq6018: correct QUP peripheral labels
  arm64: dts: qcom: sm8250: use constants for audio clocks
  arm64: dts: qcom: sdm845*: replace i2s reg with constant
  arm64: dts: qcom: sm8450: Fix the IRQ trigger type for remoteproc nodes
  arm64: dts: qcom: msm8916: Fix typo in pronto remoteproc node
  arm64: dts: qcom: msm8998-xperia: Introduce ToF sensor support
  arm64: dts: qcom: sc7280: Add proxy interconnect requirements for modem
  arm64: dts: qcom: sm8450: remove duplicated glink-edge interrupt
  arm64: dts: qcom: sm8350: remove duplicated glink-edge interrupt
  arm64: dts: qcom: sdm630: remove unneeded address/size cells in glink-edge
  arm64: dts: qcom: ipq6018: add label to remoteproc node
  arm64: dts: qcom: Remove unused 'vdda-max-microamp' & 'vdda-pll-max-microamp' properties
  arm64: dts: qcom: ipq8074: add USB power domains
  arm64: dts: qcom: Fix 'reg-names' for sdhci nodes
  arm64: dts: qcom: Fix ordering of 'clocks' & 'clock-names' for sdhci nodes
  arm64: dts: qcom: sdm630: Fix 'interconnect-names' for sdhci nodes
  arm64: dts: qcom: Fix sdhci node names - use 'mmc@'
  arm64: dts: qcom: sdm630-nile: Add RGB status LED on the PM660L LPG
  arm64: dts: qcom: pm660l: Add LPG node
  arm64: dts: qcom: qcs404: fix default pinctrl settings for blsp1_spi1
  arm64: dts: qcom: qrb5165-rb5: declare tri-led user leds
  arm64: dts: qcom: pm8150l: add Light Pulse Generator device node
  arm64: dts: qcom: pm8150b: add Light Pulse Generator device node
  arm64: dts: qcom: align led node names with dtschema
  arm64: dts: qcom: sdm630-sony-xperia-nile: drop unneeded status from gpio-keys
  arm64: dts: qcom: correct gpio-keys properties
  arm64: dts: qcom: align gpio-key node names with dtschema
  arm64: dts: qcom: adjust whitespace around '='
  arm64: dts: qcom: msm8998-mtp: correct board compatible
  arm64: dts: qcom: ipq6018-cp01-c1: fix Micron SPI NOR compatible
  arm64: dts: qcom: sdm630: correct QFPROM byte offsets
  arm64: dts: qcom: use dedicated QFPROM compatibles
  arm64: dts: qcom: correct SPMI WLED register range encoding
  arm64: dts: qcom: add missing AOSS QMP compatible fallback
  arm64: dts: qcom: sc7180: Add kingoftown dts files
  arm64: dts: qcom: sc7180: Add pazquel dts files
  arm64: dts: qcom: sc7180: Add mrbland dts files
  arm64: dts: qcom: sc7180: Add quackingstick dts files
  arm64: dts: qcom: sc7180: Add wormdingler dts files
  arm64: dts: qcom: sc7280: Rename sar sensor labels
  arm64: dts: qcom: sc8280xp: add Lenovo Thinkpad X13s devicetree
  arm64: dts: qcom: add SA8540P and ADP
  arm64: dts: qcom: sc8280xp: Add reference device
  stack: Declare {randomize_,}kstack_offset to fix Sparse warnings
  lib: overflow: Do not define 64-bit tests on 32-bit
  MAINTAINERS: Add a general "kernel hardening" section
  usercopy: use unsigned long instead of uintptr_t
  kunit: Taint the kernel when KUnit tests are run
  panic: Taint kernel if tests are run
  exec: Fix a spelling mistake
  ACPI: bus: Drop unused list heads from struct acpi_device
  hisi_lpc: Use acpi_dev_for_each_child()
  bus: hisi_lpc: fix missing platform_device_put() in hisi_lpc_acpi_probe()
  irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling
  dt-bindings: interrupt-controller: Require trigger type for T-HEAD PLIC
  irqchip/sifive-plic: Add support for Renesas RZ/Five SoC
  dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC
  arm64: Add an override for ID_AA64SMFR0_EL1.FA64
  arm64: Add the arm64.nosve command line option
  arm64: Add the arm64.nosme command line option
  arm64: Expose a __check_override primitive for oddball features
  arm64: Allow the idreg override to deal with variable field width
  arm64: Factor out checking of a feature against the override into a macro
  arm64: Allow sticky E2H when entering EL1
  arm64: Save state of HCR_EL2.E2H before switch to EL1
  arm64: Rename the VHE switch to "finalise_el2"
  arm64: mm: fix booting with 52-bit address space
  x86/kexec: Carry forward IMA measurement log on kexec
  ARM: davinci: Delete DM646x board files
  ARM: davinci: Delete DM644x board files
  arm64: Do not forget syscall when starting a new thread.
  arm64: vdso32: Add DWARF_DEBUG
  arm64: vdso32: Shuffle .ARM.exidx section above ELF_DETAILS
  arm64: compat: Move sigreturn32.S to .rodata section
  spi: dt-bindings: dw-apb-ssi: update spi-{r,t}x-bus-width
  arm64: defconfig: Enable qcom interconnect drivers
  arm64: defconfig: Enable qcom ss & hs usb phy
  ARM: dts: qcom: apq8064: drop phy-names from HDMI device node
  ARM: dts: qcom: apq8064-ifc6410: drop hdmi-mux-supply
  ARM: dts: qcom: pm8841: add required thermal-sensor-cells
  ARM: dts: qcom: msm8974: add required ranges to OCMEM
  ARM: dts: qcom: sdx55: add dedicated IMEM and syscon compatibles
  ARM: dts: qcom: msm8974: add dedicated IMEM compatible
  ARM: dts: qcom: apq8064-asus-nexus7: add dedicated IMEM compatible
  ARM: dts: qcom: use generic sram as name for imem and ocmem nodes
  ARM: dts: qcom: ipq8064: add function to LED nodes
  ARM: dts: qcom: ipq8064-rb3011: add color to LED node
  ARM: dts: qcom: ipq4018-ap120c-ac: add function and color to LED nodes
  ARM: dts: qcom: apq8060-ifc6410: add color to LED node
  ARM: dts: qcom: apq8060-dragonboard: add function and color to LED nodes
  soc: qcom: aoss: Fix refcount leak in qmp_cooling_devices_register
  soc: qcom: llcc: Fix syntax errors in comments
  soc: qcom: ocmem: Fix refcount leak in of_get_ocmem
  ARM: dts: qcom: sdx55: Fix the IRQ trigger type for UART
  ARM: dts: qcom-msm8974: fix irq type on blsp2_uart1
  ARM: dts: qcom: msm8974: Add BAM DMUX Ethernet/IP device
  dt-bindings: clock: qcom: ipq8074: add USB GDSCs
  dt-bindings: soc: qcom,wcnss: remove unneeded ref for names
  docs/doc-guide: Mention make variable SPHINXDIRS
  scripts: get_feat.pl: use /usr/bin/env to find perl
  docs/zh_CN: Add mutex-design Chinese translation
  docs/zh_CN: Show the Chinese translation of spinlocks
  dax: set did_zero to true when zeroing successfully
  iomap: set did_zero to true when zeroing successfully
  iomap: skip pages past eof in iomap_do_writepage()
  ACPI: Move PRM config option under the main ACPI config
  ACPI: Enable Platform Runtime Mechanism(PRM) support on ARM64
  ACPI: PRM: Change handler_addr type to void pointer
  arm64: dts: qcom: add SC8280XP platform
  dt-bindings: mailbox: qcom-ipcc: Add NSP1 client
  dt-bindings: arm: qcom: Document additional sc8280xp devices
  arm64: dts: qcom: sm8450: Add interconnect requirements for SCM
  arm64: dts: qcom: sdm660: Add initial Inforce IFC6560 board support
  spi: spi.c: Remove redundant else block
  spi: spi.c: Fix comment style
  spi: spi.c: White-space fix in __spi_pump_messages()
  regmap: cache: Add extra parameter check in regcache_init
  regulator: scmi: Add missing of_node_get()
  ACPI: bus: Drop driver member of struct acpi_device
  ACPI: bus: Drop redundant check in acpi_device_remove()
  spi: pxa2xx: Add support for Intel Meteor Lake-P
  crypto: arm64/gcm - Select AEAD for GHASH_ARM64_CE
  crypto: testmgr - fix version number of RSA tests
  crypto: vmx - drop unexpected word 'for' in comments
  crypto: caam - drop unexpected word 'for' in comments
  crypto: caam - drop unexpected word 'a' in comments
  crypto: cavium - fix typos in comments
  crypto: arm64/aes-neon - Fix typo in comment
  crypto: ux500/hash - drop unexpected word "the"
  crypto: nx - drop unexpected word "the"
  crypto: lib/blake2s - reduce stack frame usage in self test
  arm64: defconfig: enable Qualcomm LPG leds driver
  ARM: dts: qcom: align gpio-key node names with dtschema
  ARM: dts: qcom: adjust whitespace around '='
  ARM: dts: qcom: ipq4019: fix Micron SPI NOR compatible
  ARM: dts: qcom: apq8064: add unit addresses to QFPROM regions
  ARM: dts: qcom: cleanup QFPROM nodes
  ARM: dts: qcom: use dedicated QFPROM compatibles
  ARM: dts: qcom: replace gcc PXO with pxo_board fixed clock
  firmware: qcom_scm: Add bw voting support to the SCM interface
  dt-bindings: firmware: qcom-scm: Add interconnects property
  context_tracking: Split user tracking Kconfig
  context_tracking: Rename context_tracking_cpu_set() to ct_cpu_track_user()
  context_tracking: Rename context_tracking_enter/exit() to ct_user_enter/exit()
  context_tracking: Rename context_tracking_user_enter/exit() to user_enter/exit_callable()
  ACPI: APEI: Fix _EINJ vs EFI_MEMORY_SP
  ACPI: LPSS: Fix missing check in register_device_clock()
  dm: improve BLK_STS_DM_REQUEUE and BLK_STS_AGAIN handling
  cpufreq: ACPI: Add Zhaoxin/Centaur turbo boost control interface support
  ACPI: APEI: Better fix to avoid spamming the console with old error logs
  ACPI: PM: save NVS memory for Lenovo G40-45
  Documentation: ACPI: Update links and references to DSD related docs
  ACPI: EC: Drop unused ident initializers from dmi_system_id tables
  ACPI: EC: Re-use boot_ec when possible even when EC_FLAGS_TRUST_DSDT_GPE is set
  ACPI: EC: Drop the EC_FLAGS_IGNORE_DSDT_GPE quirk
  ACPI: EC: Remove duplicate ThinkPad X1 Carbon 6th entry from DMI quirks
  regmap-irq: Deprecate the not_fixed_stride flag
  regmap-irq: Add get_irq_reg() callback
  regmap-irq: Fix inverted handling of unmask registers
  regmap-irq: Deprecate type registers and virtual registers
  regmap-irq: Introduce config registers for irq types
  regmap-irq: Refactor checks for status bulk read support
  regmap-irq: Remove mask_writeonly and regmap_irq_update_bits()
  regmap-irq: Remove inappropriate uses of regmap_irq_update_bits()
  regmap-irq: Remove an unnecessary restriction on type_in_mask
  regmap-irq: Cleanup sizeof(...) use in memory allocation
  regmap-irq: Remove unused type_reg_stride field
  regmap-irq: Convert bool bitfields to unsigned int
  blk-cgroup: factor out blkcg_free_all_cpd()
  blk-cgroup: factor out blkcg_iostat_update()
  ACPI: processor: Drop leftover acpi_processor_get_limit_info() declaration
  ACPI: processor: Split out thermal initialization from ACPI PSS
  dm: refactor dm_md_mempool allocation
  dm: unexport dm_get_reserved_rq_based_ios
  ACPI: video: Drop X86 dependency from Kconfig
  regulator: qcom_smd: Add PM8909 RPM regulators
  regulator: dt-bindings: qcom,smd-rpm: Add PM8909
  regulator: qcom_smd: Fix pm8916_pldo range
  regulator: mt6370: Use the correct header for platform_device_id
  regulator: mt6370: Use 'fwnode_gpiod_get_index' to fix gpio parsing
  block: simplify disk_set_independent_access_ranges
  block: move ->ia_ranges from the request_queue to the gendisk
  block: remove "select BLK_RQ_IO_DATA_LEN" from BLK_CGROUP_IOCOST dependency
  ARM: dts: r9a06g032-rzn1d400-db: Add switch description
  dt-bindings: net: pcs: add bindings for Renesas RZ/N1 MII converter
  ARM: dts: r9a06g032: Describe switch
  ARM: dts: r9a06g032: Describe GMAC2
  ARM: dts: r9a06g032: Describe MII converter
  arm64: dts: renesas: r9a07g054l2-smarc: Correct SoC name in comment
  ARM: dts: renesas: Fix DA9063 watchdog subnode names
  arm64: dts: renesas: r8a779m8: Drop operating points above 1.5 GHz
  MAINTAINERS: Add Renesas SoC DT bindings to Renesas Architecture sections
  nfs: Leave pages in the pagecache if readpage failed
  buffer: Remove check for PageError
  orangefs: Remove test for folio error
  iomap: Remove test for folio error
  jfs: Remove check for PageUptodate
  remap_range: Remove check of uptodate flag
  ufs: Remove checks for PageError
  reiserfs: Remove check for PageError
  ntfs3: Remove check for PageError
  ntfs: Remove check for PageError
  nilfs2: Remove check for PageError
  ext2: Remove check for PageError
  ntfs: Remove check for PageError
  hfsplus: Remove check for PageError
  hfs: Remove check for PageError
  freevxfs: Remove check of PageError
  afs: Remove check of PageError
  block: Remove check of PageError
  docs: Improve ->read_folio documentation
  filemap: Use filemap_read_folio() in do_read_cache_folio()
  filemap: Handle AOP_TRUNCATED_PAGE in do_read_cache_folio()
  filemap: Move 'filler' case to the end of do_read_cache_folio()
  netfs: Remove extern from function prototypes
  filemap: Remove find_get_pages_range() and associated functions
  shmem: Convert shmem_unlock_mapping() to use filemap_get_folios()
  vmscan: Add check_move_unevictable_folios()
  nilfs2: Convert nilfs_copy_back_pages() to use filemap_get_folios()
  hugetlbfs: Convert remove_inode_hugepages() to use filemap_get_folios()
  f2fs: Convert f2fs_invalidate_compress_pages() to use filemap_get_folios()
  ext4: Convert mpage_map_and_submit_buffers() to use filemap_get_folios()
  ext4: Convert mpage_release_unused_pages() to use filemap_get_folios()
  buffer: Convert clean_bdev_aliases() to use filemap_get_folios()
  filemap: Add filemap_get_folios()
  filemap: Remove add_to_page_cache() and add_to_page_cache_locked()
  hugetlb: Convert huge_add_to_page_cache() to use a folio
  mpage: Convert do_mpage_readpage() to use a folio
  mm: Remove __delete_from_page_cache()
  mm: Account dirty folios properly during splits
  firmware: xilinx: Add TF_A_PM_REGISTER_SGI SMC call
  cpufreq: zynq: Fix refcount leak in zynq_get_revision
  spi: intel: Add support for Intel Meteor Lake-P SPI serial flash
  spi: s3c64xx: define exynosautov9 compatible
  spi: s3c64xx: add spi port configuration for Exynos Auto v9 SoC
  spi: s3c64xx: support custom value of internal clock divider
  spi: s3c64xx: support loopback mode
  arm64: dts: juno: Add cache-level property to L2 caches
  arm64/fpsimd: Remove duplicate SYS_SVCR read
  arm64: head: remove __PHYS_OFFSET
  arm64: lds: use PROVIDE instead of conditional definitions
  ata: libata-scsi: fix result type of ata_ioc32()
  PCI: vmd: Add DID 8086:7D0B and 8086:AD0B for Intel MTL SKUs
  fix short copy handling in copy_mc_pipe_to_iter()
  copy_page_{to,from}_iter(): switch iovec variants to generic
  dt-bindings: arm: qcom: document sda660 SoC and ifc6560 board
  arm64: dts: qcom: sdm660: move SDHC2 card detect pinconf to board files
  arm64: dts: qcom: sdm636-sony-xperia-ganges-mermaid: correct sdc2 pinconf
  arm64: dts: qcom: sdm630: fix gpu's interconnect path
  arm64: dts: qcom: sdm630: add second (HS) USB host support
  arm64: dts: qcom: sdm630: rename qusb2phy to qusb2phy0
  arm64: dts: qcom: sdm630: fix the qusb2phy ref clock
  arm64: dts: qcom: sdm630: disable GPU by default
  arm64: dts: qcom: sdm660: disable dsi1/dsi1_phy by default
  arm64: dts: qcom: sdm630: disable dsi0/dsi0_phy by default
  arm64: dts: qcom: correct interrupt controller on PM8916 and PMS405
  arm64: dts: qcom: add missing gpio-ranges in PMIC GPIOs
  soc: qcom: cmd-db: replace strscpy_pad() with strncpy()
  selftests/drivers/gpu: Add error messages to drm_mm.sh
  selftests/tpm2: increase timeout for kselftests
  treewide: uapi: Replace zero-length arrays with flexible-array members
  efi: Simplify arch_efi_call_virt() macro
  drivers: fix typo in firmware/efi/memmap.c
  blk-mq: cleanup disk sysfs registration
  blk-mq: rename blk_mq_sysfs_{,un}register
  block: remove the extra gendisk reference in __blk_mq_register_dev
  block: use default groups to register the queue attributes
  block: remove a superflous queue kobject reference
  block: simplify blktrace sysfs attribute creation
  arm64: vdso*: place got/plt sections in .rodata
  arm64: vdso32: add ARM.exidx* sections
  arm64: correct the effect of mitigations off on kpti
  block: remove blk_cleanup_disk
  block: simplify disk shutdown
  block: stop setting the nomerges flags in blk_cleanup_queue
  block: remove QUEUE_FLAG_DEAD
  mtip32xx: fix device removal
  mtip32xx: remove the device_status debugfs file
  regulator: fix a kernel-doc warning
  arm64: extable: cleanup redundant extable type EX_TYPE_FIXUP
  arm64: extable: move _cond_extable to _cond_uaccess_extable
  arm64: extable: make uaaccess helper use extable type EX_TYPE_UACCESS_ERR_ZERO
  arm64: asm-extable: add asm uacess helpers
  arm64: asm-extable: move data fields
  arm64: extable: add new extable type EX_TYPE_KACCESS_ERR_ZERO support
  x86/mce: Check whether writes to MCA_STATUS are getting ignored
  sched/fair: Remove the energy margin in feec()
  sched/fair: Remove task_util from effective utilization in feec()
  sched/fair: Use the same cpumask per-PD throughout find_energy_efficient_cpu()
  sched/fair: Rename select_idle_mask to select_rq_mask
  sched, drivers: Remove max param from effective_cpu_util()/sched_cpu_util()
  sched/fair: Decay task PELT values during wakeup migration
  sched/fair: Provide u64 read for 32-bits arch helper
  perf/core: Add a new read format to get a number of lost samples
  sched/fair: Introduce SIS_UTIL to search idle CPU based on sum of util_avg
  sched: only perform capability check on privileged operation
  sched: Remove unused function group_first_cpu()
  sched/fair: Remove redundant word " *"
  selftests/rseq: check if libc rseq support is registered
  selftests/rseq: riscv: fix 'literal-suffix' warning
  selftests/rseq: riscv: use rseq_get_abi() helper
  ARM: OMAP2+: Kconfig: Fix indentation
  ARM: OMAP2+: Fix refcount leak in omap3xxx_prm_late_init
  ARM: OMAP2+: pdata-quirks: Fix refcount leak bug
  ARM: OMAP2+: display: Fix refcount leak bug
  ARM: OMAP2+: Fix refcount leak in omapdss_init_of
  spi: s3c64xx: move dma_release_channel to unprepare
  spi: synquacer: Add missing clk_disable_unprepare()
  docs/doc-guide: Put meta title for kernel-doc HTML page
  docs/doc-guide: Add footnote on Inkscape for better images in PDF documents
  docs/kselftest: add more guidelines for adding new tests
  docs/zh_CN: Update zh_CN/kernel-hacking/hacking.rst to 5.19-rc1
  docs/zh_CN: add vm vmalloced-kernel-stacks translation
  docs/zh_CN: add vm page_migration translation
  docs/zh_CN: riscv: Update the translation of vm-layout.rst to 5.19-rc1
  docs/zh_CN: riscv: Remove the translation of pmu.rst
  docs: dev-tools: modify SPL reference URL to actual SPL doc entry
  docs: filesystems: f2fs: fix description about compress ioctl
  docs/zh_CN: Update the translation of vm index to 5.19-rc1
  docs/zh_CN: Update the translation of page_owner to 5.19-rc1
  docs/zh_CN: Update the translation of highmem to 5.19-rc1
  arm64: dts: qcom: sdm630: order interrupts according to bindings
  arm64: dts: qcom: sdm630: order regs according to bindings
  arm64: dts: qcom: sdm630: order clocks according to bindings
  ARM: dts: qcom: add missing gpio-ranges in PMIC GPIOs
  ARM: dts: qcom: pmx65: add fallback compatible to PMIC GPIO
  ARM: dts: qcom: mdm9615: add missing PMIC GPIO reg
  ARM: dts: qcom: align PMIC GPIO pin configuration with DT schema
  arm64: dts: qcom: msm8994-msft-lumia-octagon: add PM8994 pin properties
  arm64: dts: qcom: apq8096-db820c: add PM8994 pin function
  arm64: dts: qcom: add fallback compatible to PMIC GPIOs
  arm64: dts: qcom: align PMIC GPIO pin configuration with DT schema
  arm64: dts: qcom: sdm845-akatsuki: Round down l22a regulator voltage
  ARM: dts: qcom: sdx65: Add Watchdog support
  dt-bindings: firmware: scm: Add compatible for SDX65
  ARM: dts: qcom: sdx65: Add pshold support
  ARM: dts: qcom: sdx65-mtp: Enable modem
  ARM: dts: qcom: sdx65: Add Modem remoteproc node
  ARM: dts: qcom: sdx65: Add SCM node
  ARM: dts: qcom: sdx65: Add IMEM and PIL info region
  ARM: dts: qcom: sdx65: Add modem SMP2P node
  ARM: dts: qcom: sdx65: Add CPUFreq support
  ARM: dts: qcom: sdx65-mtp: Enable QPIC NAND support
  ARM: dts: qcom: sdx65-mtp: Enable QPIC BAM support
  ARM: dts: qcom: sdx65: Add QPIC NAND support
  ARM: dts: qcom: sdx65: Add QPIC BAM support
  ARM: dts: qcom: sdx65-mtp: Enable USB3 and PHY support
  ARM: dts: qcom: sdx65: Add USB3 and PHY support
  ARM: dts: qcom: sdx65: Add interconnect nodes
  ARM: dts: qcom: sdx65: Add Shared memory manager support
  arm64: dts: qcom: msm8996: Add SDHCI resets
  arm64: dts: qcom: msm8996-tone: Rule out PM(I)8994 variants
  arm64: dts: qcom: msm8996-tone: Drop cont_splash_mem region
  arm64: dts: qcom: msm8998-mtp: Merge and fix up the DT
  arm64: dts: qcom: msm8998-fxtec: Decouple from 8998 MTP
  arm64: dts: qcom: msm8998*: Clean up #includes
  arm64: dts: qcom: msm8998-oneplus: Add clocks & GDSC to simplefb
  arm64: dts: qcom: msm8998*: Keep MMCC & MMSS_SMMU enabled by default
  arm64: dts: qcom: msm8998-fxtec: Use "okay" instead of "ok"
  arm64: dts: qcom: msm8998-oneplus: Apply style fixes
  arm64: dts: qcom: msm8998-yoshino/oneplus: Use pm8005_regulators label
  arm64: dts: qcom: msm8998-yoshino: Remove simple-bus compatible from clocks{}
  arm64: dts: qcom: msm8998-yoshino: Add USB extcon
  arm64: dts: qcom: msm8998-yoshino-lilac: Disable LVS1
  arm64: dts: qcom: msm8998-laptops: Clean up DTs
  arm64: dts: qcom: msm8998-clamshell: Clean up the DT
  arm64: dts: qcom: msm8998*: Fix TLMM and pin nodes
  arm64: dts: qcom: sdm845: Add camss vdda-pll-supply
  arm64: dts: qcom: sdm845: Rename camss vdda-supply to vdda-phy-supply
  arm64: dts: qcom: timer should use only 32-bit size
  kselftests/damon: add support for cases where debugfs cannot be read
  selftests: Make the usage formatting consistent in kselftest_deps.sh
  kselftests: Enable the echo command to print newlines in Makefile
  arm64: dts: qcom: align OPP table names with DT schema
  userfaultfd/selftests: Fix typo in comment
  ARM: dts: bcm2711: Use proper compatible in PM/Watchdog node
  ARM: dts: bcm2835/bcm2711: Introduce reg-names in watchdog node
  dt-bindings: soc: bcm: bcm2835-pm: Add support for bcm2711
  dt-bindings: soc: bcm: bcm2835-pm: Introduce reg-names
  dt-bindings: soc: bcm: bcm2835-pm: Convert bindings to DT schema
  blk-mq: blk_mq_tag_busy is no need to return a value
  block: Always initialize bio IO priority on submit
  block: Initialize bio priority earlier
  blk-ioprio: Convert from rqos policy to direct call
  blk-ioprio: Remove unneeded field
  block: Fix handling of tasks without ioprio in ioprio_get(2)
  block: Make ioprio_best() static
  block: Generalize get_current_ioprio() for any task
  block: Return effective IO priority from get_current_ioprio()
  block: fix default IO priority handling again
  blk-mq: Don't disable preemption around __blk_mq_run_hw_queue().
  block: bfq: Fix kernel-doc headers
  block: bfq: Remove an unused function definition
  bfq: Remove useless code in bfq_lookup_next_entity
  block: move blk_queue_get_max_sectors to blk.h
  block: fold blk_max_size_offset into get_max_io_size
  block: cleanup variable naming in get_max_io_size
  block: open code blk_max_size_offset in blk_rq_get_max_sectors
  dm: open code blk_max_size_offset in max_io_len
  block: factor out a chunk_size_left helper
  block: Make blk_mq_get_sq_hctx() select the proper hardware queue type
  block: Rename a blk_mq_map_queue() argument
  blk-iocost: Simplify ioc_rqos_done()
  block: Directly use ida_alloc()/free()
  iomap: add support for dma aligned direct-io
  block: relax direct io memory alignment
  block: introduce bdev_iter_is_aligned helper
  iov: introduce iov_iter_aligned
  block/bounce: count bytes instead of sectors
  block/merge: count bytes instead of sectors
  block: add a helper function for dio alignment
  block: introduce bdev_dma_alignment helper
  block: export dma_alignment attribute
  block/bio: remove duplicate append pages code
  block: fix infinite loop for invalid zone append
  spi: opportunistically skip ctlr->cur_msg_completion
  spi: Ensure the io_mutex is held until spi_finalize_current_message()
  spi: Set ctlr->cur_msg also in the sync transfer case
  spi: Remove unneeded READ_ONCE for ctlr->busy flag
  spi: Remove the now unused ctlr->idling flag
  spi: Remove check for idling in __spi_pump_messages()
  spi: Remove check for controller idling in spi sync path
  spi: __spi_pump_messages: Consolidate spin_unlocks to goto target
  spi: Lock controller idling transition inside the io_mutex
  spi: Don't use the message queue if possible in spi_sync
  spi: Move ctlr->cur_msg_prepared to struct spi_message
  spi: mpc52xx-psc: Switch to using core message queue
  spi: sh: Switch to using core message queue
  spi: dt-bindings: samsung: Add Exynos4210 SPI
  spi: dw: Add deferred DMA-channels setup support
  spi: s3c64xx: constify fsd_spi_port_config
  regmap: Don't warn about cache only mode for devices with no cache
  arm64: Add HAVE_IOREMAP_PROT support
  arm64: mm: Convert to GENERIC_IOREMAP
  mm: ioremap: Add ioremap/iounmap_allowed()
  mm: ioremap: Setup phys_addr of struct vm_struct
  mfd: core: Use acpi_dev_for_each_child()
  mm: ioremap: Use more sensible name in ioremap_prot()
  ARM: mm: kill unused runtime hook arch_iounmap()
  ARM: dts: am33xx: Map baseboard EEPROM on BeagleBone Black
  perf: hisi: Extract hisi_pmu_init
  arm64: Copy the task argument to unwind_state
  arm64: Split unwind_init()
  arm64/signal: Clean up SVE/SME feature checking inconsistency
  cgroup.c: remove redundant check for mixable cgroup in cgroup_migrate_vet_dst
  ARM: dts: s5pv210: align SDHCI node name with dtschema
  ARM: dts: s3c64xx: align SDHCI node name with dtschema
  ARM: dts: s3c24xx: align SDHCI node name with dtschema
  ARM: dts: exynos: align SDHCI node name with dtschema
  ARM: dts: at91: drop unneeded status from gpio-keys
  ARM: dts: at91: correct gpio-keys properties
  ARM: dts: at91: align gpio-key node names with dtschema
  ARM: dts: omap: correct gpio-keys properties
  ARM: dts: omap: align gpio-key node names with dtschema
  arm64: dts: marvell: armada-3720: align lednode names with dtschema
  arm64: dts: marvell: align gpio-key node names with dtschema
  ARM: dts: marvell: correct gpio-keys properties
  ARM: dts: marvell: align gpio-key node names with dtschema
  ARM: dts: omap: adjust whitespace around '='
  ARM: dts: ti: adjust whitespace around '='
  ARM: dts: stih407-family: Harmonize DWC USB3 DT nodes name
  soc: imx: imx8m-blk-ctrl: Make error prints useful
  arm64: dts: apm: Harmonize DWC USB3 DT nodes name
  arm64: dts: freescale: Add phyBOARD-Polis-i.MX8MM support
  arm64: dts: imx8m{m,p}-verdin: use IT temperatures
  ARM: dts: imx6qdl-prti6q.dtsi: Add applicable properties to usdhc3
  ARM: dts: imx6q-bosch-acc: Replace 'enable-sdio-wakeup'
  ARM: dts: imx7d-smegw01: Replace 'enable-sdio-wakeup'
  arm64: defconfig: Enable gpio-fan support
  bindings: arm: fsl: Add PHYTEC i.MX8MM devicetree bindings
  arm64: dts: imx8mn-evk: add bt-sco sound card support
  arm64: dts: imx8mq-evk: add bt-sco sound card support
  arm64: dts: imx8mm-evk: add bt-sco sound card support
  soc: fsl: guts: add serial_number support
  soc: fsl: guts: drop platform driver
  soc: fsl: guts: use of_root instead of own reference
  soc: fsl: guts: allocate soc_dev_attr on the heap
  soc: fsl: guts: embed fsl_guts_get_svr() in probe()
  soc: fsl: guts: remove module_exit() and fsl_guts_remove()
  soc: fsl: guts: machine variable might be unset
  dt-bindings: arm: qcom: switch maintainer to Bjorn
  soc: qcom: rpmhpd: fix typos in comment
  arm64: dts: qcom: sm8250: Disable camcc by default
  soc: qcom: correct kerneldoc
  soc: qcom: cmd-db: replace strncpy() with strscpy_pad()
  firmware: qcom_scm-legacy: correct kerneldoc
  dt-bindings: firmware: document Qualcomm QCS404 and SM6125 SCM
  soc: qcom: apr: Drop redundant check in .remove()
  arm64: dts: qcom: msm8996: add clocks to the MMCC device node
  arm64: dts: qcom: sm8450: add uart20 node
  arm64: dts: qcom: sc7280-qcard: Add ldo_l17b regulator node
  arm64: dts: qcom: sc7280: Set SPI flash to 50 MHz for herobrine boards
  arm64: dts: qcom: sc7280: Set modem FW path for Chrome OS boards
  arm64: qcom: sc7280-herobrine: Enable DP
  arm64: dts: qcom: sc7180: Remove ipa_fw_mem node on trogdor
  arm64: dts: qcom: sc7280: Enable wifi for Chrome OS boards
  dt-bindings: arm: qcom: Add more sc7180 Chromebook board bindings
  dt-bindings: arm: qcom: Add / fix sc7280 board bindings
  dt-bindings: arm: qcom: Add sc7180 Chromebook board bindings
  dt-bindings: arm: qcom: Mention that Chromebooks use a different scheme
  dt-bindings: Document how Chromebooks with depthcharge boot
  arm64: dts: qcom: sc7280: Enable keyboard backlight for villager
  arm64: dts: qcom: sc7280: herobrine: Don't disable the keyboard backlight node
  arm64: dts: qcom: sc7280: Add touchscreen to villager
  clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe clocks
  clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe clocks
  clk: qcom: regmap: add PHY clock source implementation
  firmware: qcom_scm: drop unexpected word "the"
  soc: qcom: socinfo: Add an ID for sc7180P
  arm64: dts: qcom: sc7280-herobrine: Add lpi pinmux properties for CRD 3.0/3.1
  arm64: dts: qcom: sc7280: add lpass lpi pin controller node
  arm64: dts: qcom: sc7280: Add secondary MI2S pinmux specifications for CRD 3.0/3.1
  arm64: dts: qcom: sc7280: Add pinmux for I2S speaker and Headset
  arm64: dts: qcom: sdm660-xiaomi-lavender: Configure WLED
  docs: UML: fix typo
  docs/zh_CN: core-api: Update the translation of xarray.rst to 5.19-rc3
  docs/zh_CN: core-api: Update the translation of workqueue.rst to 5.19-rc3
  docs/zh_CN: core-api: Update the translation of printk-format.rst to 5.19-rc3
  docs/zh_CN: core-api: Update the translation of printk-basics.rst to 5.19-rc3
  docs/zh_CN: core-api: Update the translation of mm-api.rst to 5.19-rc3
  docs/zh_CN: core-api: Update the translation of kernel-api.rst to 5.19-rc3
  docs/zh_CN: core-api: Update the translation of irq/irq-domain.rst to 5.19-rc3
  docs/zh_CN: core-api: Update the translation of cpu_hotplug.rst to 5.19-rc3
  docs/zh_CN: core-api: Update the translation of cachetlb.rst to 5.19-rc3
  docs: driver-api: gpio: Fix some typos
  docs: Remove duplicate word
  arm64: dts: altera: socfpga_stratix10: move clocks out of soc node
  docs: admin-guide/sysctl: Fix rendering error
  efi: vars: Move efivar caching layer into efivarfs
  efi: vars: Drop __efivar_entry_iter() helper which is no longer used
  efi: vars: Switch to new wrapper layer
  efi: vars: Use locking version to iterate over efivars linked lists
  efi: vars: Remove deprecated 'efivars' sysfs interface
  efi: pstore: Omit efivars caching EFI varstore access layer
  efi: vars: Add thin wrapper around EFI get/set variable interface
  efi: vars: Don't drop lock in the middle of efivar_init()
  pstore: Add priv field to pstore_record for backend specific use
  ARM: dts: lpc18xx: Harmonize EHCI/OHCI DT nodes name
  arm64: dts: qcom: sm8250: remove assigned-clock-rate property for mdp clk
  arm64: dts: qcom: sdm845: remove assigned-clock-rate property for mdp clk
  arm64: dts: qcom: sm7180: remove assigned-clock-rate property for mdp clk
  arm64: dts: qcom: sm7280: remove assigned-clock-rate property for mdp clk
  arm64: setup: drop early FDT pointer helpers
  arm64: head: avoid relocating the kernel twice for KASLR
  arm64: kaslr: defer initialization to initcall where permitted
  arm64: head: record CPU boot mode after enabling the MMU
  arm64: head: populate kernel page tables with MMU and caches on
  arm64: head: factor out TTBR1 assignment into a macro
  arm64: idreg-override: use early FDT mapping in ID map
  arm64: head: create a temporary FDT mapping in the initial ID map
  arm64: head: use relative references to the RELA and RELR tables
  arm64: head: cover entire kernel image in initial ID map
  arm64: head: add helper function to remap regions in early page tables
  arm64: mm: provide idmap pointer to cpu_replace_ttbr1()
  arm64: head: pass ID map root table address to __enable_mmu()
  arm64: kernel: drop unnecessary PoC cache clean+invalidate
  arm64: head: split off idmap creation code
  arm64: head: switch to map_memory macro for the extended ID map
  arm64: head: simplify page table mapping macros (slightly)
  arm64: head: drop idmap_ptrs_per_pgd
  arm64: head: move assignment of idmap_t0sz to C code
  arm64: mm: make vabits_actual a build time constant if possible
  arm64: head: move kimage_vaddr variable into C file
  ARM: tegra: Align gpio-keys node names with dtschema
  firmware: tegra: bpmp: Do only aligned access to IPC memory area
  perf/marvell_cn10k: Fix TAD PMU register offset
  perf/marvell_cn10k: Remove useless license text when SPDX-License-Identifier is already used
  arm64: entry: simplify trampoline data page
  crypto: qat - Removes the x86 dependency on the QAT drivers
  crypto: qat - replace get_current_node() with numa_node_id()
  crypto: rsa - implement Chinese Remainder Theorem for faster private key operations
  crypto: ccp - During shutdown, check SEV data pointer before using
  Input: applespi - avoid efivars API and invoke EFI services directly
  selftests/kexec: remove broken EFI_VARS secure boot fallback check
  locking/lockdep: Fix lockdep_init_map_*() confusion
  jump_label: make initial NOP patching the special case
  jump_label: mips: move module NOP patching into arch code
  jump_label: s390: avoid pointless initial NOP patching
  PCI: rcar-gen2: Add RZ/N1 SOC family compatible string
  dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for R9A06G032
  dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema
  dmaengine: dw-edma: Add support for chip-specific flags
  dmaengine: dw-edma: Fix eDMA Rd/Wr-channels and DMA-direction semantics
  dmaengine: dw-edma: Drop dma_slave_config.direction field usage
  dmaengine: dw-edma: Rename wr(rd)_ch_cnt to ll_wr(rd)_cnt in struct dw_edma_chip
  dmaengine: dw-edma: Change rg_region to reg_base in struct dw_edma_chip
  dmaengine: dw-edma: Detach the private data and chip info structures
  ACPI / MMC: PM: Unify fixing up device power
  soundwire: Use acpi_dev_for_each_child()
  arm64: trap implementation defined functionality in userspace
  Documentation/arm64: update memory layout table.
  arm64: kcsan: Support detecting more missing memory barriers
  asm-generic: Add memory barrier dma_mb()
  arm64: boot: add zstd support
  arm64: cpufeature: Allow different PMU versions in ID_DFR0_EL1
  arm64: mm: install KPTI nG mappings with MMU enabled
  arm64: kpti-ng: simplify page table traversal logic
  arm64/sme: Expose SMIDR through sysfs
  pstore/zone: cleanup "rcnt" type
  arm64: compat: Move kuser32.S to .rodata section
  arm64: stacktrace: use non-atomic __set_bit
  arm64: kasan: do not instrument stacktrace.c
  ARM: dts: ux500: Fix Gavini accelerometer mounting matrix
  ARM: dts: ux500: Fix Codina accelerometer mounting matrix
  ARM: dts: ux500: Fix Janice accelerometer mounting matrix
  spi: fsi: Increase timeout and ensure status is checked
  regulator: mt6370: Add mt6370 DisplayBias and VibLDO support
  perf/arm-cci: fix typo in comment
  drivers/perf:Directly use ida_alloc()/free()
  drivers/perf: Directly use ida_alloc()/free()
  arm64: select TRACE_IRQFLAGS_NMI_SUPPORT
  arch: make TRACE_IRQFLAGS_NMI_SUPPORT generic
  arm64: vdso32: enable orphan handling for VDSO
  arm64: vdso32: put ELF related sections in the linker script
  arm64: vdso: enable orphan handling for VDSO
  arm64: vdso: put ELF related sections in the linker script
  arm64: cpuidle: remove generic cpuidle support
  cpuidle: cpuidle-arm: remove arm64 support
  regulator: rt5120: Add PMIC regulator support
  soc: mediatek: fix missing clk_disable_unprepare() on err in svs_resume()
  ARM: dts: xilinx: align gpio-key node names with dtschema
  arm64: dts: xilinx: align gpio-key node names with dtschema
  arm64: dts: zynqmp: add AMS driver to device tree
  dt-bindings: gpio: zynq: Describe gpio-line-names
  arm64: zynqmp: Fix comment about number of gpio line names
  dt-bindings: gpio: zynq: Add power-domains
  dt-bindings: gpio: zynq: Add missing compatible strings
  ARM: dts: rockchip: correct gpio-keys properties on rk3288-tinker
  ARM: dts: rockchip: align gpio-key node names with dtschema
  arm64: dts: rockchip: align gpio-key node names with dtschema
  dt-bindings: arm: Add compatible for MediaTek MT8186
  dt-bindings: arm: mediatek: Add mt8186 pericfg compatible
  arm64: dts: mediatek: mt6795: Specify interrupts for vGIC
  arm64: dts: mediatek: mt6795: Add pinctrl controller node
  arm64: dts: mediatek: mt6795: Add ARM CCI-400 node and assign to CPUs
  arm64: dts: mediatek: mt6795: Add general purpose timer node
  arm64: dts: mediatek: mt6795: Remove incorrect fixed-clocks
  arm64: dts: mediatek: mt6795: Add fixed clocks for 32kHz and 26MHz XOs
  arm64: dts: mediatek: mt6795: Add watchdog node to avoid timeouts
  arm64: dts: mediatek: mt6795: Add Cortex A53 PMU nodes
  arm64: dts: mediatek: mt6795: Add cpu-map and L2 cache
  arm64: dts: mediatek: mt6795: Create soc bus node and move mmio devices
  arm64: dts: mediatek: mt7622-rfb1: remove wrong gpio-keys property
  arm64: dts: mediatek: mt2712e: Add mediatek, infracfg phandle for IOMMU
  arm64: dts: mediatek: mt8173: Add mediatek,infracfg phandle for IOMMU
  arm64: dts: mediatek: mt8183: change efuse node name
  arm64: dts: mediatek: mt8192: fix dtbs check warning of efuse
  arm64: dts: mt8192: Fix idle-states entry-method
  arm64: dts: mt8192: Fix idle-states nodes naming scheme
  soc: mediatek: mutex: Use DDP_COMPONENT_DITHER0 mod index for MT8365
  pwm: mediatek: Add MT8365 support
  arm64: dts: mediatek: Replace 'enable-sdio-wakeup'
  dt-bindings: pwm: Add MT8365 SoC binding
  pwm: Drop unused forward declaration from pwm.h
  pwm: Reorder header file to get rid of struct pwm_capture forward declaration
  pwm: atmel-tcb: Fix typo in comment
  pwm: Drop support for legacy drivers
  ARM: dts: exynos: add function and color to LED nodes in Odroid XU/XU3
  ARM: dts: exynos: add function and color to LED node in Odroid XU4
  ARM: dts: exynos: add function and color to LED node in Odroid HC1
  ARM: dts: exynos: add function and color to LED nodes in Odroid X/X2
  ARM: dts: exynos: add function and color to LED node in Odroid U3
  ARM: dts: exynos: add function and color to LED nodes in Itop Elite
  ARM: dts: exynos: add function to LED nodes in Tiny4412
  ARM: dts: exynos: add function to LED node in Origen 4210
  ARM: dts: exynos: add function and color to aat1290 flash LED node in Galaxy S3
  ARM: dts: exynos: align aat1290 flash LED node with bindings in Galaxy S3
  arm64: dts: mediatek: Add infra #reset-cells property for MT8195
  arm64: dts: mediatek: Add infra #reset-cells property for MT8192
  ARM: dts: ast2600-evb-a1: fix board compatible
  ARM: dts: ast2600-evb: fix board compatible
  ARM: dts: ast2500-evb: fix board compatible
  dt-bindings: arm: aspeed: document board compatibles
  dt-bindings: arm: aspeed: document board compatibles
  x86/vmware: Use BIT() macro for shifting
  context_tracking: Rename __context_tracking_enter/exit() to __ct_user_enter/exit()
  refscale: Convert test_lock spinlock to raw_spinlock
  rcutorture: Handle failure of memory allocation functions
  rcutorture: Fix ksoftirqd boosting timing and iteration
  torture: Create kvm-check-branches.sh output in proper location
  rcuscale: Fix smp_processor_id()-in-preemptible warnings
  rcutorture: Make failure indication note reader-batch overflow
  torture: Adjust to again produce debugging information
  rcutorture: Fix memory leak in rcu_test_debug_objects()
  rcutorture: Simplify rcu_torture_read_exit_child() loop
  rcu/torture: Change order of warning and trace dump
  rcu-tasks: Use delayed_work to delay rcu_tasks_verify_self_tests()
  rcu-tasks: Be more patient for RCU Tasks boot-time testing
  rcu-tasks: Update comments
  rcu-tasks: Disable and enable CPU hotplug in same function
  rcu-tasks: Eliminate RCU Tasks Trace IPIs to online CPUs
  rcu-tasks: Maintain a count of tasks blocking RCU Tasks Trace grace period
  rcu-tasks: Stop RCU Tasks Trace from scanning full tasks list
  doc: Document rcutree.nocb_nobypass_lim_per_jiffy kernel parameter
  doc: Document the rcutree.rcu_divisor kernel boot parameter
  rcutorture: Update rcutorture.fwd_progress help text
  platform/x86/thinkpad_acpi: Use acpi_dev_for_each_child()
  ACPI: scan: Walk ACPI device's children using driver core
  selinux: selinux_add_opt() callers free memory
  ARM: dts: BCM5301X: Add DT for Meraki MR26
  dt-bindings: ARM: add bindings for the Meraki MR26
  ACPI: bus: Introduce acpi_dev_for_each_child_reverse()
  ACPI: video: Use acpi_dev_for_each_child()
  ACPI: bus: Export acpi_dev_for_each_child() to modules
  ACPI: property: Use acpi_dev_for_each_child() for child lookup
  ACPI: container: Use acpi_dev_for_each_child()
  USB: ACPI: Replace usb_acpi_find_port() with acpi_find_child_by_adr()
  thunderbolt: ACPI: Replace tb_acpi_find_port() with acpi_find_child_by_adr()
  ACPI: glue: Introduce acpi_find_child_by_adr()
  ACPI: glue: Introduce acpi_dev_has_children()
  ACPI: glue: Use acpi_dev_for_each_child()
  dt-bindings: clock: Add compatible for D1 DE2 clocks
  context_tracking: Add a note about noinstr VS unsafe context tracking functions
  tools/nolibc: add a help target to list supported targets
  tools/nolibc: make the default target build the headers
  tools/nolibc: fix the makefile to also work as "make -C tools ..."
  tools/nolibc/stdio: Add format attribute to enable printf warnings
  tools/nolibc/stdlib: Support overflow checking for older compiler versions
  context_tracking: Remove unused context_tracking_in_user()
  rcu: Apply noinstr to rcu_idle_enter() and rcu_idle_exit()
  rcu: Dump rcuc kthread status for CPUs not reporting quiescent state
  torture: Make kvm-remote.sh announce which system is being waited on
  rcu-tasks: Stop RCU Tasks Trace from scanning idle tasks
  rcu-tasks: Pull in tasks blocked within RCU Tasks Trace readers
  rcu-tasks: Scan running tasks for RCU Tasks Trace readers
  rcu-tasks: Avoid rcu_tasks_trace_pertask() duplicate list additions
  rcu-tasks: Move rcu_tasks_trace_pertask() before rcu_tasks_trace_pregp_step()
  rcu-tasks: Add blocked-task indicator to RCU Tasks Trace stall warnings
  rcu-tasks: Untrack blocked RCU Tasks Trace at reader end
  rcu-tasks: Track blocked RCU Tasks Trace readers
  rcu-tasks: Add data structures for lightweight grace periods
  rcu-tasks: Make RCU Tasks Trace stall warning handle idle offline tasks
  rcu-tasks: Make RCU Tasks Trace stall warnings print full .b.need_qs field
  rcu-tasks: Flag offline CPUs in RCU Tasks Trace stall warnings
  rcu-tasks: Add slow-IPI indicator to RCU Tasks Trace stall warnings
  rcu-tasks: Simplify trc_inspect_reader() QS logic
  rcu-tasks: Make rcu_note_context_switch() unconditionally call rcu_tasks_qs()
  rcu-tasks: RCU Tasks Trace grace-period kthread has implicit QS
  rcu-tasks: Handle idle tasks for recently offlined CPUs
  rcu-tasks: Idle tasks on offline CPUs are in quiescent states
  rcu-tasks: Make trc_read_check_handler() fetch ->trc_reader_nesting only once
  rcu-tasks: Remove rcu_tasks_trace_postgp() wait for counter
  rcu-tasks: Merge state into .b.need_qs and atomically update
  rcu-tasks: Drive synchronous grace periods from calling task
  rcu-tasks: Move synchronize_rcu_tasks_generic() down
  rcu-tasks: Split rcu_tasks_one_gp() from rcu_tasks_kthread()
  rcu-tasks: Check for abandoned callbacks
  rcutorture: Validate get_completed_synchronize_rcu()
  rcu: Provide a get_completed_synchronize_rcu() function
  rcu: Make normal polling GP be more precise about sequence numbers
  x86/pmem: Fix platform-device leak in error path
  arm64: dts: exynos: Add internal eMMC support to jackpotlte
  m68k: sun3: Use __func__ to get function's name in an output message
  m68k: mac: Fix typos in comments
  m68k: virt: Kconfig minor fixes
  dt-bindings: clock: Add indices for Exynos7885 TREX clocks
  dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS
  spi: topcliff-pch: Use core message validation
  ARM: dts: animeo: correct gpio-keys properties
  ARM: dts: animeo: align gpio-key node names with dtschema
  arm64: dts: hisilicon: correct gpio-keys properties
  arm64: dts: hisilicon: align gpio-key node names with dtschema
  arm64: dts: broadcom: align gpio-key node names with dtschema
  arm64: dts: apm: correct gpio-keys properties
  ata: pata_macio: Fix compilation warning
  brcmfmac: Switch to appropriate helper to load EFI variable contents
  iwlwifi: Switch to proper EFI variable store interface
  media: atomisp_gmin_platform: stop abusing efivar API
  efi: efibc: avoid efivar API for setting variables
  efi: avoid efivars layer when loading SSDTs from variables
  ARM: dts: imx6q-apalis: Cleanup
  ARM: dts: imx6q-apalis: backlight pwm: Adapt brightness steps
  ARM: dts: imx6q-apalis: backlight pwm: Simplify inverted backlight
  ARM: dts: imx6q-apalis: Add support for Toradex Ixora V1.2 carrier boards
  ARM: dts: imx6q-apalis: Clean-up sd card support
  ARM: dts: imx6q-apalis: Add adv7280 video input
  ARM: dts: imx6q-apalis: Add ov5640 mipi csi camera
  ARM: dts: imx6q-apalis: Disable stmpe touchscreen
  ARM: dts: imx6q-apalis: Disable HDMI
  ARM: dts: imx6q-apalis: Add LVDS panel support
  ARM: dts: imx6q-apalis: move gpio-keys to SoM dtsi
  ARM: dts: imx6q-apalis: Move Atmel MXT touch ctrl to SoM dtsi
  ARM: dts: imx6q-apalis: Move pinmux groups to SoM dtsi
  ARM: dts: imx6q-apalis: Move parallel rgb interface to SoM dtsi
  ARM: dts: imx6q-apalis: Command pmic to standby for poweroff
  ARM: dts: imx6q-apalis: Add gpio-line-names
  Revert "ARM: dts: imx6qdl-apalis: Avoid underscore in node name"
  dt-bindings: arm: fsl: Add carrier for toradex,apalis-imx6q
  arm64: freescale/imx8mp-evk.dts: reorder nodes alphabetically
  arm64: dts: imx8mq: Pass a label to the AIPS nodes
  arm64: dts: imx8m: Pass a label to the soc node
  ARM: dts: imx: Pass a label to the AIPS nodes
  ARM: dts: imx: Pass a label to the soc node
  dt-bindings: arm: fsl: Decrease the line length
  dt-bindings: arm: Add DH electronics i.MX8M Plus DHCOM and PDK2
  dt-bindings: arm: fsl: add toradex,colibri-imx7s/d/d-emmc-iris/-v2
  dt-bindings: arm: fsl: add imx93 11x11 evk board
  dt-bindings: arm: fsl: correct 1g vs. 1gb in toradex,colibri-imx6ull-*
  arm64: dts: imx8mm-venice-gw7902: fix UART1 CTS
  ata: libata-eh: fix sloppy result type of ata_internal_cmd_timeout()
  ata: libata-core: fix sloppy parameter type in ata_exec_internal[_sg]()
  ata: make ata_port::fastdrain_cnt *unsigned int*
  ata: libata-eh: fix sloppy result type of ata_eh_nr_in_flight()
  arm64: dts: imx8mp: Add support for DH electronics i.MX8M Plus DHCOM and PDK2
  ARM: dts: imx6ul: fix qspi node compatible
  ARM: dts: imx6ul: fix lcdif node compatible
  ARM: dts: imx6ul: fix csi node compatible
  ARM: dts: imx6ul: fix keypad compatible
  ARM: dts: imx6ul: change operating-points to uint32-matrix
  ARM: dts: imx6ul: add missing properties for sram
  arm64: dts: freescale: align led node names with dtschema
  arm64: dts: freescale: align gpio-key node names with dtschema
  soc: imx: gpcv2: print errno for regulator errors
  arm64: dts: imx8m: Disable job ring 0 nodes
  arm64: dts: freescale: imx8qxp: Fix thermal zone name for cpu0
  ARM: dts: imx6: fix node names for ebook reader keys
  ARM: dts: imx6sl-tolino-shine2hd: fix led node name.
  ARM: imx25: support silicon revision 1.2
  arm64: dts: mba8mx: Remove unneeded comments
  ARM: dts: imx6: skov: add pwm-regulator to control the panel's VCOM
  soc: ti: wkup_m3_ipc: Remove unneeded semicolon
  ARM: dts: keystone: Adjust whitespace around '='
  arm64: dts: ti: Align gpio-key node names with dtschema
  arm64: dts: ti: Adjust whitespace around '='
  soc: bcm: brcmstb: biuctrl: Add missing of_node_put()
  arm64: dts: rockchip: rock-pi-s add more peripherals
  arm64: dts: rockchip: add ROCK Pi S DTS support
  dt-bindings: arm: rockchip: Add Radxa ROCK Pi S
  arm64: dts: mt8183: add GCE client property for Mediatek MUTEX
  soc: mediatek: mutex: add functions that operate registers by CMDQ
  dt-bindings: soc: mediatek: add gce-client-reg for MUTEX
  dt-bindings: soc: mediatek: move out common module from display folder
  soc: mediatek: mutex: add 8183 MUTEX MOD settings for MDP
  soc: mediatek: mutex: add common interface for modules setting
  soc: mediatek: pm-domains: Add support always on flag
  ARM: dts: mediatek: align gpio-key node names with dtschema
  arm64: dts: mediatek: mt7622-bananapi-bpi-r64: align led node names with dtschema
  arm64: dts: mediatek: align gpio-key node names with dtschema
  soc: mediatek: mt8365-mmsys: add DPI/HDMI display path
  soc: mediatek: mutex: add MT8365 support
  crypto: hisilicon/sec - only HW V2 needs to change the BD err detection
  crypto: sun8i-ss - fix infinite loop in sun8i_ss_setup_ivs()
  crypto: hisilicon/qm - modify event irq processing
  crypto: hisilicon/qm - move alloc qm->wq to qm.c
  crypto: hisilicon/qm - add functions for releasing resources
  crypto: hisilicon/trng - fix local variable type
  MAINTAINERS: update HiSilicon ZIP and QM maintainers
  ARM: dts: mediatek: adjust whitespace around '='
  arm64: dts: mediatek: adjust whitespace around '='
  arm64: dts: mediatek: mt8195: enable usb remote wakeup
  arm64: dts: mediatek: mt8195: add efuse node and cells
  arm64: dts: mt8183: add svs device information
  soc: mediatek: SVS: add mt8192 SVS GPU driver
  dt-bindings: soc: mediatek: add mt8192 svs dt-bindings
  soc: mediatek: SVS: add debug commands
  soc: mediatek: SVS: add monitor mode
  soc: mediatek: SVS: introduce MTK SVS engine
  dt-bindings: soc: mediatek: add mtk svs dt-bindings
  ARM: dts: rza2mevb: Fix LED node names
  arm64: dts: renesas: Fix thermal-sensors on single-zone sensors
  arm64: dts: renesas: spider-cpu: Enable SCIF0 on second connector
  arm64: dts: renesas: r8a779f0: Add SCIF nodes
  arm64: dts: renesas: r8a779f0: Add HSCIF nodes
  arm64: dts: renesas: r8a779f0: Add DMA properties to SCIF3
  arm64: dts: renesas: Add missing space after remote-endpoint
  arm64: dts: renesas: rzg2ul-smarc-som: Enable ADC on SMARC platform
  arm64: dts: renesas: rzg2ul-smarc: Enable RSPI1 on carrier board
  arm64: dts: renesas: r8a779f0: Add CPU core clocks
  arm64: dts: renesas: r8a779f0: Add CPUIdle support
  arm64: dts: renesas: r8a779f0: Add secondary CA55 CPU cores
  arm64: dts: renesas: r8a779f0: Add L3 cache controller
  arm64: dts: renesas: r8a779a0: Add CPU0 core clock
  arm64: dts: renesas: r8a779a0: Update to R-Car Gen4 compatible values
  ata: libata-core: make ata_exec_internal_sg() *static*
  soc: amlogic: Fix refcount leak in meson-secure-pwrc.c
  ARM: dts: r9a06g032-rzn1d400-db: Enable rtc0
  arm64: dts: renesas: rzg2l-smarc: Use proper bool operator
  arm64: dts: renesas: r8a779f0: Add UFS node
  arm64: dts: renesas: r8a779f0: Add iommus to DMAC nodes
  arm64: dts: renesas: r8a779f0: Add IPMMU nodes
  arm64: dts: renesas: Adjust whitespace around '='
  arm64: dts: renesas: r8a779f0: Add thermal support
  ata: make transfer mode masks *unsigned int*
  dt-bindings: soc: renesas: Move renesas,prr from arm to soc
  arm64: dts: microchip: adjust whitespace around '='
  arm64: dts: sprd: adjust whitespace around '='
  arm64: dts: hisilicon: adjust whitespace around '='
  arm64: dts: marvell: adjust whitespace around '='
  arm64: dts: lg: adjust whitespace around '='
  arm64: dts: apm: adjust whitespace around '='
  arm64: dts: amd: adjust whitespace around '='
  ARM: dts: sd: adjust whitespace around '='
  ARM: dts: sti: adjust whitespace around '='
  ARM: dts: ste: adjust whitespace around '='
  ARM: dts: nuvoton: adjust whitespace around '='
  ARM: dts: lpc: adjust whitespace around '='
  ARM: dts: ecx: adjust whitespace around '='
  ARM: dts: alpine: adjust whitespace around '='
  ARM: dts: spear: adjust whitespace around '='
  ARM: dts: axm: adjust whitespace around '='
  ARM: dts: at91: adjust whitespace around '='
  ARM: dts: aspeed: adjust whitespace around '='
  ARM: dts: pxa: adjust whitespace around '='
  cgroup.c: add helper __cset_cgroup_from_root to cleanup duplicated codes
  dmaengine: dw-edma: Remove unused irq field in struct dw_edma_chip
  spi: microchip-core: fix passing zero to PTR_ERR warning
  ARM: dts: s5pv210: align gpio-key node names with dtschema
  ARM: dts: exynos: align gpio-key node names with dtschema
  PCI: mediatek-gen3: Print LTSSM state when PCIe link down
  MAINTAINERS: Add BCM6813 to bcmbca arch entry
  arm64: dts: Add DTS files for bcmbca SoC BCM6813
  dt-bindings: arm64: Add BCM6813 SoC
  ARM: dts: Add PCIe support for Airoha EN7523
  efi: Correct comment on efi_memmap_alloc
  PCI: mediatek: Allow building for ARCH_AIROHA
  dt-bindings: PCI: mediatek: Add Airoha EN7532 support
  selftests/timens: add a test for vfork+exit
  fs/exec: allow to unshare a time namespace on vfork+exec
  arm64: dts: Add support for Stratix 10 Software Virtual Platform
  dt-bindings: altera: document Stratix 10 SWVP compatibles
  regmap: provide regmap_field helpers for simple bit operations
  memblock: Disable mirror feature if kernelcore is not specified
  arm64: mm: Only remove nomap flag for initrd
  mm: Limit warning message in vmemmap_verify() to once
  mm: Ratelimited mirrored memory related warning messages
  efi: Make code to find mirrored memory ranges generic
  selinux: Add boundary check in put_entry()
  ARM: dts: allwinner: align gpio-key node names with dtschema
  arm64: dts: allwinner: align gpio-key node names with dtschema
  dt-bindings: timer: Add Nomadik MTU binding
  arm64: dts: altera: adjust whitespace around '='
  ARM: dts: Add DTS files for bcmbca SoC BCM63148
  dt-bindings: arm: Add BCM63148 SoC
  dt-bindings: arm64: Add BCM6856 SoC
  dt-bindings: arm64: Add BCM63146 SoC
  ARM: dts: broadcom: correct gpio-keys properties
  ARM: dts: broadcom: align gpio-key node names with dtschema
  ARM: dts: Add DTS files for bcmbca SoC BCM6756
  dt-bindings: arm: Add BCM6756 SoC
  ARM: dts: Add DTS files for bcmbca SoC BCM6855
  arm64: dts: intel: socfpga_agilex: use defined GIC interrupt type for ECC
  dt-bindings: altera: Add Chameleon v3 board
  ARM: dts: socfpga: Add Google Chameleon v3 devicetree
  ARM: dts: socfpga: Add atsha204a node to Mercury+ AA1 dts
  ARM: dts: socfpga: Move sdmmc-ecc node to Arria 10 dts
  ARM: dts: socfpga: Change Mercury+ AA1 dts to dtsi
  thermal: Directly use ida_alloc()/free()
  spi: core: Fix error code in spi_register_controller()
  cpuidle: haltpoll: Add trace points for guest_halt_poll_ns grow/shrink
  cpufreq: Drop unnecessary cpus locking from store()
  cpufreq: Optimize cpufreq_show_cpus()
  arm64: dts: arm: adjust whitespace around '='
  arm64: dts: fsl: adjust whitespace around '='
  arm64: dts: fsl-ls10xx: use generic dma node name
  arm64: dts: imx8mp-evk: add regulator supply to CPU nodes
  arm64: dts: imx8mm: Add SNVS LPGPR
  arm64: dts: fsl: ls1012a: fix Micron SPI NOR compatible
  ata: libata-core: get rid of *else* branches in ata_id_n_sectors()
  spi: microchip-core: fix potentially incorrect return from probe
  PCI: aardvark: Fix reporting Slot capabilities on emulated bridge
  PCI: aardvark: Add support for AER registers on emulated bridge
  selinux: fix memleak in security_read_state_kernel()
  MAINTAINERS: Add BCM63148 to bcmbca arch entry
  MAINTAINERS: Add BCM6856 to bcmbca arch entry
  arm64: dts: Add DTS files for bcmbca SoC BCM6856
  arm64: dts: Add DTS files for bcmbca SoC BCM63146
  MAINTAINERS: Add BCM63146 to bcmbca arch entry
  arm64: defconfig: Enable DRM_V3D
  arm64: dts: allwinner: Use constants for RTC clock indexes
  ARM: dts: sunxi: Use constants for RTC clock indexes
  docs: selinux: add '=' signs to kernel boot options
  mm: create security context for memfd_secret inodes
  audit: make is_audit_feature_set() static
  docs: Kconfig: Fix help text indentation
  docs/zh_CN: Update translation of reporting-issues.rst to 5.18
  docs/arm64: elf_hwcaps: Unify HWCAP lists as description lists
  MAINTAINERS: Add BCM6756 to bcmbca arch entry
  MAINTAINERS: Add BCM6855 to bcmbca arch entry
  dt-bindings: arm: add BCM6855 SoC to device tree binding document
  ARM: dts: bcm2711: Enable V3D
  ARM: dts: Update BCM47622 DTS file
  ARM: dts: Add DTS files for bcmbca SoC BCM6846
  ARM: configs: Enable DRM_V3D
  scripts: kernel-doc: Always increment warnings counter
  spi: spidev_test: Warn when the mode is not the requested mode
  spi: s3c64xx: set pointers to null using NULL rather than 0
  spi: micro: fix unreasonable clk_prepare_enable() on error in mchp_corespi_probe()
  spi: dt-bindings: Add compatible for Tegra241 QSPI
  spi: dt-bindings: split peripheral prods
  spi: tegra210-quad: Multi-cs support
  regulator: rpi-panel-attiny: Use backlight helper
  genirq/PM: Unexport {suspend,resume}_device_irqs()
  soc: renesas: rcar-sysc: Optimize rcar_sysc_area struct sizes
  soc: renesas: r8a779a0-sysc: Fix A2DP1 and A2CV[2357] PDR values
  arm64: dts: arm/juno: Drop erroneous 'mbox-name' property
  arm64: dts: arm/fvp-base-revc: Remove 'panel-dpi' compatible
  arm64: defconfig: Enable R8A779G0 SoC
  ARM: shmobile: defconfig: Refresh for v5.19-rc1
  sched: Remove the limitation of WF_ON_CPU on wakelist if wakee cpu is idle
  sched: Fix the check of nr_running at queue wakelist
  sched: Allow newidle balancing to bail out of load_balance
  sched/deadline: Use proc_douintvec_minmax() limit minimum value
  sched/fair: Optimize and simplify rq leaf_cfs_rq_list
  sched/fair: Consider CPU affinity when allowing NUMA imbalance in find_idlest_group()
  sched/numa: Adjust imb_numa_nr to a better approximation of memory channels
  sched/numa: Apply imbalance limitations consistently
  sched/numa: Do not swap tasks between nodes when spare capacity is available
  sched/numa: Initialise numa_migrate_retry
  arm64: dts: meson: add gpio-fan control to GS-King-X
  perf/x86/amd/uncore: Add PerfMonV2 RDPMC assignments
  perf/x86/amd/uncore: Add PerfMonV2 DF event format
  perf/x86/amd/uncore: Detect available DF counters
  perf/x86/amd/uncore: Use attr_update for format attributes
  perf/x86/amd/uncore: Use dynamic events array
  x86/events/intel/ds: Enable large PEBS for PERF_SAMPLE_WEIGHT_TYPE
  ata: libata-core: fix sloppy typing in ata_id_n_sectors()
  ata: pata_hpt3x2n: pass base DPLL frequency to hpt3x2n_pci_clock()
  ata: pata_hpt37x: merge hpt374_read_freq() to hpt37x_pci_clock()
  ata: pata_hpt37x: factor out hpt37x_pci_clock()
  ata: pata_hpt37x: move claculating PCI clock from hpt37x_clock_slot()
  ata: libata: Fix syntax errors in comments
  arm64: dts: rockchip: Add missing space around regulator-name on rk3368-orion-r68
  ARM: imx6ul: drop the adc num-channels property
  ARM: dts: fsl: adjust whitespace around '='
  ARM: imx: Kconfig: Fix indentation
  arm64: dts: rockchip: enable the gpu on BPI-R2-Pro
  arm64: dts: rockchip: configure thermal shutdown for BPI-R2-Pro
  arm64: dts: rockchip: Enable HDMI audio on BPI R2 Pro
  arm64: dts: rockchip: enable vop2 and hdmi tx on BPI-R2-Pro
  arm64: dts: rockchip: set display regulators to always-on on BPI-R2-Pro
  arm64: dts: rockchip: add RTC to BPI-R2 Pro
  arm64: dts: rockchip: Enable HDMI audio on Quartz64 A
  arm64: dts: rockchip: Add HDMI audio nodes to rk356x
  ARM: dts: imx6ulz-bsh-smm-m2: Support proper board power off
  ARM: dts: imx7-colibri: add support for Toradex Iris carrier boards
  ARM: dts: imx7-colibri: clean-up iomuxc pinctrl group naming
  ARM: dts: imx7-colibri: set regulator-name properties
  ARM: dts: imx7-colibri: remove leading zero from reg address
  ARM: dts: imx7-colibri: clean-up device enabling/disabling
  ARM: dts: imx7-colibri: alphabetical re-order
  ARM: dts: imx7-colibri: add clarifying comments
  ARM: dts: imx7-colibri-aster: add ssp aka spi cs aka ss pins
  ARM: dts: imx7-colibri: disable adc2
  ARM: dts: imx7-colibri-eval-v3: correct can controller comment
  ARM: dts: imx7d-colibri-emmc: add cpu1 supply
  ARM: dts: imx7-colibri: move rtc node
  ARM: dts: imx7-colibri: clean-up usdhc1 and add sleep config
  ARM: dts: imx7-colibri: add delay for on-module phy supply
  ARM: dts: imx7-colibri: move regulators
  ARM: dts: imx7-colibri: add ethernet aliases
  ARM: dts: imx7-colibri: move aliases, chosen, extcon and gpio-keys
  ARM: dts: imx7-colibri: improve wake-up with gpio key
  ARM: dts: imx7-colibri: improve licensing and compatible strings
  ARM: dts: imx7-colibri: add usb dual-role switching using extcon
  ARM: dts: imx7-colibri: set lcdif clock source to video pll
  ARM: dts: imx7-colibri: add mdio phy node
  ARM: dts: imx7-colibri: overhaul display/touch functionality
  ARM: dts: imx6qdl-colibri: backlight pwm: Adapt brightness steps
  ARM: dts: imx6qdl-colibri: backlight pwm: Simplify inverted backlight
  ARM: dts: imx6qdl-colibri: Mux mclk for sgtl5000 with the codec node
  keep iocb_flags() result cached in struct file
  iocb: delay evaluation of IS_SYNC(...) until we want to check IOCB_DSYNC
  struct file: use anonymous union member for rcuhead and llist
  btrfs: use IOMAP_DIO_NOSYNC
  teach iomap_dio_rw() to suppress dsync
  selinux: fix typos in comments
  arm64: dts: rockchip: adjust whitespace around '='
  ARM: dts: rockchip: adjust whitespace around '='
  PCI: vmd: Use devm_kasprintf() instead of simple kasprintf()
  spi: Fix per-cpu stats access on 32 bit systems
  spi: sifive: add PM callbacks to support suspend/resume
  crypto: sun8i-ss - fix a NULL vs IS_ERR() check in sun8i_ss_hashkey
  crypto: octeontx2 - fix potential null pointer access
  crypto: blake2s - remove shash module
  crypto: memneq - move into lib/
  crypto: octeontx2 - add firmware version in devlink info
  crypto: ccp - fix typo in comment
  crypto: hisilicon/sec - fix typos in comment
  fscrypt: Add HCTR2 support for filename encryption
  crypto: arm64/polyval - Add PMULL accelerated implementation of POLYVAL
  crypto: x86/polyval - Add PCLMULQDQ accelerated implementation of POLYVAL
  crypto: arm64/aes-xctr - Improve readability of XCTR and CTR modes
  crypto: arm64/aes-xctr - Add accelerated implementation of XCTR
  crypto: x86/aesni-xctr - Add accelerated implementation of XCTR
  crypto: hctr2 - Add HCTR2 support
  crypto: polyval - Add POLYVAL support
  crypto: xctr - Add XCTR support
  crypto: atmel-ecc - Remove duplicated error reporting in .remove()
  crypto: sun8i-ss - Fix error codes for dma_mapping_error()
  crypto: sun8i-ss - fix error codes in allocate_flows()
  crypto: ccp - Use kzalloc for sev ioctl interfaces to prevent kernel memory leak
  arm64: dts: imx8ulp: address build warning
  arm64: defconfig: enable i.MX93 clk & pinctrl
  arm64: dts: freescale: add i.MX93 11x11 EVK basic support
  arm64: dts: freescale: Add i.MX93 dtsi support
  arm64: dts: amlogic: align gpio-key node names with dtschema
  arm64: dts: amlogic: correct gpio-keys properties
  arm64: dts: meson: add reset controller for Meson-S4 SoC
  arm64: dts: amlogic: adjust whitespace around '='
  ARM: dts: meson: adjust whitespace around '='
  PCI: Add ACS quirk for Broadcom BCM5750x NICs
  ACPI: APEI: Fix double word in a comment
  ACPI: processor/idle: Annotate more functions to live in cpuidle section
  PCI: switchtec: Prefer ida_alloc()/free() over ida_simple_get()/remove()
  PCI: mediatek-gen3: Fix refcount leak in mtk_pcie_init_irq_domains()
  ARM: s3c: Kconfig.s3c64xx: Fix indentation
  ARM: s3c: Kconfig.s3c24xx: Fix indentation and replace some tabs
  ARM: s3c: Kconfig: Fix indentation
  9p: handling Rerror without copy_from_iter_full()
  spi: atmel-quadspi: align condition to parenthesis
  spi: atmel-quadspi: use pm_ptr()
  spi: atmel-quadspi: add runtime pm support
  net: macb: change return type for gem_ptp_set_one_step_sync()
  spi: Return true/false (not 1/0) from bool function
  spi: fix platform_no_drv_owner.cocci warning
  vmxnet3: update to version 7
  vmxnet3: use ext1 field to indicate encapsulated packet
  vmxnet3: limit number of TXDs used for TSO packet
  vmxnet3: add command to set ring buffer sizes
  vmxnet3: add support for out of order rx completion
  vmxnet3: add support for large passthrough BAR register
  vmxnet3: add support for capability registers
  vmxnet3: prepare for version 7 changes
  xen/netback: do some code cleanup
  PCI: tegra194: Fix PM error handling in tegra_pcie_config_ep()
  PCI: microchip: Fix refcount leak in mc_pcie_init_irq_domains()
  PCI/ERR: Recognize disconnected devices in report_error_detected()
  x86: Fix comment for X86_FEATURE_ZEN
  x86: Remove vendor checks from prefer_mwait_c1_over_halt
  x86: Handle idle=nomwait cmdline properly for x86_idle
  net: constify some inline functions in sock.h
  nfp: Remove kernel.h when not needed
  spi: <linux/spi/spi.h>: Add missing documentation for struct members
  dt-bindings: Add headers for Tegra234 GPCDMA
  ARM: tegra: Adjust whitespace around '='
  arm64: defconfig: Build Tegra OPE module
  spi: s3c64xx: Fix spelling mistake "hannel" -> "channel"
  ARM: bcm: Fix refcount leak in bcm_kona_smc_init
  MAINTAINERS: Add BCM6846 to bcmbca arch entry
  dt-bindings: arm: add BCM6846 SoC to device tree binding document
  ARM: dts: broadcom: adjust whitespace around '='
  arm64: dts: broadcom: adjust whitespace around '='
  MAINTAINERS: Add BCM6878 to bcmbca arch entry
  MAINTAINERS: Add BCM6858 to bcmbca arch entry
  MAINTAINERS: Add BCM4912 to bcmbca arch entry
  MAINTAINERS: Add BCM63158 to bcmbca arch entry
  MAINTAINERS: Add BCM63178 to bcmbca arch entry
  ARM: dts: Add DTS files for bcmbca SoC BCM6878
  dt-bindings: arm: Add BCM6878 soc
  ARM64: dts: Add DTS files for bcmbca SoC BCM6858
  arm64: dts: Add DTS files for bcmbca SoC BCM4912
  arm64: dts: Add DTS files for bcmbca SoC BCM63158
  dt-bindings: arm64: Add BCM6858 SoC to binding document
  dt-bindings: arm64: Add BCM4912 SoC to binding document
  dt-bindings: arm64: add BCM63158 SoC to binding document
  ARM: dts: add dts files for bcmbca soc 63178
  dt-bindings: arm: add BCM63178 SoC to binding document
  ARM: dts: bcm283x: Drop unnecessary properties from dpi node
  arm64: defconfig: enable bcmbca soc support
  arm64: bcmbca: add arch bcmbca machine entry
  soc: bcm: brcmstb: pm: pm-arm: fix typo in comment
  net: ethernet: mtk_eth_soc: enable rx cksum offload for MTK_NETSYS_V2
  net: dsa: microchip: ksz8xxx: Replace kernel.h with the necessary inclusions
  x86/pkeys: Clarify PKRU_AD_KEY macro
  Documentation/protection-keys: Clean up documentation for User Space pkeys
  selinux: drop unnecessary NULL check
  No need of likely/unlikely on calls of check_copy_size()
  selinux: add __randomize_layout to selinux_audit_data
  audit: remove redundant data_len check
  regulator: qcom_smd: add get_voltage to MP5496
  iavf: Add waiting for response from PF in set mac
  i40e: Add VF VLAN pruning
  psi: dont alloc memory for psi by default
  arm64: dts: mediatek: Add mediatek,cci property for MT8183 cpufreq
  arm64: dts: mediatek: Add MediaTek CCI node for MT8183
  arm64: dts: mediatek: Add opp table and clock property for MT8183 cpufreq
  ARM: dts: add clock support for Airoha EN7523
  soc: mediatek: devapc: Add support for MT8186
  soc: mediatek: devapc: Separate register offsets from mtk_devapc_data
  dt-bindings: soc: mediatek: devapc: Add bindings for MT8186
  soc: mediatek: pwrap: Compress of_device_id entries to one line
  soc: mediatek: pwrap: Move IO pointers to new structure
  soc: mediatek: pwrap: Check return value of platform_get_irq()
  soc: mediatek: pwrap: Switch to devm_platform_ioremap_resource_byname()
  soc: mediatek: pwrap: Use readx_poll_timeout() instead of custom function
  ASoC: dt-bindings: renesas,rz-ssi: Document RZ/G2UL SoC
  regulator: mp5416: remove kernel.h include
  x86/mm/tlb: Avoid reading mm_tlb_gen when possible
  MAINTAINERS: add spi to PolarFire SoC entry
  spi: add support for microchip fpga spi controllers
  ARM: s3c: Use strscpy to replace strlcpy
  regulator: dt-bindings: Convert pwm-regulator to DT schema
  net: dropreason: reformat the comment fo skb drop reasons
  net: skb: use auto-generation to convert skb drop reason to string
  net: skb: move enum skb_drop_reason to standalone header file
  ARM: dts: rockchip: enable nfc node in rk3066a-mk808.dts
  arm64: dts: rockchip: enable vop2 and hdmi tx on rock-3a
  arm64: dts: rockchip: enable vop2 and hdmi tx on quartz64a
  arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi
  arm64: dts: rockchip: rk356x: Add HDMI nodes
  arm64: dts: rockchip: rk356x: Add VOP2 nodes
  arm64: dts: rockchip: add pine64 touch panel display to rockpro64
  arm64: dts: rockchip: Enable PCIe controller on quartz64-a
  arm64: dts: rockchip: Add rk3568 PCIe2x1 controller
  net: altera: Replace kernel.h with the necessary inclusions
  WAN: Fix syntax errors in comments
  arm64: dts: rockchip: enable sfc controller on Quartz64 Model A
  arm64: dts: rockchip: enable sdr-104 for sdmmc on Quartz A
  arm64: dts: rockchip: add Quartz64-A fan pinctrl
  arm64: dts: exynos: enable secondary ufs devices ExynosAutov9 SADK
  arm64: dts: exynos: add secondary ufs devices in ExynosAutov9
  arm64: dts: fsd: use local header for pinctrl register values
  arm64: dts: exynos: use local header for pinctrl register values
  ARM: dts: exynos: use local header for pinctrl register values
  ARM: dts: s5pv210: use local header for pinctrl register values
  ARM: dts: s3c64xx: use local header for pinctrl register values
  ARM: dts: s3c2410: use local header for pinctrl register values
  ARM: dts: exynos: align MMC node name with dtschema
  arm64: dts: exynos: align MMC node name with dtschema
  arm64: dts: exynos: adjust DT style of ufs nodes in ExynosAutov9
  ARM: dts: exynos: adjust whitespace around '='
  arm64: dts: exynos: adjust whitespace around '='
  ARM: dts: sun5i: adjust whitespace around '='
  spi: spi-ti-qspi: Support per-transfer and per-slave speed_hz settings
  spi: spi.c: Convert statistics to per-cpu u64_stats_t
  spi: dt-bindings: Move 'rx-sample-delay-ns' to spi-peripheral-props.yaml
  spi: intel: Use correct order for the parameters of devm_kcalloc()
  spi: spi-zynqmp-gqspi: Add two chip select support
  spi: fix typo in comment
  spi: mt65xx: add MT8365 SoC bindings
  spi: cadence-quadspi: Remove spi_master_put() in probe failure path
  spi: s3c64xx: requests spi-dma channel only during data transfer
  spi: spi-altera-dfl: Fix an error handling path
  spi: stm32-qspi: Remove stm32_qspi_wait_poll_status() unused parameter
  spi: stm32-qspi: Remove stm32_qspi_wait_cmd() unused parameter
  spi: stm32-qspi: Remove stm32_qspi_get_mode() unused parameter
  regulator: rt5190a: check if init_data is NULL, bypass rt5190a_of_parse_cb
  regulator: mp5416: add support for MP5496
  regulator: mp5416: use OF match data
  regulator: mp5416: alphabetically sort header includes
  regulator: dt-bindings: mps,mp5416: add MP5496 compatible
  regmap: cache: Fix syntax errors in comments
  memory: mtk-smi: Add support for MT6795 Helio X10
  dt-bindings: memory: mtk-smi: Add MT6795 Helio X10 bindings
  arm64: dts: fsd: add ufs device node
  arm64: dts: exynos: add watchdog in ExynosAutov9
  arm64: dts: exynos: add syscon reboot/reboot_mode support in ExynosAutov9
  dt-bindings: soc: add samsung,boot-mode definitions
  arm64: dts: fsd: Add cpu cache information
  arm64: dts: renesas: rzv2mevk2: Enable ethernet
  arm64: dts: renesas: r9a09g011: Add ethernet nodes
  arm64: dts: renesas: Rename numbered regulators
  arm64: dts: renesas: beacon: Fix regulator node names
  arm64: dts: renesas: r9a07g043: Add ADC node
  ARM: dts: exynos: add panel and backlight to p4note
  meson-mx-socinfo: Fix refcount leak in meson_mx_socinfo_init
  pstore: migrate to crypto acomp interface

Bug: 147209885
Bug: 160883266
Bug: 160883801
Bug: 170507310
Bug: 178022444
Bug: 187186685
Bug: 188684133
Bug: 200103201
Bug: 231160619
Bug: 242078480
Change-Id: I16007c8ca186db4baf8c3e649059c10850e9031b
Signed-off-by: jianzhou <quic_jianzhou@quicinc.com>

Documentation/ABI/stable/sysfs-block

@@ -260,6 +260,15 @@ Description:
 		for discards, and don't read this file.
 
 
+What:		/sys/block/<disk>/queue/dma_alignment
+Date:		May 2022
+Contact:	linux-block@vger.kernel.org
+Description:
+		Reports the alignment that user space addresses must have to be
+		used for raw block device access with O_DIRECT and other driver
+		specific passthrough mechanisms.
+
+
 What:		/sys/block/<disk>/queue/fua
 Date:		May 2018
 Contact:	linux-block@vger.kernel.org

Documentation/ABI/testing/sysfs-class-hwmon

@@ -938,3 +938,12 @@ Description:
 		- 1: enable
 
 		RW
+
+What:		/sys/class/hwmon/hwmonX/device/pec
+Description:
+		PEC support on I2C devices
+
+		- 0, off, n: disable
+		- 1, on, y: enable
+
+		RW

Documentation/ABI/testing/sysfs-devices-system-cpu

@@ -493,12 +493,13 @@ What:		/sys/devices/system/cpu/cpuX/regs/
 		/sys/devices/system/cpu/cpuX/regs/identification/
 		/sys/devices/system/cpu/cpuX/regs/identification/midr_el1
 		/sys/devices/system/cpu/cpuX/regs/identification/revidr_el1
+		/sys/devices/system/cpu/cpuX/regs/identification/smidr_el1
 Date:		June 2016
 Contact:	Linux ARM Kernel Mailing list <linux-arm-kernel@lists.infradead.org>
 Description:	AArch64 CPU registers
 
 		'identification' directory exposes the CPU ID registers for
-		identifying model and revision of the CPU.
+		identifying model and revision of the CPU and SMCU.
 
 What:		/sys/devices/system/cpu/aarch32_el0
 Date:		May 2021

Documentation/ABI/testing/sysfs-driver-qat

@@ -0,0 +1,49 @@
+What:		/sys/bus/pci/devices/<BDF>/qat/state
+Date:		June 2022
+KernelVersion:	5.20
+Contact:	qat-linux@intel.com
+Description:	(RW) Reports the current state of the QAT device. Write to
+		the file to start or stop the device.
+
+		The values are:
+
+		* up: the device is up and running
+		* down: the device is down
+
+
+		It is possible to transition the device from up to down only
+		if the device is up and vice versa.
+
+		This attribute is only available for qat_4xxx devices.
+
+What:		/sys/bus/pci/devices/<BDF>/qat/cfg_services
+Date:		June 2022
+KernelVersion:	5.20
+Contact:	qat-linux@intel.com
+Description:	(RW) Reports the current configuration of the QAT device.
+		Write to the file to change the configured services.
+
+		The values are:
+
+		* sym;asym: the device is configured for running crypto
+		  services
+		* dc: the device is configured for running compression services
+
+		It is possible to set the configuration only if the device
+		is in the `down` state (see /sys/bus/pci/devices/<BDF>/qat/state)
+
+		The following example shows how to change the configuration of
+		a device configured for running crypto services in order to
+		run data compression::
+
+			# cat /sys/bus/pci/devices/<BDF>/qat/state
+			up
+			# cat /sys/bus/pci/devices/<BDF>/qat/cfg_services
+			sym;asym
+			# echo down > /sys/bus/pci/devices/<BDF>/qat/state
+			# echo dc > /sys/bus/pci/devices/<BDF>/qat/cfg_services
+			# echo up > /sys/bus/pci/devices/<BDF>/qat/state
+			# cat /sys/bus/pci/devices/<BDF>/qat/cfg_services
+			dc
+
+		This attribute is only available for qat_4xxx devices.

Documentation/ABI/testing/sysfs-firmware-qemu_fw_cfg

@@ -12,8 +12,9 @@ Description:
 		configuration data to the guest userspace.
 
 		The authoritative guest-side hardware interface documentation
-		to the fw_cfg device can be found in "docs/specs/fw_cfg.txt"
-		in the QEMU source tree.
+		to the fw_cfg device can be found in "docs/specs/fw_cfg.rst"
+		in the QEMU source tree, or online at:
+		https://qemu-project.gitlab.io/qemu/specs/fw_cfg.html
 
 		**SysFS fw_cfg Interface**
 

Documentation/Kconfig

@@ -1,23 +1,22 @@
 config WARN_MISSING_DOCUMENTS
-
 	bool "Warn if there's a missing documentation file"
 	depends on COMPILE_TEST
 	help
-	   It is not uncommon that a document gets renamed.
-	   This option makes the Kernel to check for missing dependencies,
-	   warning when something is missing. Works only if the Kernel
-	   is built from a git tree.
+	  It is not uncommon that a document gets renamed.
+	  This option makes the Kernel to check for missing dependencies,
+	  warning when something is missing. Works only if the Kernel
+	  is built from a git tree.
 
-	   If unsure, select 'N'.
+	  If unsure, select 'N'.
 
 config WARN_ABI_ERRORS
 	bool "Warn if there are errors at ABI files"
 	depends on COMPILE_TEST
 	help
-	   The files under Documentation/ABI should follow what's
-	   described at Documentation/ABI/README. Yet, as they're manually
-	   written, it would be possible that some of those files would
-	   have errors that would break them for being parsed by
-	   scripts/get_abi.pl. Add a check to verify them.
+	  The files under Documentation/ABI should follow what's
+	  described at Documentation/ABI/README. Yet, as they're manually
+	  written, it would be possible that some of those files would
+	  have errors that would break them for being parsed by
+	  scripts/get_abi.pl. Add a check to verify them.
 
-	   If unsure, select 'N'.
+	  If unsure, select 'N'.

Documentation/PCI/pci-iov-howto.rst

@@ -125,14 +125,14 @@ Following piece of code illustrates the usage of the SR-IOV API.
 		...
 	}
 
-	static int dev_suspend(struct pci_dev *dev, pm_message_t state)
+	static int dev_suspend(struct device *dev)
 	{
 		...
 
 		return 0;
 	}
 
-	static int dev_resume(struct pci_dev *dev)
+	static int dev_resume(struct device *dev)
 	{
 		...
 
@@ -165,8 +165,7 @@ Following piece of code illustrates the usage of the SR-IOV API.
 		.id_table =	dev_id_table,
 		.probe =	dev_probe,
 		.remove =	dev_remove,
-		.suspend =	dev_suspend,
-		.resume =	dev_resume,
+		.driver.pm =	&dev_pm_ops,
 		.shutdown =	dev_shutdown,
 		.sriov_configure = dev_sriov_configure,
 	};

Documentation/PCI/sysfs-pci.rst

@@ -125,7 +125,7 @@ implementation of that functionality. To support the historical interface of
 mmap() through files in /proc/bus/pci, platforms may also set HAVE_PCI_MMAP.
 
 Alternatively, platforms which set HAVE_PCI_MMAP may provide their own
-implementation of pci_mmap_page_range() instead of defining
+implementation of pci_mmap_resource_range() instead of defining
 ARCH_GENERIC_PCI_MMAP_RESOURCE.
 
 Platforms which support write-combining maps of PCI resources must define

Documentation/RCU/Design/Requirements/Requirements.rst

@@ -1844,10 +1844,10 @@ that meets this requirement.
 
 Furthermore, NMI handlers can be interrupted by what appear to RCU to be
 normal interrupts. One way that this can happen is for code that
-directly invokes rcu_irq_enter() and rcu_irq_exit() to be called
+directly invokes ct_irq_enter() and ct_irq_exit() to be called
 from an NMI handler. This astonishing fact of life prompted the current
-code structure, which has rcu_irq_enter() invoking
-rcu_nmi_enter() and rcu_irq_exit() invoking rcu_nmi_exit().
+code structure, which has ct_irq_enter() invoking
+ct_nmi_enter() and ct_irq_exit() invoking ct_nmi_exit().
 And yes, I also learned of this requirement the hard way.
 
 Loadable Modules
@@ -2195,7 +2195,7 @@ scheduling-clock interrupt be enabled when RCU needs it to be:
    sections, and RCU believes this CPU to be idle, no problem. This
    sort of thing is used by some architectures for light-weight
    exception handlers, which can then avoid the overhead of
-   rcu_irq_enter() and rcu_irq_exit() at exception entry and
+   ct_irq_enter() and ct_irq_exit() at exception entry and
    exit, respectively. Some go further and avoid the entireties of
    irq_enter() and irq_exit().
    Just make very sure you are running some of your tests with
@@ -2226,7 +2226,7 @@ scheduling-clock interrupt be enabled when RCU needs it to be:
 +-----------------------------------------------------------------------+
 | **Answer**:                                                           |
 +-----------------------------------------------------------------------+
-| One approach is to do ``rcu_irq_exit();rcu_irq_enter();`` every so    |
+| One approach is to do ``ct_irq_exit();ct_irq_enter();`` every so      |
 | often. But given that long-running interrupt handlers can cause other |
 | problems, not least for response time, shouldn't you work to keep     |
 | your interrupt handler's runtime within reasonable bounds?            |

Documentation/RCU/stallwarn.rst

@@ -97,12 +97,12 @@ warnings:
 	which will include additional debugging information.
 
 -	A low-level kernel issue that either fails to invoke one of the
-	variants of rcu_user_enter(), rcu_user_exit(), rcu_idle_enter(),
-	rcu_idle_exit(), rcu_irq_enter(), or rcu_irq_exit() on the one
+	variants of rcu_eqs_enter(true), rcu_eqs_exit(true), ct_idle_enter(),
+	ct_idle_exit(), ct_irq_enter(), or ct_irq_exit() on the one
 	hand, or that invokes one of them too many times on the other.
 	Historically, the most frequent issue has been an omission
 	of either irq_enter() or irq_exit(), which in turn invoke
-	rcu_irq_enter() or rcu_irq_exit(), respectively.  Building your
+	ct_irq_enter() or ct_irq_exit(), respectively.  Building your
 	kernel with CONFIG_RCU_EQS_DEBUG=y can help track down these types
 	of issues, which sometimes arise in architecture-specific code.
 

Documentation/admin-guide/cgroup-v1/memcg_test.rst

@@ -97,7 +97,7 @@ Under below explanation, we assume CONFIG_MEM_RES_CTRL_SWAP=y.
 =============
 
 	Page Cache is charged at
-	- add_to_page_cache_locked().
+	- filemap_add_folio().
 
 	The logic is very clear. (About migration, see below)
 

Documentation/admin-guide/cgroup-v2.rst

@@ -184,6 +184,14 @@ cgroup v2 currently supports the following mount options.
 	ignored on non-init namespace mounts.  Please refer to the
 	Delegation section for details.
 
+  favordynmods
+        Reduce the latencies of dynamic cgroup modifications such as
+        task migrations and controller on/offs at the cost of making
+        hot path operations such as forks and exits more expensive.
+        The static usage pattern of creating a cgroup, enabling
+        controllers, and then seeding it with CLONE_INTO_CGROUP is
+        not affected by this option.
+
   memory_localevents
         Only populate memory.events with data for the current cgroup,
         and not any subtrees. This is legacy behaviour, the default

Documentation/admin-guide/device-mapper/writecache.rst

@@ -20,6 +20,7 @@ Constructor parameters:
    size)
 5. the number of optional parameters (the parameters with an argument
    count as two)
+
 	start_sector n		(default: 0)
 		offset from the start of cache device in 512-byte sectors
 	high_watermark n	(default: 50)
@@ -74,20 +75,21 @@ Constructor parameters:
 		the origin volume in the last n milliseconds
 
 Status:
+
 1. error indicator - 0 if there was no error, otherwise error number
 2. the number of blocks
 3. the number of free blocks
 4. the number of blocks under writeback
-5. the number of read requests
-6. the number of read requests that hit the cache
-7. the number of write requests
-8. the number of write requests that hit uncommitted block
-9. the number of write requests that hit committed block
-10. the number of write requests that bypass the cache
-11. the number of write requests that are allocated in the cache
+5. the number of read blocks
+6. the number of read blocks that hit the cache
+7. the number of write blocks
+8. the number of write blocks that hit uncommitted block
+9. the number of write blocks that hit committed block
+10. the number of write blocks that bypass the cache
+11. the number of write blocks that are allocated in the cache
 12. the number of write requests that are blocked on the freelist
 13. the number of flush requests
-14. the number of discard requests
+14. the number of discarded blocks
 
 Messages:
 	flush

Documentation/admin-guide/devices.rst

@@ -7,10 +7,9 @@ This list is the Linux Device List, the official registry of allocated
 device numbers and ``/dev`` directory nodes for the Linux operating
 system.
 
-The LaTeX version of this document is no longer maintained, nor is
-the document that used to reside at lanana.org.  This version in the
-mainline Linux kernel is the master document.  Updates shall be sent
-as patches to the kernel maintainers (see the
+The version of this document at lanana.org is no longer maintained.  This
+version in the mainline Linux kernel is the master document.  Updates
+shall be sent as patches to the kernel maintainers (see the
 :ref:`Documentation/process/submitting-patches.rst <submittingpatches>` document).
 Specifically explore the sections titled "CHAR and MISC DRIVERS", and
 "BLOCK LAYER" in the MAINTAINERS file to find the right maintainers

Documentation/admin-guide/efi-stub.rst

@@ -7,10 +7,10 @@ as a PE/COFF image, thereby convincing EFI firmware loaders to load
 it as an EFI executable. The code that modifies the bzImage header,
 along with the EFI-specific entry point that the firmware loader
 jumps to are collectively known as the "EFI boot stub", and live in
-arch/x86/boot/header.S and arch/x86/boot/compressed/eboot.c,
+arch/x86/boot/header.S and drivers/firmware/efi/libstub/x86-stub.c,
 respectively. For ARM the EFI stub is implemented in
 arch/arm/boot/compressed/efi-header.S and
-arch/arm/boot/compressed/efi-stub.c. EFI stub code that is shared
+drivers/firmware/efi/libstub/arm32-stub.c. EFI stub code that is shared
 between architectures is in drivers/firmware/efi/libstub.
 
 For arm64, there is no compressed kernel support, so the Image itself

Documentation/admin-guide/kernel-parameters.txt

@@ -400,6 +400,12 @@
 	arm64.nomte	[ARM64] Unconditionally disable Memory Tagging Extension
 			support
 
+	arm64.nosve	[ARM64] Unconditionally disable Scalable Vector
+			Extension support
+
+	arm64.nosme	[ARM64] Unconditionally disable Scalable Matrix
+			Extension support
+
 	ataflop=	[HW,M68k]
 
 	atarimouse=	[HW,MOUSE] Atari Mouse
@@ -550,7 +556,7 @@
 			nosocket -- Disable socket memory accounting.
 			nokmem -- Disable kernel memory accounting.
 
-	checkreqprot	[SELINUX] Set initial checkreqprot flag value.
+	checkreqprot=	[SELINUX] Set initial checkreqprot flag value.
 			Format: { "0" | "1" }
 			See security/selinux/Kconfig help text.
 			0 -- check protection applied by kernel (includes
@@ -1439,7 +1445,7 @@
 			(in particular on some ATI chipsets).
 			The kernel tries to set a reasonable default.
 
-	enforcing	[SELINUX] Set initial enforcing status.
+	enforcing=	[SELINUX] Set initial enforcing status.
 			Format: {"0" | "1"}
 			See security/selinux/Kconfig help text.
 			0 -- permissive (log only, no denials).
@@ -3111,7 +3117,7 @@
 			mem_encrypt=on:		Activate SME
 			mem_encrypt=off:	Do not activate SME
 
-			Refer to Documentation/virt/kvm/amd-memory-encryption.rst
+			Refer to Documentation/virt/kvm/x86/amd-memory-encryption.rst
 			for details on when memory encryption can be activated.
 
 	mem_sleep_default=	[SUSPEND] Default system suspend mode:
@@ -3169,7 +3175,7 @@
 				improves system performance, but it may also
 				expose users to several CPU vulnerabilities.
 				Equivalent to: nopti [X86,PPC]
-					       kpti=0 [ARM64]
+					       if nokaslr then kpti=0 [ARM64]
 					       nospectre_v1 [X86,PPC]
 					       nobp=0 [S390]
 					       nospectre_v2 [X86,PPC,S390,ARM64]
@@ -3669,6 +3675,9 @@
 			just as if they had also been called out in the
 			rcu_nocbs= boot parameter.
 
+			Note that this argument takes precedence over
+			the CONFIG_RCU_NOCB_CPU_DEFAULT_ALL option.
+
 	noiotrap	[SH] Disables trapped I/O port accesses.
 
 	noirqdebug	[X86-32] Disables the code which attempts to detect and
@@ -3743,11 +3752,6 @@
 	noreplace-smp	[X86-32,SMP] Don't replace SMP instructions
 			with UP alternatives
 
-	nordrand	[X86] Disable kernel use of the RDRAND and
-			RDSEED instructions even if they are supported
-			by the processor.  RDRAND and RDSEED are still
-			available to user space applications.
-
 	noresume	[SWSUSP] Disables resume and restores original swap
 			space.
 
@@ -4567,6 +4571,9 @@
 			no-callback mode from boot but the mode may be
 			toggled at runtime via cpusets.
 
+			Note that this argument takes precedence over
+			the CONFIG_RCU_NOCB_CPU_DEFAULT_ALL option.
+
 	rcu_nocb_poll	[KNL]
 			Rather than requiring that offloaded CPUs
 			(specified by rcu_nocbs= above) explicitly
@@ -4676,6 +4683,34 @@
 			When RCU_NOCB_CPU is set, also adjust the
 			priority of NOCB callback kthreads.
 
+	rcutree.rcu_divisor= [KNL]
+			Set the shift-right count to use to compute
+			the callback-invocation batch limit bl from
+			the number of callbacks queued on this CPU.
+			The result will be bounded below by the value of
+			the rcutree.blimit kernel parameter.  Every bl
+			callbacks, the softirq handler will exit in
+			order to allow the CPU to do other work.
+
+			Please note that this callback-invocation batch
+			limit applies only to non-offloaded callback
+			invocation.  Offloaded callbacks are instead
+			invoked in the context of an rcuoc kthread, which
+			scheduler will preempt as it does any other task.
+
+	rcutree.nocb_nobypass_lim_per_jiffy= [KNL]
+			On callback-offloaded (rcu_nocbs) CPUs,
+			RCU reduces the lock contention that would
+			otherwise be caused by callback floods through
+			use of the ->nocb_bypass list.	However, in the
+			common non-flooded case, RCU queues directly to
+			the main ->cblist in order to avoid the extra
+			overhead of the ->nocb_bypass list and its lock.
+			But if there are too many callbacks queued during
+			a single jiffy, RCU pre-queues the callbacks into
+			the ->nocb_bypass queue.  The definition of "too
+			many" is supplied by this kernel boot parameter.
+
 	rcutree.rcu_nocb_gp_stride= [KNL]
 			Set the number of NOCB callback kthreads in
 			each group, which defaults to the square root

Documentation/admin-guide/perf/hns3-pmu.rst

@@ -0,0 +1,136 @@
+======================================
+HNS3 Performance Monitoring Unit (PMU)
+======================================
+
+HNS3(HiSilicon network system 3) Performance Monitoring Unit (PMU) is an
+End Point device to collect performance statistics of HiSilicon SoC NIC.
+On Hip09, each SICL(Super I/O cluster) has one PMU device.
+
+HNS3 PMU supports collection of performance statistics such as bandwidth,
+latency, packet rate and interrupt rate.
+
+Each HNS3 PMU supports 8 hardware events.
+
+HNS3 PMU driver
+===============
+
+The HNS3 PMU driver registers a perf PMU with the name of its sicl id.::
+
+  /sys/devices/hns3_pmu_sicl_<sicl_id>
+
+PMU driver provides description of available events, filter modes, format,
+identifier and cpumask in sysfs.
+
+The "events" directory describes the event code of all supported events
+shown in perf list.
+
+The "filtermode" directory describes the supported filter modes of each
+event.
+
+The "format" directory describes all formats of the config (events) and
+config1 (filter options) fields of the perf_event_attr structure.
+
+The "identifier" file shows version of PMU hardware device.
+
+The "bdf_min" and "bdf_max" files show the supported bdf range of each
+pmu device.
+
+The "hw_clk_freq" file shows the hardware clock frequency of each pmu
+device.
+
+Example usage of checking event code and subevent code::
+
+  $# cat /sys/devices/hns3_pmu_sicl_0/events/dly_tx_normal_to_mac_time
+  config=0x00204
+  $# cat /sys/devices/hns3_pmu_sicl_0/events/dly_tx_normal_to_mac_packet_num
+  config=0x10204
+
+Each performance statistic has a pair of events to get two values to
+calculate real performance data in userspace.
+
+The bits 0~15 of config (here 0x0204) are the true hardware event code. If
+two events have same value of bits 0~15 of config, that means they are
+event pair. And the bit 16 of config indicates getting counter 0 or
+counter 1 of hardware event.
+
+After getting two values of event pair in usersapce, the formula of
+computation to calculate real performance data is:::
+
+  counter 0 / counter 1
+
+Example usage of checking supported filter mode::
+
+  $# cat /sys/devices/hns3_pmu_sicl_0/filtermode/bw_ssu_rpu_byte_num
+  filter mode supported: global/port/port-tc/func/func-queue/
+
+Example usage of perf::
+
+  $# perf list
+  hns3_pmu_sicl_0/bw_ssu_rpu_byte_num/ [kernel PMU event]
+  hns3_pmu_sicl_0/bw_ssu_rpu_time/     [kernel PMU event]
+  ------------------------------------------
+
+  $# perf stat -g -e hns3_pmu_sicl_0/bw_ssu_rpu_byte_num,global=1/ -e hns3_pmu_sicl_0/bw_ssu_rpu_time,global=1/ -I 1000
+  or
+  $# perf stat -g -e hns3_pmu_sicl_0/config=0x00002,global=1/ -e hns3_pmu_sicl_0/config=0x10002,global=1/ -I 1000
+
+
+Filter modes
+--------------
+
+1. global mode
+PMU collect performance statistics for all HNS3 PCIe functions of IO DIE.
+Set the "global" filter option to 1 will enable this mode.
+Example usage of perf::
+
+  $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,global=1/ -I 1000
+
+2. port mode
+PMU collect performance statistic of one whole physical port. The port id
+is same as mac id. The "tc" filter option must be set to 0xF in this mode,
+here tc stands for traffic class.
+
+Example usage of perf::
+
+  $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,port=0,tc=0xF/ -I 1000
+
+3. port-tc mode
+PMU collect performance statistic of one tc of physical port. The port id
+is same as mac id. The "tc" filter option must be set to 0 ~ 7 in this
+mode.
+Example usage of perf::
+
+  $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,port=0,tc=0/ -I 1000
+
+4. func mode
+PMU collect performance statistic of one PF/VF. The function id is BDF of
+PF/VF, its conversion formula::
+
+  func = (bus << 8) + (device << 3) + (function)
+
+for example:
+  BDF         func
+  35:00.0    0x3500
+  35:00.1    0x3501
+  35:01.0    0x3508
+
+In this mode, the "queue" filter option must be set to 0xFFFF.
+Example usage of perf::
+
+  $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,bdf=0x3500,queue=0xFFFF/ -I 1000
+
+5. func-queue mode
+PMU collect performance statistic of one queue of PF/VF. The function id
+is BDF of PF/VF, the "queue" filter option must be set to the exact queue
+id of function.
+Example usage of perf::
+
+  $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,bdf=0x3500,queue=0/ -I 1000
+
+6. func-intr mode
+PMU collect performance statistic of one interrupt of PF/VF. The function
+id is BDF of PF/VF, the "intr" filter option must be set to the exact
+interrupt id of function.
+Example usage of perf::
+
+  $# perf stat -a -e hns3_pmu_sicl_0/config=0x00301,bdf=0x3500,intr=0/ -I 1000

Documentation/admin-guide/perf/index.rst

@@ -9,6 +9,7 @@ Performance monitor support
 
    hisi-pmu
    hisi-pcie-pmu
+   hns3-pmu
    imx-ddr
    qcom_l2_pmu
    qcom_l3_pmu

Documentation/admin-guide/pm/cpuidle.rst

@@ -612,8 +612,8 @@ the ``menu`` governor to be used on the systems that use the ``ladder`` governor
 by default this way, for example.
 
 The other kernel command line parameters controlling CPU idle time management
-described below are only relevant for the *x86* architecture and some of
-them affect Intel processors only.
+described below are only relevant for the *x86* architecture and references
+to ``intel_idle`` affect Intel processors only.
 
 The *x86* architecture support code recognizes three kernel command line
 options related to CPU idle time management: ``idle=poll``, ``idle=halt``,
@@ -635,10 +635,13 @@ idle, so it very well may hurt single-thread computations performance as well as
 energy-efficiency.  Thus using it for performance reasons may not be a good idea
 at all.]
 
-The ``idle=nomwait`` option disables the ``intel_idle`` driver and causes
-``acpi_idle`` to be used (as long as all of the information needed by it is
-there in the system's ACPI tables), but it is not allowed to use the
-``MWAIT`` instruction of the CPUs to ask the hardware to enter idle states.
+The ``idle=nomwait`` option prevents the use of ``MWAIT`` instruction of
+the CPU to enter idle states. When this option is used, the ``acpi_idle``
+driver will use the ``HLT`` instruction instead of ``MWAIT``. On systems
+running Intel processors, this option disables the ``intel_idle`` driver
+and forces the use of the ``acpi_idle`` driver instead. Note that in either
+case, ``acpi_idle`` driver will function only if all the information needed
+by it is in the system's ACPI tables.
 
 In addition to the architecture-level kernel command line options affecting CPU
 idle time management, there are parameters affecting individual ``CPUIdle``

Documentation/admin-guide/sysctl/kernel.rst

@@ -38,8 +38,8 @@ acct
 
 If BSD-style process accounting is enabled these values control
 its behaviour. If free space on filesystem where the log lives
-goes below ``lowwater``% accounting suspends. If free space gets
-above ``highwater``% accounting resumes. ``frequency`` determines
+goes below ``lowwater``\ % accounting suspends. If free space gets
+above ``highwater``\ % accounting resumes. ``frequency`` determines
 how often do we check the amount of free space (value is in
 seconds). Default:
 

Documentation/admin-guide/tainted-kernels.rst

@@ -100,6 +100,7 @@ Bit  Log  Number  Reason that got the kernel tainted
  15  _/K   32768  kernel has been live patched
  16  _/X   65536  auxiliary taint, defined for and used by distros
  17  _/T  131072  kernel was built with the struct randomization plugin
+ 18  _/N  262144  an in-kernel test has been run
 ===  ===  ======  ========================================================
 
 Note: The character ``_`` is representing a blank in this table to make reading

Documentation/arm/google/chromebook-boot-flow.rst

@@ -0,0 +1,69 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+======================================
+Chromebook Boot Flow
+======================================
+
+Most recent Chromebooks that use device tree are using the opensource
+depthcharge_ bootloader. Depthcharge_ expects the OS to be packaged as a `FIT
+Image`_ which contains an OS image as well as a collection of device trees. It
+is up to depthcharge_ to pick the right device tree from the `FIT Image`_ and
+provide it to the OS.
+
+The scheme that depthcharge_ uses to pick the device tree takes into account
+three variables:
+
+- Board name, specified at depthcharge_ compile time. This is $(BOARD) below.
+- Board revision number, determined at runtime (perhaps by reading GPIO
+  strappings, perhaps via some other method). This is $(REV) below.
+- SKU number, read from GPIO strappings at boot time. This is $(SKU) below.
+
+For recent Chromebooks, depthcharge_ creates a match list that looks like this:
+
+- google,$(BOARD)-rev$(REV)-sku$(SKU)
+- google,$(BOARD)-rev$(REV)
+- google,$(BOARD)-sku$(SKU)
+- google,$(BOARD)
+
+Note that some older Chromebooks use a slightly different list that may
+not include SKU matching or may prioritize SKU/rev differently.
+
+Note that for some boards there may be extra board-specific logic to inject
+extra compatibles into the list, but this is uncommon.
+
+Depthcharge_ will look through all device trees in the `FIT Image`_ trying to
+find one that matches the most specific compatible. It will then look
+through all device trees in the `FIT Image`_ trying to find the one that
+matches the *second most* specific compatible, etc.
+
+When searching for a device tree, depthcharge_ doesn't care where the
+compatible string falls within a device tree's root compatible string array.
+As an example, if we're on board "lazor", rev 4, SKU 0 and we have two device
+trees:
+
+- "google,lazor-rev5-sku0", "google,lazor-rev4-sku0", "qcom,sc7180"
+- "google,lazor", "qcom,sc7180"
+
+Then depthcharge_ will pick the first device tree even though
+"google,lazor-rev4-sku0" was the second compatible listed in that device tree.
+This is because it is a more specific compatible than "google,lazor".
+
+It should be noted that depthcharge_ does not have any smarts to try to
+match board or SKU revisions that are "close by". That is to say that
+if depthcharge_ knows it's on "rev4" of a board but there is no "rev4"
+device tree then depthcharge_ *won't* look for a "rev3" device tree.
+
+In general when any significant changes are made to a board the board
+revision number is increased even if none of those changes need to
+be reflected in the device tree. Thus it's fairly common to see device
+trees with multiple revisions.
+
+It should be noted that, taking into account the above system that
+depthcharge_ has, the most flexibility is achieved if the device tree
+supporting the newest revision(s) of a board omits the "-rev{REV}"
+compatible strings. When this is done then if you get a new board
+revision and try to run old software on it then we'll at pick the
+newest device tree we know about.
+
+.. _depthcharge: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/depthcharge/
+.. _`FIT Image`: https://doc.coreboot.org/lib/payloads/fit.html

Documentation/arm/index.rst

@@ -31,6 +31,8 @@ SoC-specific documents
 .. toctree::
    :maxdepth: 1
 
+   google/chromebook-boot-flow
+
    ixp4xx
 
    marvell

Documentation/arm64/elf_hwcaps.rst

@@ -171,96 +171,73 @@ HWCAP_PACG
     Documentation/arm64/pointer-authentication.rst.
 
 HWCAP2_DCPODP
-
     Functionality implied by ID_AA64ISAR1_EL1.DPB == 0b0010.
 
 HWCAP2_SVE2
-
     Functionality implied by ID_AA64ZFR0_EL1.SVEVer == 0b0001.
 
 HWCAP2_SVEAES
-
     Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0001.
 
 HWCAP2_SVEPMULL
-
     Functionality implied by ID_AA64ZFR0_EL1.AES == 0b0010.
 
 HWCAP2_SVEBITPERM
-
     Functionality implied by ID_AA64ZFR0_EL1.BitPerm == 0b0001.
 
 HWCAP2_SVESHA3
-
     Functionality implied by ID_AA64ZFR0_EL1.SHA3 == 0b0001.
 
 HWCAP2_SVESM4
-
     Functionality implied by ID_AA64ZFR0_EL1.SM4 == 0b0001.
 
 HWCAP2_FLAGM2
-
     Functionality implied by ID_AA64ISAR0_EL1.TS == 0b0010.
 
 HWCAP2_FRINT
-
     Functionality implied by ID_AA64ISAR1_EL1.FRINTTS == 0b0001.
 
 HWCAP2_SVEI8MM
-
     Functionality implied by ID_AA64ZFR0_EL1.I8MM == 0b0001.
 
 HWCAP2_SVEF32MM
-
     Functionality implied by ID_AA64ZFR0_EL1.F32MM == 0b0001.
 
 HWCAP2_SVEF64MM
-
     Functionality implied by ID_AA64ZFR0_EL1.F64MM == 0b0001.
 
 HWCAP2_SVEBF16
-
     Functionality implied by ID_AA64ZFR0_EL1.BF16 == 0b0001.
 
 HWCAP2_I8MM
-
     Functionality implied by ID_AA64ISAR1_EL1.I8MM == 0b0001.
 
 HWCAP2_BF16
-
     Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0001.
 
 HWCAP2_DGH
-
     Functionality implied by ID_AA64ISAR1_EL1.DGH == 0b0001.
 
 HWCAP2_RNG
-
     Functionality implied by ID_AA64ISAR0_EL1.RNDR == 0b0001.
 
 HWCAP2_BTI
-
     Functionality implied by ID_AA64PFR0_EL1.BT == 0b0001.
 
 HWCAP2_MTE
-
     Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0010, as described
     by Documentation/arm64/memory-tagging-extension.rst.
 
 HWCAP2_ECV
-
     Functionality implied by ID_AA64MMFR0_EL1.ECV == 0b0001.
 
 HWCAP2_AFP
-
     Functionality implied by ID_AA64MFR1_EL1.AFP == 0b0001.
 
 HWCAP2_RPRES
-
     Functionality implied by ID_AA64ISAR2_EL1.RPRES == 0b0001.
 
 HWCAP2_MTE3
-
     Functionality implied by ID_AA64PFR1_EL1.MTE == 0b0011, as described
     by Documentation/arm64/memory-tagging-extension.rst.
 
@@ -301,6 +278,10 @@ HWCAP2_WFXT
 
     Functionality implied by ID_AA64ISAR2_EL1.WFXT == 0b0010.
 
+HWCAP2_EBF16
+
+    Functionality implied by ID_AA64ISAR1_EL1.BF16 == 0b0010.
+
 4. Unused AT_HWCAP bits
 -----------------------
 

Documentation/arm64/memory.rst

@@ -33,9 +33,8 @@ AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
   0000000000000000	0000ffffffffffff	 256TB		user
   ffff000000000000	ffff7fffffffffff	 128TB		kernel logical memory map
  [ffff600000000000	ffff7fffffffffff]	  32TB		[kasan shadow region]
-  ffff800000000000	ffff800007ffffff	 128MB		bpf jit region
-  ffff800008000000	ffff80000fffffff	 128MB		modules
-  ffff800010000000	fffffbffefffffff	 124TB		vmalloc
+  ffff800000000000	ffff800007ffffff	 128MB		modules
+  ffff800008000000	fffffbffefffffff	 124TB		vmalloc
   fffffbfff0000000	fffffbfffdffffff	 224MB		fixed mappings (top down)
   fffffbfffe000000	fffffbfffe7fffff	   8MB		[guard region]
   fffffbfffe800000	fffffbffff7fffff	  16MB		PCI I/O space
@@ -51,9 +50,8 @@ AArch64 Linux memory layout with 64KB pages + 3 levels (52-bit with HW support):
   0000000000000000	000fffffffffffff	   4PB		user
   fff0000000000000	ffff7fffffffffff	  ~4PB		kernel logical memory map
  [fffd800000000000	ffff7fffffffffff]	 512TB		[kasan shadow region]
-  ffff800000000000	ffff800007ffffff	 128MB		bpf jit region
-  ffff800008000000	ffff80000fffffff	 128MB		modules
-  ffff800010000000	fffffbffefffffff	 124TB		vmalloc
+  ffff800000000000	ffff800007ffffff	 128MB		modules
+  ffff800008000000	fffffbffefffffff	 124TB		vmalloc
   fffffbfff0000000	fffffbfffdffffff	 224MB		fixed mappings (top down)
   fffffbfffe000000	fffffbfffe7fffff	   8MB		[guard region]
   fffffbfffe800000	fffffbffff7fffff	  16MB		PCI I/O space

Documentation/arm64/silicon-errata.rst

@@ -82,10 +82,14 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A57      | #1319537        | ARM64_ERRATUM_1319367       |
 +----------------+-----------------+-----------------+-----------------------------+
+| ARM            | Cortex-A57      | #1742098        | ARM64_ERRATUM_1742098       |
++----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A72      | #853709         | N/A                         |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A72      | #1319367        | ARM64_ERRATUM_1319367       |
 +----------------+-----------------+-----------------+-----------------------------+
+| ARM            | Cortex-A72      | #1655431        | ARM64_ERRATUM_1742098       |
++----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A73      | #858921         | ARM64_ERRATUM_858921        |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A76      | #1188873,1418040| ARM64_ERRATUM_1418040       |
@@ -102,6 +106,8 @@ stable kernels.
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A510     | #2077057        | ARM64_ERRATUM_2077057       |
 +----------------+-----------------+-----------------+-----------------------------+
+| ARM            | Cortex-A510     | #2441009        | ARM64_ERRATUM_2441009       |
++----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A710     | #2119858        | ARM64_ERRATUM_2119858       |
 +----------------+-----------------+-----------------+-----------------------------+
 | ARM            | Cortex-A710     | #2054223        | ARM64_ERRATUM_2054223       |

Documentation/core-api/idr.rst

@@ -17,6 +17,9 @@ solution to the problem to avoid everybody inventing their own.  The IDR
 provides the ability to map an ID to a pointer, while the IDA provides
 only ID allocation, and as a result is much more memory-efficient.
 
+The IDR interface is deprecated; please use the :doc:`XArray <xarray>`
+instead.
+
 IDR usage
 =========
 

Documentation/core-api/protection-keys.rst

@@ -4,31 +4,29 @@
 Memory Protection Keys
 ======================
 
-Memory Protection Keys for Userspace (PKU aka PKEYs) is a feature
-which is found on Intel's Skylake (and later) "Scalable Processor"
-Server CPUs. It will be available in future non-server Intel parts
-and future AMD processors.
+Memory Protection Keys provide a mechanism for enforcing page-based
+protections, but without requiring modification of the page tables when an
+application changes protection domains.
 
-For anyone wishing to test or use this feature, it is available in
-Amazon's EC2 C5 instances and is known to work there using an Ubuntu
-17.04 image.
+Pkeys Userspace (PKU) is a feature which can be found on:
+        * Intel server CPUs, Skylake and later
+        * Intel client CPUs, Tiger Lake (11th Gen Core) and later
+        * Future AMD CPUs
 
-Memory Protection Keys provides a mechanism for enforcing page-based
-protections, but without requiring modification of the page tables
-when an application changes protection domains.  It works by
-dedicating 4 previously ignored bits in each page table entry to a
-"protection key", giving 16 possible keys.
+Pkeys work by dedicating 4 previously Reserved bits in each page table entry to
+a "protection key", giving 16 possible keys.
 
-There is also a new user-accessible register (PKRU) with two separate
-bits (Access Disable and Write Disable) for each key.  Being a CPU
-register, PKRU is inherently thread-local, potentially giving each
+Protections for each key are defined with a per-CPU user-accessible register
+(PKRU).  Each of these is a 32-bit register storing two bits (Access Disable
+and Write Disable) for each of 16 keys.
+
+Being a CPU register, PKRU is inherently thread-local, potentially giving each
 thread a different set of protections from every other thread.
 
-There are two new instructions (RDPKRU/WRPKRU) for reading and writing
-to the new register.  The feature is only available in 64-bit mode,
-even though there is theoretically space in the PAE PTEs.  These
-permissions are enforced on data access only and have no effect on
-instruction fetches.
+There are two instructions (RDPKRU/WRPKRU) for reading and writing to the
+register.  The feature is only available in 64-bit mode, even though there is
+theoretically space in the PAE PTEs.  These permissions are enforced on data
+access only and have no effect on instruction fetches.
 
 Syscalls
 ========

Documentation/dev-tools/coccinelle.rst

@@ -66,7 +66,7 @@ The wiki documentation always refers to the linux-next version of the script.
 
 For Semantic Patch Language(SmPL) grammar documentation refer to:
 
-http://coccinelle.lip6.fr/documentation.php
+https://coccinelle.gitlabpages.inria.fr/website/docs/main_grammar.html
 
 Using Coccinelle on the Linux kernel
 ------------------------------------

Documentation/dev-tools/kselftest.rst

@@ -208,6 +208,14 @@ In general, the rules for selftests are
 Contributing new tests (details)
 ================================
 
+ * In your Makefile, use facilities from lib.mk by including it instead of
+   reinventing the wheel. Specify flags and binaries generation flags on
+   need basis before including lib.mk. ::
+
+    CFLAGS = $(KHDR_INCLUDES)
+    TEST_GEN_PROGS := close_range_test
+    include ../lib.mk
+
  * Use TEST_GEN_XXX if such binaries or files are generated during
    compiling.
 
@@ -230,13 +238,30 @@ Contributing new tests (details)
  * First use the headers inside the kernel source and/or git repo, and then the
    system headers.  Headers for the kernel release as opposed to headers
    installed by the distro on the system should be the primary focus to be able
-   to find regressions.
+   to find regressions. Use KHDR_INCLUDES in Makefile to include headers from
+   the kernel source.
 
  * If a test needs specific kernel config options enabled, add a config file in
    the test directory to enable them.
 
    e.g: tools/testing/selftests/android/config
 
+ * Create a .gitignore file inside test directory and add all generated objects
+   in it.
+
+ * Add new test name in TARGETS in selftests/Makefile::
+
+    TARGETS += android
+
+ * All changes should pass::
+
+    kselftest-{all,install,clean,gen_tar}
+    kselftest-{all,install,clean,gen_tar} O=abo_path
+    kselftest-{all,install,clean,gen_tar} O=rel_path
+    make -C tools/testing/selftests {all,install,clean,gen_tar}
+    make -C tools/testing/selftests {all,install,clean,gen_tar} O=abs_path
+    make -C tools/testing/selftests {all,install,clean,gen_tar} O=rel_path
+
 Test Module
 ===========
 
@@ -250,6 +275,14 @@ assist writing kernel modules that are for use with kselftest:
 - ``tools/testing/selftests/kselftest_module.h``
 - ``tools/testing/selftests/kselftest/module.sh``
 
+Note that test modules should taint the kernel with TAINT_TEST. This will
+happen automatically for modules which are in the ``tools/testing/``
+directory, or for modules which use the ``kselftest_module.h`` header above.
+Otherwise, you'll need to add ``MODULE_INFO(test, "Y")`` to your module
+source. selftests which do not load modules typically should not taint the
+kernel, but in cases where a non-test module is loaded, TEST_TAINT can be
+applied from userspace by writing to ``/proc/sys/kernel/tainted``.
+
 How to use
 ----------
 
@@ -308,6 +341,7 @@ A bare bones test module might look like this:
    KSTM_MODULE_LOADERS(test_foo);
    MODULE_AUTHOR("John Developer <jd@fooman.org>");
    MODULE_LICENSE("GPL");
+   MODULE_INFO(test, "Y");
 
 Example test script
 -------------------

Documentation/dev-tools/kunit/run_wrapper.rst

@@ -192,6 +192,21 @@ via UML. To run tests on qemu, by default it requires two flags:
     if we have downloaded the microblaze toolchain from the 0-day
     website to a directory in our home directory called toolchains.
 
+This means that for most architectures, running under qemu is as simple as:
+
+.. code-block:: bash
+
+	./tools/testing/kunit/kunit.py run --arch=x86_64
+
+When cross-compiling, we'll likely need to specify a different toolchain, for
+example:
+
+.. code-block:: bash
+
+	./tools/testing/kunit/kunit.py run \
+		--arch=s390 \
+		--cross_compile=s390x-linux-gnu-
+
 If we want to run KUnit tests on an architecture not supported by
 the ``--arch`` flag, or want to run KUnit tests on qemu using a
 non-default configuration; then we can write our own``QemuConfig``.
@@ -214,14 +229,11 @@ as
 		--jobs=12 \
 		--qemu_config=./tools/testing/kunit/qemu_configs/x86_64.py
 
-To run existing KUnit tests on non-UML architectures, see:
-Documentation/dev-tools/kunit/non_uml.rst.
-
 Command-Line Arguments
 ======================
 
 kunit_tool has a number of other command-line arguments which can
-be useful for our test environment. Below the most commonly used
+be useful for our test environment. Below are the most commonly used
 command line arguments:
 
 - ``--help``: Lists all available options. To list common options,
@@ -245,3 +257,64 @@ command line arguments:
             added or modified. Instead, enable all tests
             which have satisfied dependencies by adding
             ``CONFIG_KUNIT_ALL_TESTS=y`` to your ``.kunitconfig``.
+
+- ``--kunitconfig``: Specifies the path or the directory of the ``.kunitconfig``
+  file. For example:
+
+  - ``lib/kunit/.kunitconfig`` can be the path of the file.
+
+  - ``lib/kunit`` can be the directory in which the file is located.
+
+  This file is used to build and run with a predefined set of tests
+  and their dependencies. For example, to run tests for a given subsystem.
+
+- ``--kconfig_add``: Specifies additional configuration options to be
+  appended to the ``.kunitconfig`` file. For example:
+
+  .. code-block::
+
+	./tools/testing/kunit/kunit.py run --kconfig_add CONFIG_KASAN=y
+
+- ``--arch``: Runs tests on the specified architecture. The architecture
+  argument is same as the Kbuild ARCH environment variable.
+  For example, i386, x86_64, arm, um, etc. Non-UML architectures run on qemu.
+  Default is `um`.
+
+- ``--cross_compile``: Specifies the Kbuild toolchain. It passes the
+  same argument as passed to the ``CROSS_COMPILE`` variable used by
+  Kbuild. This will be the prefix for the toolchain
+  binaries such as GCC. For example:
+
+  - ``sparc64-linux-gnu-`` if we have the sparc toolchain installed on
+    our system.
+
+  - ``$HOME/toolchains/microblaze/gcc-9.2.0-nolibc/microblaze-linux/bin/microblaze-linux``
+    if we have downloaded the microblaze toolchain from the 0-day
+    website to a specified path in our home directory called toolchains.
+
+- ``--qemu_config``: Specifies the path to a file containing a
+  custom qemu architecture definition. This should be a python file
+  containing a `QemuArchParams` object.
+
+- ``--qemu_args``: Specifies additional qemu arguments, for example, ``-smp 8``.
+
+- ``--jobs``: Specifies the number of jobs (commands) to run simultaneously.
+  By default, this is set to the number of cores on your system.
+
+- ``--timeout``: Specifies the maximum number of seconds allowed for all tests to run.
+  This does not include the time taken to build the tests.
+
+- ``--kernel_args``: Specifies additional kernel command-line arguments. May be repeated.
+
+- ``--run_isolated``: If set, boots the kernel for each individual suite/test.
+  This is useful for debugging a non-hermetic test, one that
+  might pass/fail based on what ran before it.
+
+- ``--raw_output``: If set, generates unformatted output from kernel. Possible options are:
+
+   - ``all``: To view the full kernel output, use ``--raw_output=all``.
+
+   - ``kunit``: This is the default option and filters to KUnit output. Use ``--raw_output`` or ``--raw_output=kunit``.
+
+- ``--json``: If set, stores the test results in a JSON format and prints to `stdout` or
+  saves to a file if a filename is specified.

Documentation/dev-tools/kunit/running_tips.rst

@@ -15,7 +15,7 @@ It can be handy to create a bash function like:
 .. code-block:: bash
 
 	function run_kunit() {
-	  ( cd "$(git rev-parse --show-toplevel)" && ./tools/testing/kunit/kunit.py run $@ )
+	  ( cd "$(git rev-parse --show-toplevel)" && ./tools/testing/kunit/kunit.py run "$@" )
 	}
 
 .. note::
@@ -123,8 +123,7 @@ Putting it together into a copy-pastable sequence of commands:
 .. code-block:: bash
 
 	# Append coverage options to the current config
-	$ echo -e "CONFIG_DEBUG_KERNEL=y\nCONFIG_DEBUG_INFO=y\nCONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y\nCONFIG_GCOV=y" >> .kunit/.kunitconfig
-	$ ./tools/testing/kunit/kunit.py run
+	$ ./tools/testing/kunit/kunit.py run --kunitconfig=.kunit/ --kunitconfig=tools/testing/kunit/configs/coverage_uml.config
 	# Extract the coverage information from the build dir (.kunit/)
 	$ lcov -t "my_kunit_tests" -o coverage.info -c -d .kunit/
 

Documentation/dev-tools/kunit/usage.rst

@@ -505,7 +505,7 @@ By reusing the same ``cases`` array from above, we can write the test as a
 		const char *str;
 		const char *sha1;
 	};
-	struct sha1_test_case cases[] = {
+	const struct sha1_test_case cases[] = {
 		{
 			.str = "hello world",
 			.sha1 = "2aae6c35c94fcfb415dbe95f408b9ce91ee846ed",

Documentation/devicetree/bindings/arm/altera.yaml

@@ -25,7 +25,14 @@ properties:
         items:
           - enum:
               - altr,socfpga-arria10-socdk
-              - enclustra,mercury-aa1
+          - const: altr,socfpga-arria10
+          - const: altr,socfpga
+
+      - description: Mercury+ AA1 boards
+        items:
+          - enum:
+              - google,chameleon-v3
+          - const: enclustra,mercury-aa1
           - const: altr,socfpga-arria10
           - const: altr,socfpga
 
@@ -47,6 +54,7 @@ properties:
         items:
           - enum:
               - altr,socfpga-stratix10-socdk
+              - altr,socfpga-stratix10-swvp
           - const: altr,socfpga-stratix10
 
       - description: SoCFPGA VT

Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml

@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/aspeed/aspeed.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aspeed SoC based boards
+
+maintainers:
+  - Joel Stanley <joel@jms.id.au>
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: AST2400 based boards
+        items:
+          - enum:
+              - facebook,galaxy100-bmc
+              - facebook,wedge100-bmc
+              - facebook,wedge40-bmc
+              - microsoft,olympus-bmc
+              - quanta,q71l-bmc
+              - tyan,palmetto-bmc
+              - yadro,vesnin-bmc
+          - const: aspeed,ast2400
+
+      - description: AST2500 based boards
+        items:
+          - enum:
+              - amd,ethanolx-bmc
+              - ampere,mtjade-bmc
+              - aspeed,ast2500-evb
+              - asrock,e3c246d4i-bmc
+              - asrock,romed8hm3-bmc
+              - bytedance,g220a-bmc
+              - facebook,cmm-bmc
+              - facebook,minipack-bmc
+              - facebook,tiogapass-bmc
+              - facebook,yamp-bmc
+              - facebook,yosemitev2-bmc
+              - facebook,wedge400-bmc
+              - hxt,stardragon4800-rep2-bmc
+              - ibm,mihawk-bmc
+              - ibm,mowgli-bmc
+              - ibm,romulus-bmc
+              - ibm,swift-bmc
+              - ibm,witherspoon-bmc
+              - ingrasys,zaius-bmc
+              - inspur,fp5280g2-bmc
+              - inspur,nf5280m6-bmc
+              - inspur,on5263m5-bmc
+              - intel,s2600wf-bmc
+              - inventec,lanyang-bmc
+              - lenovo,hr630-bmc
+              - lenovo,hr855xg2-bmc
+              - portwell,neptune-bmc
+              - qcom,centriq2400-rep-bmc
+              - supermicro,x11spi-bmc
+              - tyan,s7106-bmc
+              - tyan,s8036-bmc
+              - yadro,nicole-bmc
+              - yadro,vegman-n110-bmc
+              - yadro,vegman-rx20-bmc
+              - yadro,vegman-sx20-bmc
+          - const: aspeed,ast2500
+
+      - description: AST2600 based boards
+        items:
+          - enum:
+              - aspeed,ast2600-evb
+              - aspeed,ast2600-evb-a1
+              - facebook,bletchley-bmc
+              - facebook,cloudripper-bmc
+              - facebook,elbert-bmc
+              - facebook,fuji-bmc
+              - ibm,everest-bmc
+              - ibm,rainier-bmc
+              - ibm,tacoma-bmc
+              - inventec,transformer-bmc
+              - jabil,rbp-bmc
+              - nuvia,dc-scm-bmc
+              - quanta,s6q-bmc
+          - const: aspeed,ast2600
+
+additionalProperties: true

Documentation/devicetree/bindings/arm/atmel-at91.yaml

@@ -163,9 +163,11 @@ properties:
           - const: microchip,sama7g5
           - const: microchip,sama7
 
-      - description: Microchip LAN9662 PCB8291 Evaluation Board.
+      - description: Microchip LAN9662 Evaluation Boards.
         items:
-          - const: microchip,lan9662-pcb8291
+          - enum:
+              - microchip,lan9662-pcb8291
+              - microchip,lan9662-pcb8309
           - const: microchip,lan9662
           - const: microchip,lan966
 

Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml

@@ -87,6 +87,13 @@ properties:
           - const: brcm,bcm53012
           - const: brcm,bcm4708
 
+      - description: BCM53015 based boards
+        items:
+          - enum:
+              - meraki,mr26
+          - const: brcm,bcm53015
+          - const: brcm,bcm4708
+
       - description: BCM53016 based boards
         items:
           - enum:

Documentation/devicetree/bindings/arm/bcm/brcm,bcmbca.yaml

@@ -28,6 +28,99 @@ properties:
           - const: brcm,bcm47622
           - const: brcm,bcmbca
 
+      - description: BCM4912 based boards
+        items:
+          - enum:
+              - asus,gt-ax6000
+              - brcm,bcm94912
+          - const: brcm,bcm4912
+          - const: brcm,bcmbca
+
+      - description: BCM63138 based boards
+        items:
+          - enum:
+              - brcm,bcm963138
+              - brcm,BCM963138DVT
+          - const: brcm,bcm63138
+          - const: brcm,bcmbca
+
+      - description: BCM63146 based boards
+        items:
+          - enum:
+              - brcm,bcm963146
+          - const: brcm,bcm63146
+          - const: brcm,bcmbca
+
+      - description: BCM63148 based boards
+        items:
+          - enum:
+              - brcm,bcm963148
+          - const: brcm,bcm63148
+          - const: brcm,bcmbca
+
+      - description: BCM63158 based boards
+        items:
+          - enum:
+              - brcm,bcm963158
+          - const: brcm,bcm63158
+          - const: brcm,bcmbca
+
+      - description: BCM63178 based boards
+        items:
+          - enum:
+              - brcm,bcm963178
+          - const: brcm,bcm63178
+          - const: brcm,bcmbca
+
+      - description: BCM6756 based boards
+        items:
+          - enum:
+              - brcm,bcm96756
+          - const: brcm,bcm6756
+          - const: brcm,bcmbca
+
+      - description: BCM6813 based boards
+        items:
+          - enum:
+              - brcm,bcm96813
+          - const: brcm,bcm6813
+          - const: brcm,bcmbca
+
+      - description: BCM6846 based boards
+        items:
+          - enum:
+              - brcm,bcm96846
+          - const: brcm,bcm6846
+          - const: brcm,bcmbca
+
+      - description: BCM6855 based boards
+        items:
+          - enum:
+              - brcm,bcm96855
+          - const: brcm,bcm6855
+          - const: brcm,bcmbca
+
+      - description: BCM6856 based boards
+        items:
+          - enum:
+              - brcm,bcm96856
+          - const: brcm,bcm6856
+          - const: brcm,bcmbca
+
+      - description: BCM6858 based boards
+        items:
+          - enum:
+              - brcm,bcm96858
+          - const: brcm,bcm6858
+          - const: brcm,bcmbca
+
+      - description: BCM6878 based boards
+        items:
+          - enum:
+              - brcm,bcm96878
+          - const: brcm,bcm6878
+          - const: brcm,bcmbca
+
 additionalProperties: true
 
 ...

Documentation/devicetree/bindings/arm/cpus.yaml

@@ -221,6 +221,7 @@ properties:
           - qcom,kpss-acc-v1
           - qcom,kpss-acc-v2
           - qcom,msm8226-smp
+          - qcom,msm8909-smp
           # Only valid on ARM 32-bit, see above for ARM v8 64-bit
           - qcom,msm8916-smp
           - renesas,apmu

Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt

@@ -1,271 +0,0 @@
-NXP i.MX System Controller Firmware (SCFW)
---------------------------------------------------------------------
-
-The System Controller Firmware (SCFW) is a low-level system function
-which runs on a dedicated Cortex-M core to provide power, clock, and
-resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
-(QM, QP), and i.MX8QX (QXP, DX).
-
-The AP communicates with the SC using a multi-ported MU module found
-in the LSIO subsystem. The current definition of this MU module provides
-5 remote AP connections to the SC to support up to 5 execution environments
-(TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
-with the LSIO DSC IP bus. The SC firmware will communicate with this MU
-using the MSI bus.
-
-System Controller Device Node:
-============================================================
-
-The scu node with the following properties shall be under the /firmware/ node.
-
-Required properties:
--------------------
-- compatible:	should be "fsl,imx-scu".
-- mbox-names:	should include "tx0", "tx1", "tx2", "tx3",
-			       "rx0", "rx1", "rx2", "rx3";
-		include "gip3" if want to support general MU interrupt.
-- mboxes:	List of phandle of 4 MU channels for tx, 4 MU channels for
-		rx, and 1 optional MU channel for general interrupt.
-		All MU channels must be in the same MU instance.
-		Cross instances are not allowed. The MU instance can only
-		be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users need
-		to make sure use the one which is not conflict with other
-		execution environments. e.g. ATF.
-		Note:
-		Channel 0 must be "tx0" or "rx0".
-		Channel 1 must be "tx1" or "rx1".
-		Channel 2 must be "tx2" or "rx2".
-		Channel 3 must be "tx3" or "rx3".
-		General interrupt rx channel must be "gip3".
-		e.g.
-		mboxes = <&lsio_mu1 0 0
-			  &lsio_mu1 0 1
-			  &lsio_mu1 0 2
-			  &lsio_mu1 0 3
-			  &lsio_mu1 1 0
-			  &lsio_mu1 1 1
-			  &lsio_mu1 1 2
-			  &lsio_mu1 1 3
-			  &lsio_mu1 3 3>;
-		See Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
-		for detailed mailbox binding.
-
-Note: Each mu which supports general interrupt should have an alias correctly
-numbered in "aliases" node.
-e.g.
-aliases {
-	mu1 = &lsio_mu1;
-};
-
-i.MX SCU Client Device Node:
-============================================================
-
-Client nodes are maintained as children of the relevant IMX-SCU device node.
-
-Power domain bindings based on SCU Message Protocol
-------------------------------------------------------------
-
-This binding for the SCU power domain providers uses the generic power
-domain binding[2].
-
-Required properties:
-- compatible:		Should be one of:
-			  "fsl,imx8qm-scu-pd",
-			  "fsl,imx8qxp-scu-pd"
-			followed by "fsl,scu-pd"
-
-- #power-domain-cells:	Must be 1. Contains the Resource ID used by
-			SCU commands.
-			See detailed Resource ID list from:
-			include/dt-bindings/firmware/imx/rsrc.h
-
-Clock bindings based on SCU Message Protocol
-------------------------------------------------------------
-
-This binding uses the common clock binding[1].
-
-Required properties:
-- compatible:		Should be one of:
-			  "fsl,imx8dxl-clk"
-			  "fsl,imx8qm-clk"
-			  "fsl,imx8qxp-clk"
-			followed by "fsl,scu-clk"
-- #clock-cells:		Should be 2.
-			Contains the Resource and Clock ID value.
-- clocks:		List of clock specifiers, must contain an entry for
-			each required entry in clock-names
-- clock-names:		Should include entries "xtal_32KHz", "xtal_24MHz"
-
-The clock consumer should specify the desired clock by having the clock
-ID in its "clocks" phandle cell.
-
-See the full list of clock IDs from:
-include/dt-bindings/clock/imx8qxp-clock.h
-
-Pinctrl bindings based on SCU Message Protocol
-------------------------------------------------------------
-
-This binding uses the i.MX common pinctrl binding[3].
-
-Required properties:
-- compatible:		Should be one of:
-			"fsl,imx8qm-iomuxc",
-			"fsl,imx8qxp-iomuxc",
-			"fsl,imx8dxl-iomuxc".
-
-Required properties for Pinctrl sub nodes:
-- fsl,pins:		Each entry consists of 3 integers which represents
-			the mux and config setting for one pin. The first 2
-			integers <pin_id mux_mode> are specified using a
-			PIN_FUNC_ID macro, which can be found in
-			<dt-bindings/pinctrl/pads-imx8qm.h>,
-			<dt-bindings/pinctrl/pads-imx8qxp.h>,
-			<dt-bindings/pinctrl/pads-imx8dxl.h>.
-			The last integer CONFIG is the pad setting value like
-			pull-up on this pin.
-
-			Please refer to i.MX8QXP Reference Manual for detailed
-			CONFIG settings.
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/power/power-domain.yaml
-[3] Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
-
-RTC bindings based on SCU Message Protocol
-------------------------------------------------------------
-
-Required properties:
-- compatible: should be "fsl,imx8qxp-sc-rtc";
-
-OCOTP bindings based on SCU Message Protocol
-------------------------------------------------------------
-Required properties:
-- compatible:		Should be one of:
-			"fsl,imx8qm-scu-ocotp",
-			"fsl,imx8qxp-scu-ocotp".
-- #address-cells:	Must be 1. Contains byte index
-- #size-cells:		Must be 1. Contains byte length
-
-Optional Child nodes:
-
-- Data cells of ocotp:
-  Detailed bindings are described in bindings/nvmem/nvmem.txt
-
-Watchdog bindings based on SCU Message Protocol
-------------------------------------------------------------
-
-Required properties:
-- compatible: should be:
-              "fsl,imx8qxp-sc-wdt"
-              followed by "fsl,imx-sc-wdt";
-Optional properties:
-- timeout-sec: contains the watchdog timeout in seconds.
-
-SCU key bindings based on SCU Message Protocol
-------------------------------------------------------------
-
-Required properties:
-- compatible: should be:
-              "fsl,imx8qxp-sc-key"
-              followed by "fsl,imx-sc-key";
-- linux,keycodes: See Documentation/devicetree/bindings/input/input.yaml
-
-Thermal bindings based on SCU Message Protocol
-------------------------------------------------------------
-
-Required properties:
-- compatible:			Should be :
-				  "fsl,imx8qxp-sc-thermal"
-				followed by "fsl,imx-sc-thermal";
-
-- #thermal-sensor-cells:	See Documentation/devicetree/bindings/thermal/thermal-sensor.yaml
-				for a description.
-
-Example (imx8qxp):
--------------
-aliases {
-	mu1 = &lsio_mu1;
-};
-
-lsio_mu1: mailbox@5d1c0000 {
-	...
-	#mbox-cells = <2>;
-};
-
-firmware {
-	scu {
-		compatible = "fsl,imx-scu";
-		mbox-names = "tx0", "tx1", "tx2", "tx3",
-			     "rx0", "rx1", "rx2", "rx3",
-			     "gip3";
-		mboxes = <&lsio_mu1 0 0
-			  &lsio_mu1 0 1
-			  &lsio_mu1 0 2
-			  &lsio_mu1 0 3
-			  &lsio_mu1 1 0
-			  &lsio_mu1 1 1
-			  &lsio_mu1 1 2
-			  &lsio_mu1 1 3
-			  &lsio_mu1 3 3>;
-
-		clk: clk {
-			compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
-			#clock-cells = <2>;
-		};
-
-		iomuxc {
-			compatible = "fsl,imx8qxp-iomuxc";
-
-			pinctrl_lpuart0: lpuart0grp {
-				fsl,pins = <
-					SC_P_UART0_RX_ADMA_UART0_RX	0x06000020
-					SC_P_UART0_TX_ADMA_UART0_TX	0x06000020
-				>;
-			};
-			...
-		};
-
-		ocotp: imx8qx-ocotp {
-			compatible = "fsl,imx8qxp-scu-ocotp";
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			fec_mac0: mac@2c4 {
-				reg = <0x2c4 8>;
-			};
-		};
-
-		pd: imx8qx-pd {
-			compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
-			#power-domain-cells = <1>;
-		};
-
-		rtc: rtc {
-			compatible = "fsl,imx8qxp-sc-rtc";
-		};
-
-		scu_key: scu-key {
-			compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
-			linux,keycodes = <KEY_POWER>;
-		};
-
-		watchdog {
-			compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
-			timeout-sec = <60>;
-		};
-
-		tsens: thermal-sensor {
-			compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
-			#thermal-sensor-cells = <1>;
-		};
-	};
-};
-
-serial@5a060000 {
-	...
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lpuart0>;
-	clocks = <&uart0_clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
-	clock-names = "ipg";
-	power-domains = <&pd IMX_SC_R_UART_0>;
-};

Documentation/devicetree/bindings/arm/fsl.yaml

@@ -321,6 +321,7 @@ properties:
           - enum:
               - toradex,apalis_imx6q-ixora      # Apalis iMX6Q/D Module on Ixora Carrier Board
               - toradex,apalis_imx6q-ixora-v1.1 # Apalis iMX6Q/D Module on Ixora V1.1 Carrier Board
+              - toradex,apalis_imx6q-ixora-v1.2 # Apalis iMX6Q/D Module on Ixora V1.2 Carrier Board
               - toradex,apalis_imx6q-eval       # Apalis iMX6Q/D Module on Apalis Evaluation Board
           - const: toradex,apalis_imx6q
           - const: fsl,imx6q
@@ -670,30 +671,30 @@ properties:
       - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules
         items:
           - enum:
-              - toradex,colibri-imx6ull-aster     # Colibri iMX6ULL Module on Aster Carrier Board
-              - toradex,colibri-imx6ull-eval      # Colibri iMX6ULL Module on Colibri Evaluation Board V3
-              - toradex,colibri-imx6ull-iris      # Colibri iMX6ULL Module on Iris Carrier Board
-              - toradex,colibri-imx6ull-iris-v2   # Colibri iMX6ULL Module on Iris V2 Carrier Board
+              - toradex,colibri-imx6ull-aster     # Aster Carrier Board
+              - toradex,colibri-imx6ull-eval      # Colibri Evaluation Board V3
+              - toradex,colibri-imx6ull-iris      # Iris Carrier Board
+              - toradex,colibri-imx6ull-iris-v2   # Iris V2 Carrier Board
           - const: toradex,colibri-imx6ull        # Colibri iMX6ULL Module
           - const: fsl,imx6ull
 
       - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL 1GB (eMMC) Module
         items:
           - enum:
-              - toradex,colibri-imx6ull-emmc-aster     # Colibri iMX6ULL 1G (eMMC) on Aster Carrier Board
-              - toradex,colibri-imx6ull-emmc-eval      # Colibri iMX6ULL 1G (eMMC) on Colibri Evaluation B. V3
-              - toradex,colibri-imx6ull-emmc-iris      # Colibri iMX6ULL 1G (eMMC) on Iris Carrier Board
-              - toradex,colibri-imx6ull-emmc-iris-v2   # Colibri iMX6ULL 1G (eMMC) on Iris V2 Carrier Board
+              - toradex,colibri-imx6ull-emmc-aster     # Aster Carrier Board
+              - toradex,colibri-imx6ull-emmc-eval      # Colibri Evaluation B. V3
+              - toradex,colibri-imx6ull-emmc-iris      # Iris Carrier Board
+              - toradex,colibri-imx6ull-emmc-iris-v2   # Iris V2 Carrier Board
           - const: toradex,colibri-imx6ull-emmc        # Colibri iMX6ULL 1GB (eMMC) Module
           - const: fsl,imx6ull
 
       - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Wi-Fi / BT Modules
         items:
           - enum:
-              - toradex,colibri-imx6ull-wifi-eval     # Colibri iMX6ULL Wi-Fi / BT M. on Colibri Eval. B. V3
-              - toradex,colibri-imx6ull-wifi-aster    # Colibri iMX6ULL Wi-Fi / BT M. on Aster Carrier Board
-              - toradex,colibri-imx6ull-wifi-iris     # Colibri iMX6ULL Wi-Fi / BT M. on Iris Carrier Board
-              - toradex,colibri-imx6ull-wifi-iris-v2  # Colibri iMX6ULL Wi-Fi / BT M. on Iris V2 Carrier Board
+              - toradex,colibri-imx6ull-wifi-eval     # Colibri Eval. B. V3
+              - toradex,colibri-imx6ull-wifi-aster    # Aster Carrier Board
+              - toradex,colibri-imx6ull-wifi-iris     # Iris Carrier Board
+              - toradex,colibri-imx6ull-wifi-iris-v2  # Iris V2 Carrier Board
           - const: toradex,colibri-imx6ull-wifi       # Colibri iMX6ULL Wi-Fi / BT Module
           - const: fsl,imx6ull
 
@@ -738,6 +739,8 @@ properties:
           - enum:
               - toradex,colibri-imx7s-aster     # Module on Aster Carrier Board
               - toradex,colibri-imx7s-eval-v3   # Module on Colibri Evaluation Board V3
+              - toradex,colibri-imx7s-iris      # Module on Iris Carrier Board
+              - toradex,colibri-imx7s-iris-v2   # Module on Iris Carrier Board V2
           - const: toradex,colibri-imx7s
           - const: fsl,imx7s
 
@@ -789,8 +792,10 @@ properties:
       - description: i.MX7D Boards with Toradex Colibri i.MX7D Module
         items:
           - enum:
-              - toradex,colibri-imx7d-aster   # Colibri iMX7D Module on Aster Carrier Board
-              - toradex,colibri-imx7d-eval-v3 # Colibri iMX7D Module on Colibri Evaluation Board V3
+              - toradex,colibri-imx7d-aster   # Aster Carrier Board
+              - toradex,colibri-imx7d-eval-v3 # Colibri Evaluation Board V3
+              - toradex,colibri-imx7d-iris    # Iris Carrier Board
+              - toradex,colibri-imx7d-iris-v2 # Iris Carrier Board V2
           - const: toradex,colibri-imx7d
           - const: fsl,imx7d
 
@@ -799,6 +804,8 @@ properties:
           - enum:
               - toradex,colibri-imx7d-emmc-aster    # Module on Aster Carrier Board
               - toradex,colibri-imx7d-emmc-eval-v3  # Module on Colibri Evaluation Board V3
+              - toradex,colibri-imx7d-emmc-iris     # Module on Iris Carrier Board
+              - toradex,colibri-imx7d-emmc-iris-v2  # Module on Iris Carrier Board V2
           - const: toradex,colibri-imx7d-emmc
           - const: fsl,imx7d
 
@@ -865,6 +872,12 @@ properties:
           - const: toradex,verdin-imx8mm          # Verdin iMX8M Mini Module
           - const: fsl,imx8mm
 
+      - description: PHYTEC phyCORE-i.MX8MM SoM based boards
+        items:
+          - const: phytec,imx8mm-phyboard-polis-rdk # phyBOARD-Polis RDK
+          - const: phytec,imx8mm-phycore-som        # phyCORE-i.MX8MM SoM
+          - const: fsl,imx8mm
+
       - description: Variscite VAR-SOM-MX8MM based boards
         items:
           - const: variscite,var-som-mx8mm-symphony
@@ -914,6 +927,8 @@ properties:
       - description: i.MX8MP based Boards
         items:
           - enum:
+              - dh,imx8mp-dhcom-som       # i.MX8MP DHCOM SoM
+              - dh,imx8mp-dhcom-pdk2      # i.MX8MP DHCOM SoM on PDK2 board
               - fsl,imx8mp-evk            # i.MX8MP EVK Board
               - gateworks,imx8mp-gw74xx   # i.MX8MP Gateworks Board
               - toradex,verdin-imx8mp     # Verdin iMX8M Plus Modules
@@ -952,6 +967,18 @@ properties:
           - const: toradex,verdin-imx8mp          # Verdin iMX8M Plus Module
           - const: fsl,imx8mp
 
+      - description:
+          TQMa8MPxL is a series of LGA SOM featuring NXP i.MX8MP system-on-chip
+          variants. It is designed to be soldered on different carrier boards.
+          All CPU variants use the same device tree hence only one compatible
+          is needed. MBa8MPxL mainboard can be used as starterkit or in a boxed
+          version as an industrial computing device.
+        items:
+          - enum:
+              - tq,imx8mp-tqma8mpql-mba8mpxl # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM on MBa8MPxL
+          - const: tq,imx8mp-tqma8mpql       # TQ-Systems GmbH i.MX8MP TQMa8MPQL SOM
+          - const: fsl,imx8mp
+
       - description: i.MX8MQ based Boards
         items:
           - enum:
@@ -1020,6 +1047,12 @@ properties:
               - fsl,imx8ulp-evk           # i.MX8ULP EVK Board
           - const: fsl,imx8ulp
 
+      - description: i.MX93 based Boards
+        items:
+          - enum:
+              - fsl,imx93-11x11-evk       # i.MX93 11x11 EVK Board
+          - const: fsl,imx93
+
       - description:
           Freescale Vybrid Platform Device Tree Bindings
 

Documentation/devicetree/bindings/arm/marvell/marvell,ac5.yaml

@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/marvell/marvell,ac5.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell Alleycat5/5X Platforms
+
+maintainers:
+  - Chris Packham <chris.packham@alliedtelesis.co.nz>
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - description: Alleycat5 (98DX25xx) Reference Design
+        items:
+          - enum:
+              - marvell,rd-ac5
+          - const: marvell,ac5
+
+      - description: Alleycat5X (98DX35xx) Reference Design
+        items:
+          - enum:
+              - marvell,rd-ac5x
+          - const: marvell,ac5x
+          - const: marvell,ac5
+
+additionalProperties: true
+
+...

Documentation/devicetree/bindings/arm/mediatek.yaml

@@ -131,6 +131,36 @@ properties:
           - enum:
               - mediatek,mt8183-evb
           - const: mediatek,mt8183
+      - description: Google Hayato
+        items:
+          - const: google,hayato-rev1
+          - const: google,hayato
+          - const: mediatek,mt8192
+      - description: Google Spherion (Acer Chromebook 514)
+        items:
+          - const: google,spherion-rev3
+          - const: google,spherion-rev2
+          - const: google,spherion-rev1
+          - const: google,spherion-rev0
+          - const: google,spherion
+          - const: mediatek,mt8192
+      - description: Acer Tomato (Acer Chromebook Spin 513 CP513-2H)
+        items:
+          - enum:
+              - google,tomato-rev2
+              - google,tomato-rev1
+          - const: google,tomato
+          - const: mediatek,mt8195
+      - description: Acer Tomato rev3 - 4 (Acer Chromebook Spin 513 CP513-2H)
+        items:
+          - const: google,tomato-rev4
+          - const: google,tomato-rev3
+          - const: google,tomato
+          - const: mediatek,mt8195
+      - items:
+          - enum:
+              - mediatek,mt8186-evb
+          - const: mediatek,mt8186
       - items:
           - enum:
               - mediatek,mt8192-evb

Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml

@@ -26,6 +26,7 @@ properties:
               - mediatek,mt8135-pericfg
               - mediatek,mt8173-pericfg
               - mediatek,mt8183-pericfg
+              - mediatek,mt8186-pericfg
               - mediatek,mt8195-pericfg
               - mediatek,mt8516-pericfg
           - const: syscon

Documentation/devicetree/bindings/arm/npcm/npcm.yaml

@@ -8,6 +8,7 @@ title: NPCM Platforms Device Tree Bindings
 
 maintainers:
   - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
+  - Tomer Maimon <tmaimon77@gmail.com>
 
 properties:
   $nodename:
@@ -26,4 +27,10 @@ properties:
               - nuvoton,npcm750-evb         # NPCM750 evaluation board
           - const: nuvoton,npcm750
 
+      - description: NPCM845 based boards
+        items:
+          - enum:
+              - nuvoton,npcm845-evb         # NPCM845 evaluation board
+          - const: nuvoton,npcm845
+
 additionalProperties: true

Documentation/devicetree/bindings/arm/npcm/nuvoton,gcr.yaml

@@ -8,6 +8,7 @@ title: Global Control Registers block in Nuvoton SoCs
 
 maintainers:
   - Jonathan Neuschäfer <j.neuschaefer@gmx.net>
+  - Tomer Maimon <tmaimon77@gmail.com>
 
 description:
   The Global Control Registers (GCR) are a block of registers in Nuvoton SoCs
@@ -20,6 +21,7 @@ properties:
       - enum:
           - nuvoton,wpcm450-gcr
           - nuvoton,npcm750-gcr
+          - nuvoton,npcm845-gcr
       - const: syscon
       - const: simple-mfd
 

Documentation/devicetree/bindings/arm/qcom.yaml

@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
 title: QCOM device tree bindings
 
 maintainers:
-  - Stephen Boyd <sboyd@codeaurora.org>
+  - Bjorn Andersson <bjorn.andersson@linaro.org>
 
 description: |
   Some qcom based bootloaders identify the dtb blob based on a set of
@@ -38,18 +38,24 @@ description: |
         msm8992
         msm8994
         msm8996
+        msm8998
+        qcs404
         sa8155p
         sa8540p
         sc7180
         sc7280
         sc8180x
         sc8280xp
+        sda660
         sdm630
         sdm632
+        sdm636
         sdm660
         sdm845
         sdx55
         sdx65
+        sm6125
+        sm6350
         sm7225
         sm8150
         sm8250
@@ -90,6 +96,11 @@ description: |
   A dragonboard board v0.1 of subtype 1 with an apq8074 SoC version 2, made in
   foundry 2.
 
+  There are many devices in the list below that run the standard ChromeOS
+  bootloader setup and use the open source depthcharge bootloader to boot the
+  OS. These devices do not use the scheme described above. For details, see:
+  https://docs.kernel.org/arm/google/chromebook-boot-flow.html
+
 properties:
   $nodename:
     const: "/"
@@ -153,28 +164,50 @@ properties:
           - const: qcom,msm8974
 
       - items:
-          - enum:
-              - alcatel,idol347
-          - const: qcom,msm8916-mtp/1
           - const: qcom,msm8916-mtp
+          - const: qcom,msm8916-mtp/1
           - const: qcom,msm8916
 
       - items:
           - enum:
-              - longcheer,l8150
+              - alcatel,idol347
+              - asus,z00l
+              - huawei,g7
+              - longcheer,l8910
               - samsung,a3u-eur
               - samsung,a5u-eur
+              - samsung,j5
+              - samsung,serranove
+              - wingtech,wt88047
           - const: qcom,msm8916
 
+      - items:
+          - const: longcheer,l8150
+          - const: qcom,msm8916-v1-qrd/9-v1
+          - const: qcom,msm8916
+
+      - items:
+          - enum:
+              - lg,bullhead
+              - microsoft,talkman
+              - xiaomi,libra
+          - const: qcom,msm8992
+
       - items:
           - enum:
               - sony,karin_windy
+          - const: qcom,apq8094
+
+      - items:
+          - enum:
+              - huawei,angler
+              - microsoft,cityman
+              - sony,ivy-row
               - sony,karin-row
               - sony,satsuki-row
               - sony,sumire-row
               - sony,suzuran-row
-              - qcom,msm8994
-          - const: qcom,apq8094
+          - const: qcom,msm8994
 
       - items:
           - enum:
@@ -190,9 +223,24 @@ properties:
               - sony,kagura-row
               - sony,keyaki-row
               - xiaomi,gemini
+              - xiaomi,natrium
               - xiaomi,scorpio
           - const: qcom,msm8996
 
+      - items:
+          - enum:
+              - asus,novago-tp370ql
+              - fxtec,pro1
+              - hp,envy-x2
+              - lenovo,miix-630
+              - oneplus,cheeseburger
+              - oneplus,dumpling
+              - qcom,msm8998-mtp
+              - sony,xperia-lilac
+              - sony,xperia-maple
+              - sony,xperia-poplar
+          - const: qcom,msm8998
+
       - items:
           - enum:
               - qcom,ipq4019-ap-dk01.1-c1
@@ -214,19 +262,317 @@ properties:
               - qcom,ipq8074-hk10-c2
           - const: qcom,ipq8074
 
-      - items:
+      - description: Qualcomm Technologies, Inc. SC7180 IDP
+        items:
           - enum:
               - qcom,sc7180-idp
           - const: qcom,sc7180
 
-      - items:
-          - enum:
-              - qcom,sc7280-crd
-              - qcom,sc7280-idp
-              - qcom,sc7280-idp2
-              - google,hoglin
-              - google,piglin
-              - google,senor
+      - description: HP Chromebook x2 11c (rev1 - 2)
+        items:
+          - const: google,coachz-rev1
+          - const: google,coachz-rev2
+          - const: qcom,sc7180
+
+      - description: HP Chromebook x2 11c (newest rev)
+        items:
+          - const: google,coachz
+          - const: qcom,sc7180
+
+      - description: HP Chromebook x2 11c with LTE (rev1 - 2)
+        items:
+          - const: google,coachz-rev1-sku0
+          - const: google,coachz-rev2-sku0
+          - const: qcom,sc7180
+
+      - description: HP Chromebook x2 11c with LTE (newest rev)
+        items:
+          - const: google,coachz-sku0
+          - const: qcom,sc7180
+
+      - description: Lenovo Chromebook Duet 5 13 (rev2)
+        items:
+          - const: google,homestar-rev2
+          - const: google,homestar-rev23
+          - const: qcom,sc7180
+
+      - description: Lenovo Chromebook Duet 5 13 (rev3)
+        items:
+          - const: google,homestar-rev3
+          - const: qcom,sc7180
+
+      - description: Lenovo Chromebook Duet 5 13 (newest rev)
+        items:
+          - const: google,homestar
+          - const: qcom,sc7180
+
+      - description: Google Kingoftown (rev0)
+        items:
+          - const: google,kingoftown-rev0
+          - const: qcom,sc7180
+
+      - description: Google Kingoftown (newest rev)
+        items:
+          - const: google,kingoftown
+          - const: qcom,sc7180
+
+      - description: Acer Chromebook Spin 513 (rev0)
+        items:
+          - const: google,lazor-rev0
+          - const: qcom,sc7180
+
+      - description: Acer Chromebook Spin 513 (rev1 - 2)
+        items:
+          - const: google,lazor-rev1
+          - const: google,lazor-rev2
+          - const: qcom,sc7180
+
+      - description: Acer Chromebook Spin 513 (rev3 - 8)
+        items:
+          - const: google,lazor-rev3
+          - const: google,lazor-rev4
+          - const: google,lazor-rev5
+          - const: google,lazor-rev6
+          - const: google,lazor-rev7
+          - const: google,lazor-rev8
+          - const: qcom,sc7180
+
+      - description: Acer Chromebook Spin 513 (newest rev)
+        items:
+          - const: google,lazor
+          - const: qcom,sc7180
+
+      - description: Acer Chromebook Spin 513 with KB Backlight (rev1 - 2)
+        items:
+          - const: google,lazor-rev1-sku2
+          - const: google,lazor-rev2-sku2
+          - const: qcom,sc7180
+
+      - description: Acer Chromebook Spin 513 with KB Backlight (rev3 - 8)
+        items:
+          - const: google,lazor-rev3-sku2
+          - const: google,lazor-rev4-sku2
+          - const: google,lazor-rev5-sku2
+          - const: google,lazor-rev6-sku2
+          - const: google,lazor-rev7-sku2
+          - const: google,lazor-rev8-sku2
+          - const: qcom,sc7180
+
+      - description: Acer Chromebook Spin 513 with KB Backlight (newest rev)
+        items:
+          - const: google,lazor-sku2
+          - const: qcom,sc7180
+
+      - description: Acer Chromebook Spin 513 with LTE (rev1 - 2)
+        items:
+          - const: google,lazor-rev1-sku0
+          - const: google,lazor-rev2-sku0
+          - const: qcom,sc7180
+
+      - description: Acer Chromebook Spin 513 with LTE (rev3 - 8)
+        items:
+          - const: google,lazor-rev3-sku0
+          - const: google,lazor-rev4-sku0
+          - const: google,lazor-rev5-sku0
+          - const: google,lazor-rev6-sku0
+          - const: google,lazor-rev7-sku0
+          - const: google,lazor-rev8-sku0
+          - const: qcom,sc7180
+
+      - description: Acer Chromebook Spin 513 with LTE (newest rev)
+        items:
+          - const: google,lazor-sku0
+          - const: qcom,sc7180
+
+      - description: Acer Chromebook 511 (rev4 - rev8)
+        items:
+          - const: google,lazor-rev4-sku4
+          - const: google,lazor-rev5-sku4
+          - const: google,lazor-rev6-sku4
+          - const: google,lazor-rev7-sku4
+          - const: google,lazor-rev8-sku4
+          - const: qcom,sc7180
+
+      - description: Acer Chromebook 511 (newest rev)
+        items:
+          - const: google,lazor-sku4
+          - const: qcom,sc7180
+
+      - description: Acer Chromebook 511 without Touchscreen (rev4)
+        items:
+          - const: google,lazor-rev4-sku5
+          - const: qcom,sc7180
+
+      - description: Acer Chromebook 511 without Touchscreen (rev5 - rev8)
+        items:
+          - const: google,lazor-rev5-sku5
+          - const: google,lazor-rev5-sku6
+          - const: google,lazor-rev6-sku6
+          - const: google,lazor-rev7-sku6
+          - const: google,lazor-rev8-sku6
+          - const: qcom,sc7180
+
+      - description: Acer Chromebook 511 without Touchscreen (newest rev)
+        items:
+          - const: google,lazor-sku6
+          - const: qcom,sc7180
+
+      - description: Google Mrbland with AUO panel (rev0)
+        items:
+          - const: google,mrbland-rev0-sku0
+          - const: qcom,sc7180
+
+      - description: Google Mrbland with AUO panel (newest rev)
+        items:
+          - const: google,mrbland-sku1536
+          - const: qcom,sc7180
+
+      - description: Google Mrbland with BOE panel (rev0)
+        items:
+          - const: google,mrbland-rev0-sku16
+          - const: qcom,sc7180
+
+      - description: Google Mrbland with BOE panel (newest rev)
+        items:
+          - const: google,mrbland-sku1024
+          - const: google,mrbland-sku768
+          - const: qcom,sc7180
+
+      - description: Google Pazquel with Parade (newest rev)
+        items:
+          - const: google,pazquel-sku5
+          - const: qcom,sc7180
+
+      - description: Google Pazquel with TI (newest rev)
+        items:
+          - const: google,pazquel-sku1
+          - const: qcom,sc7180
+
+      - description: Google Pazquel with LTE and Parade (newest rev)
+        items:
+          - const: google,pazquel-sku4
+          - const: qcom,sc7180
+
+      - description: Google Pazquel with LTE and TI (newest rev)
+        items:
+          - const: google,pazquel-sku0
+          - const: google,pazquel-sku2
+          - const: qcom,sc7180
+
+      - description: Sharp Dynabook Chromebook C1 (rev1)
+        items:
+          - const: google,pompom-rev1
+          - const: qcom,sc7180
+
+      - description: Sharp Dynabook Chromebook C1 (rev2)
+        items:
+          - const: google,pompom-rev2
+          - const: qcom,sc7180
+
+      - description: Sharp Dynabook Chromebook C1 (newest rev)
+        items:
+          - const: google,pompom
+          - const: qcom,sc7180
+
+      - description: Sharp Dynabook Chromebook C1 with LTE (rev1)
+        items:
+          - const: google,pompom-rev1-sku0
+          - const: qcom,sc7180
+
+      - description: Sharp Dynabook Chromebook C1 with LTE (rev2)
+        items:
+          - const: google,pompom-rev2-sku0
+          - const: qcom,sc7180
+
+      - description: Sharp Dynabook Chromebook C1 with LTE (newest rev)
+        items:
+          - const: google,pompom-sku0
+          - const: qcom,sc7180
+
+      - description: Google Quackingstick (newest rev)
+        items:
+          - const: google,quackingstick-sku1537
+          - const: qcom,sc7180
+
+      - description: Google Quackingstick with LTE (newest rev)
+        items:
+          - const: google,quackingstick-sku1536
+          - const: qcom,sc7180
+
+      - description: Google Trogdor (newest rev)
+        items:
+          - const: google,trogdor
+          - const: qcom,sc7180
+
+      - description: Google Trogdor with LTE (newest rev)
+        items:
+          - const: google,trogdor-sku0
+          - const: qcom,sc7180
+
+      - description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel (rev0)
+        items:
+          - const: google,wormdingler-rev0-sku16
+          - const: qcom,sc7180
+
+      - description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel (newest rev)
+        items:
+          - const: google,wormdingler-sku1024
+          - const: qcom,sc7180
+
+      - description: Lenovo IdeaPad Chromebook Duet 3 with BOE panel and rt5682s (newest rev)
+        items:
+          - const: google,wormdingler-sku1025
+          - const: qcom,sc7180
+
+      - description: Lenovo IdeaPad Chromebook Duet 3 with INX panel (rev0)
+        items:
+          - const: google,wormdingler-rev0-sku0
+          - const: qcom,sc7180
+
+      - description: Lenovo IdeaPad Chromebook Duet 3 with INX panel (newest rev)
+        items:
+          - const: google,wormdingler-sku0
+          - const: qcom,sc7180
+
+      - description: Lenovo IdeaPad Chromebook Duet 3 with INX panel and rt5682s (newest rev)
+        items:
+          - const: google,wormdingler-sku1
+          - const: qcom,sc7180
+
+      - description: Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4)
+        items:
+          - const: qcom,sc7280-crd
+          - const: google,hoglin-rev3
+          - const: google,hoglin-rev4
+          - const: google,piglin-rev3
+          - const: google,piglin-rev4
+          - const: qcom,sc7280
+
+      - description: Qualcomm Technologies, Inc. sc7280 CRD platform (newest rev)
+        items:
+          - const: google,hoglin
+          - const: qcom,sc7280
+
+      - description: Qualcomm Technologies, Inc. sc7280 IDP SKU1 platform
+        items:
+          - const: qcom,sc7280-idp
+          - const: google,senor
+          - const: qcom,sc7280
+
+      - description: Qualcomm Technologies, Inc. sc7280 IDP SKU2 platform
+        items:
+          - const: qcom,sc7280-idp2
+          - const: google,piglin
+          - const: qcom,sc7280
+
+      - description: Google Herobrine (newest rev)
+        items:
+          - const: google,herobrine
+          - const: qcom,sc7280
+
+      - description: Google Villager (newest rev)
+        items:
+          - const: google,villager
           - const: qcom,sc7280
 
       - items:
@@ -238,14 +584,34 @@ properties:
 
       - items:
           - enum:
+              - lenovo,thinkpad-x13s
+              - qcom,sc8280xp-crd
               - qcom,sc8280xp-qrd
           - const: qcom,sc8280xp
 
+      - items:
+          - enum:
+              - sony,discovery-row
+              - sony,kirin-row
+              - sony,pioneer-row
+              - sony,voyager-row
+          - const: qcom,sdm630
+
+      - items:
+          - enum:
+              - inforce,ifc6560
+          - const: qcom,sda660
+
       - items:
           - enum:
               - fairphone,fp3
           - const: qcom,sdm632
 
+      - items:
+          - enum:
+              - sony,mermaid-row
+          - const: qcom,sdm636
+
       - items:
           - enum:
               - xiaomi,lavender
@@ -269,6 +635,13 @@ properties:
               - qcom,ipq6018-cp01-c1
           - const: qcom,ipq6018
 
+      - items:
+          - enum:
+              - qcom,qcs404-evb-1000
+              - qcom,qcs404-evb-4000
+          - const: qcom,qcs404-evb
+          - const: qcom,qcs404
+
       - items:
           - enum:
               - qcom,sa8155p-adp
@@ -279,6 +652,34 @@ properties:
               - qcom,sa8295p-adp
           - const: qcom,sa8540p
 
+      - items:
+          - enum:
+              - lenovo,yoga-c630
+              - lg,judyln
+              - lg,judyp
+              - oneplus,enchilada
+              - oneplus,fajita
+              - qcom,sdm845-mtp
+              - shift,axolotl
+              - samsung,w737
+              - sony,akari-row
+              - sony,akatsuki-row
+              - sony,apollo-row
+              - thundercomm,db845c
+              - xiaomi,beryllium
+              - xiaomi,polaris
+          - const: qcom,sdm845
+
+      - items:
+          - enum:
+              - sony,pdx201
+          - const: qcom,sm6125
+
+      - items:
+          - enum:
+              - sony,pdx213
+          - const: qcom,sm6350
+
       - items:
           - enum:
               - fairphone,fp4
@@ -286,19 +687,29 @@ properties:
 
       - items:
           - enum:
+              - microsoft,surface-duo
+              - qcom,sm8150-hdk
               - qcom,sm8150-mtp
+              - sony,bahamut-generic
+              - sony,griffin-generic
           - const: qcom,sm8150
 
       - items:
           - enum:
               - qcom,qrb5165-rb5
+              - qcom,sm8250-hdk
               - qcom,sm8250-mtp
+              - sony,pdx203-generic
+              - sony,pdx206-generic
           - const: qcom,sm8250
 
       - items:
           - enum:
+              - microsoft,surface-duo2
               - qcom,sm8350-hdk
               - qcom,sm8350-mtp
+              - sony,pdx214-generic
+              - sony,pdx215-generic
           - const: qcom,sm8350
 
       - items:

Documentation/devicetree/bindings/arm/rockchip.yaml

@@ -554,6 +554,11 @@ properties:
           - const: vamrs,rk3399pro-vmarc-som
           - const: rockchip,rk3399pro
 
+      - description: Radxa ROCK Pi S
+        items:
+          - const: radxa,rockpis
+          - const: rockchip,rk3308
+
       - description: Radxa Rock2 Square
         items:
           - const: radxa,rock2-square

Documentation/devicetree/bindings/arm/samsung/samsung-soc.yaml

@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/samsung/samsung-soc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S3C, S5P and Exynos SoC compatibles naming convention
+
+maintainers:
+  - Krzysztof Kozlowski <krzk@kernel.org>
+
+description: |
+  Guidelines for new compatibles for SoC blocks/components.
+  When adding new compatibles in new bindings, use the format::
+    samsung,SoC-IP
+
+  For example::
+    samsung,exynos5433-cmu-isp
+
+select:
+  properties:
+    compatible:
+      pattern: "^samsung,.*(s3c|s5pv|exynos)[0-9a-z]+.*$"
+  required:
+    - compatible
+
+properties:
+  compatible:
+    oneOf:
+      - description: Preferred naming style for compatibles of SoC components
+        pattern: "^samsung,(s3c|s5pv|exynos|exynosautov)[0-9]+-.*$"
+
+      # Legacy compatibles with wild-cards - list cannot grow with new bindings:
+      - enum:
+          - samsung,exynos4x12-pinctrl
+          - samsung,exynos4x12-usb2-phy
+          - samsung,s3c64xx-pinctrl
+          - samsung,s3c64xx-wakeup-eint
+
+additionalProperties: true

Documentation/devicetree/bindings/arm/stm32/stm32.yaml

@@ -59,12 +59,18 @@ properties:
               - prt,prtt1s   # Protonic PRTT1S
           - const: st,stm32mp151
 
-      - description: DH STM32MP153 SoM based Boards
+      - description: DH STM32MP153 DHCOM SoM based Boards
         items:
           - const: dh,stm32mp153c-dhcom-drc02
           - const: dh,stm32mp153c-dhcom-som
           - const: st,stm32mp153
 
+      - description: DH STM32MP153 DHCOR SoM based Boards
+        items:
+          - const: dh,stm32mp153c-dhcor-drc-compact
+          - const: dh,stm32mp153c-dhcor-som
+          - const: st,stm32mp153
+
       - items:
           - enum:
               - shiratech,stm32mp157a-iot-box # IoT Box

Documentation/devicetree/bindings/arm/sunplus,sp7021.yaml

@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) Sunplus Co., Ltd. 2021
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/sunplus,sp7021.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sunplus SP7021 Boards
+
+maintainers:
+  - qinjian <qinjian@cqplus1.com>
+
+description: |
+  ARM platforms using Sunplus SP7021, an ARM Cortex A7 (4-cores) based SoC.
+  Wiki: https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    items:
+      - enum:
+          - sunplus,sp7021-achip
+          - sunplus,sp7021-demo-v3
+      - const: sunplus,sp7021
+
+additionalProperties: true
+
+...

Documentation/devicetree/bindings/arm/sunxi.yaml

@@ -863,6 +863,11 @@ properties:
           - const: yones-toptech,bs1078-v2
           - const: allwinner,sun6i-a31s
 
+      - description: X96 Mate TV box
+        items:
+          - const: hechuang,x96-mate
+          - const: allwinner,sun50i-h616
+
       - description: Xunlong OrangePi
         items:
           - const: xunlong,orangepi
@@ -963,4 +968,9 @@ properties:
           - const: xunlong,orangepi-zero-plus2-h3
           - const: allwinner,sun8i-h3
 
+      - description: Xunlong OrangePi Zero 2
+        items:
+          - const: xunlong,orangepi-zero2
+          - const: allwinner,sun50i-h616
+
 additionalProperties: true

Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml

@@ -29,10 +29,20 @@ properties:
   compatible:
     enum:
       - allwinner,sun5i-a13-mbus
+      - allwinner,sun8i-a33-mbus
+      - allwinner,sun8i-a50-mbus
+      - allwinner,sun8i-a83t-mbus
       - allwinner,sun8i-h3-mbus
       - allwinner,sun8i-r40-mbus
+      - allwinner,sun8i-v3s-mbus
+      - allwinner,sun8i-v536-mbus
+      - allwinner,sun20i-d1-mbus
       - allwinner,sun50i-a64-mbus
+      - allwinner,sun50i-a100-mbus
       - allwinner,sun50i-h5-mbus
+      - allwinner,sun50i-h6-mbus
+      - allwinner,sun50i-h616-mbus
+      - allwinner,sun50i-r329-mbus
 
   reg:
     minItems: 1
@@ -81,13 +91,13 @@ required:
   - dma-ranges
 
 if:
-  properties:
-    compatible:
-      contains:
-        enum:
-          - allwinner,sun8i-h3-mbus
-          - allwinner,sun50i-a64-mbus
-          - allwinner,sun50i-h5-mbus
+  not:
+    properties:
+      compatible:
+        contains:
+          enum:
+            - allwinner,sun5i-a13-mbus
+            - allwinner,sun8i-r40-mbus
 
 then:
   properties:

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml

@@ -40,7 +40,6 @@ required:
   - compatible
   - reg
   - nvidia,bpmp
-  - status
 
 examples:
   - |

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml

@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: NVIDIA Tegra194 AXI2APB bridge
+
+maintainers:
+  - Sumit Gupta <sumitg@nvidia.com>
+
+properties:
+  $nodename:
+    pattern: "^axi2apb@([0-9a-f]+)$"
+
+  compatible:
+    enum:
+      - nvidia,tegra194-axi2apb
+
+  reg:
+    maxItems: 6
+    description: Physical base address and length of registers for all bridges
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+
+examples:
+  - |
+    axi2apb: axi2apb@2390000 {
+      compatible = "nvidia,tegra194-axi2apb";
+      reg = <0x02390000 0x1000>,
+            <0x023a0000 0x1000>,
+            <0x023b0000 0x1000>,
+            <0x023c0000 0x1000>,
+            <0x023d0000 0x1000>,
+            <0x023e0000 0x1000>;
+    };

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra194-cbb.yaml

@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: NVIDIA Tegra194 CBB 1.0 bindings
+
+maintainers:
+  - Sumit Gupta <sumitg@nvidia.com>
+
+description: |+
+  The Control Backbone (CBB) is comprised of the physical path from an
+  initiator to a target's register configuration space. CBB 1.0 has
+  multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
+  initiators and targets using different bridges like AXIP2P, AXI2APB.
+
+  This driver handles errors due to illegal register accesses reported
+  by the NOCs inside the CBB. NOCs reporting errors are cluster NOCs
+  "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
+  which is the main NOC.
+
+  By default, the access issuing initiator is informed about the error
+  using SError or Data Abort exception unless the ERD (Error Response
+  Disable) is enabled/set for that initiator. If the ERD is enabled, then
+  SError or Data Abort is masked and the error is reported with interrupt.
+
+  - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
+    errors due to illegal accesses from CCPLEX are reported by interrupts.
+    If ERD is not set, then error is reported by SError.
+  - For other initiators, the ERD is disabled. So, the access issuing
+    initiator is informed about the illegal access by Data Abort exception.
+    In addition, an interrupt is also generated to CCPLEX. These initiators
+    include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and
+    engines like TSEC (Security co-processor), NVDEC (NVIDIA Video Decoder
+    engine) etc which can initiate transactions.
+
+  The driver prints relevant debug information like Error Code, Error
+  Description, Master, Address, AXI ID, Cache, Protection, Security Group
+  etc on receiving error notification.
+
+properties:
+  $nodename:
+    pattern: "^[a-z]+-noc@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra194-cbb-noc
+      - nvidia,tegra194-aon-noc
+      - nvidia,tegra194-bpmp-noc
+      - nvidia,tegra194-rce-noc
+      - nvidia,tegra194-sce-noc
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    description:
+      CCPLEX receives secure or nonsecure interrupt depending on error type.
+      A secure interrupt is received for SEC(firewall) & SLV errors and a
+      non-secure interrupt is received for TMO & DEC errors.
+    items:
+      - description: non-secure interrupt
+      - description: secure interrupt
+
+  nvidia,axi2apb:
+    $ref: '/schemas/types.yaml#/definitions/phandle'
+    description:
+      Specifies the node having all axi2apb bridges which need to be checked
+      for any error logged in their status register.
+
+  nvidia,apbmisc:
+    $ref: '/schemas/types.yaml#/definitions/phandle'
+    description:
+      Specifies the apbmisc node which need to be used for reading the ERD
+      register.
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - nvidia,apbmisc
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    cbb-noc@2300000 {
+        compatible = "nvidia,tegra194-cbb-noc";
+        reg = <0x02300000 0x1000>;
+        interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+        nvidia,axi2apb = <&axi2apb>;
+        nvidia,apbmisc = <&apbmisc>;
+    };

Documentation/devicetree/bindings/arm/tegra/nvidia,tegra234-cbb.yaml

@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: NVIDIA Tegra CBB 2.0 bindings
+
+maintainers:
+  - Sumit Gupta <sumitg@nvidia.com>
+
+description: |+
+  The Control Backbone (CBB) is comprised of the physical path from an
+  initiator to a target's register configuration space. CBB 2.0 consists
+  of multiple sub-blocks connected to each other to create a topology.
+  The Tegra234 SoC has different fabrics based on CBB 2.0 architecture
+  which include cluster fabrics BPMP, AON, PSC, SCE, RCE, DCE, FSI and
+  "CBB central fabric".
+
+  In CBB 2.0, each initiator which can issue transactions connects to a
+  Root Master Node (MN) before it connects to any other element of the
+  fabric. Each Root MN contains a Error Monitor (EM) which detects and
+  logs error. Interrupts from various EM blocks are collated by Error
+  Notifier (EN) which is per fabric and presents a single interrupt from
+  fabric to the SoC interrupt controller.
+
+  The driver handles errors from CBB due to illegal register accesses
+  and prints debug information about failed transaction on receiving
+  the interrupt from EN. Debug information includes Error Code, Error
+  Description, MasterID, Fabric, SlaveID, Address, Cache, Protection,
+  Security Group etc on receiving error notification.
+
+  If the Error Response Disable (ERD) is set/enabled for an initiator,
+  then SError or Data abort exception error response is masked and an
+  interrupt is used for reporting errors due to illegal accesses from
+  that initiator. The value returned on read failures is '0xFFFFFFFF'
+  for compatibility with PCIE.
+
+properties:
+  $nodename:
+    pattern: "^[a-z]+-fabric@[0-9a-f]+$"
+
+  compatible:
+    enum:
+      - nvidia,tegra234-aon-fabric
+      - nvidia,tegra234-bpmp-fabric
+      - nvidia,tegra234-cbb-fabric
+      - nvidia,tegra234-dce-fabric
+      - nvidia,tegra234-rce-fabric
+      - nvidia,tegra234-sce-fabric
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    items:
+      - description: secure interrupt from error notifier
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    cbb-fabric@1300000 {
+      compatible = "nvidia,tegra234-cbb-fabric";
+      reg = <0x13a00000 0x400000>;
+      interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+    };

Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml

@@ -28,6 +28,9 @@ properties:
       - items:
           - const: allwinner,sun8i-r40-de2-clk
           - const: allwinner,sun8i-h3-de2-clk
+      - items:
+          - const: allwinner,sun20i-d1-de2-clk
+          - const: allwinner,sun50i-h5-de2-clk
 
   reg:
     maxItems: 1

Documentation/devicetree/bindings/clock/fsl,scu-clk.yaml

@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/fsl,scu-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX SCU Client Device Node - Clock bindings based on SCU Message Protocol
+
+maintainers:
+  - Abel Vesa <abel.vesa@nxp.com>
+
+description: i.MX SCU Client Device Node
+  Client nodes are maintained as children of the relevant IMX-SCU device node.
+  This binding uses the common clock binding.
+  (Documentation/devicetree/bindings/clock/clock-bindings.txt)
+  The clock consumer should specify the desired clock by having the clock
+  ID in its "clocks" phandle cell. See the full list of clock IDs from
+  include/dt-bindings/clock/imx8qxp-clock.h
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - fsl,imx8dxl-clk
+          - fsl,imx8qm-clk
+          - fsl,imx8qxp-clk
+      - const: fsl,scu-clk
+
+  '#clock-cells':
+    const: 2
+
+required:
+  - compatible
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller {
+        compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
+        #clock-cells = <2>;
+    };

Documentation/devicetree/bindings/clock/nuvoton,npcm845-clk.yaml

@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nuvoton,npcm845-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton NPCM8XX Clock Controller Binding
+
+maintainers:
+  - Tomer Maimon <tmaimon77@gmail.com>
+
+description: |
+  Nuvoton Arbel BMC NPCM8XX contains an integrated clock controller, which
+  generates and supplies clocks to all modules within the BMC.
+
+properties:
+  compatible:
+    enum:
+      - nuvoton,npcm845-clk
+
+  reg:
+    maxItems: 1
+
+  '#clock-cells':
+    const: 1
+    description:
+      See include/dt-bindings/clock/nuvoton,npcm8xx-clock.h for the full
+      list of NPCM8XX clock IDs.
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    ahb {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        clock-controller@f0801000 {
+            compatible = "nuvoton,npcm845-clk";
+            reg = <0x0 0xf0801000 0x0 0x1000>;
+            #clock-cells = <1>;
+        };
+    };
+...

Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml

@@ -4,18 +4,19 @@
 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
+title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250/SM8350
 
 maintainers:
   - Jonathan Marek <jonathan@marek.ca>
 
 description: |
   Qualcomm display clock control module which supports the clocks, resets and
-  power domains on SM8150 and SM8250.
+  power domains on SM8150/SM8250/SM8350.
 
   See also:
     dt-bindings/clock/qcom,dispcc-sm8150.h
     dt-bindings/clock/qcom,dispcc-sm8250.h
+    dt-bindings/clock/qcom,dispcc-sm8350.h
 
 properties:
   compatible:
@@ -23,6 +24,7 @@ properties:
       - qcom,sc8180x-dispcc
       - qcom,sm8150-dispcc
       - qcom,sm8250-dispcc
+      - qcom,sm8350-dispcc
 
   clocks:
     items:

Documentation/devicetree/bindings/clock/qcom,gpucc-sm8350.yaml

@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gpucc-sm8350.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Graphics Clock & Reset Controller Binding
+
+maintainers:
+  - Robert Foss <robert.foss@linaro.org>
+
+description: |
+  Qualcomm graphics clock control module which supports the clocks, resets and
+  power domains on Qualcomm SoCs.
+
+  See also:
+    dt-bindings/clock/qcom,gpucc-sm8350.h
+
+properties:
+  compatible:
+    enum:
+      - qcom,sm8350-gpucc
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: GPLL0 main branch source
+      - description: GPLL0 div branch source
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - '#clock-cells'
+  - '#reset-cells'
+  - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-sm8350.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        clock-controller@3d90000 {
+            compatible = "qcom,sm8350-gpucc";
+            reg = <0 0x03d90000 0 0x9000>;
+            clocks = <&rpmhcc RPMH_CXO_CLK>,
+                     <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+                     <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+            #clock-cells = <1>;
+            #reset-cells = <1>;
+            #power-domain-cells = <1>;
+        };
+    };
+...

Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml

@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm8450-camcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Camera Clock & Reset Controller Binding for SM8450
+
+maintainers:
+  - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
+
+description: |
+  Qualcomm camera clock control module which supports the clocks, resets and
+  power domains on SM8450.
+
+  See also include/dt-bindings/clock/qcom,sm8450-camcc.h
+
+properties:
+  compatible:
+    const: qcom,sm8450-camcc
+
+  clocks:
+    items:
+      - description: Camera AHB clock from GCC
+      - description: Board XO source
+      - description: Board active XO source
+      - description: Sleep clock source
+
+  power-domains:
+    maxItems: 1
+    description:
+      A phandle and PM domain specifier for the MMCX power domain.
+
+  required-opps:
+    description:
+      A phandle to an OPP node describing required MMCX performance point.
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - power-domains
+  - required-opps
+  - '#clock-cells'
+  - '#reset-cells'
+  - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,gcc-sm8450.h>
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    #include <dt-bindings/power/qcom-rpmpd.h>
+    clock-controller@ade0000 {
+      compatible = "qcom,sm8450-camcc";
+      reg = <0xade0000 0x20000>;
+      clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+               <&rpmhcc RPMH_CXO_CLK>,
+               <&rpmhcc RPMH_CXO_CLK_A>,
+               <&sleep_clk>;
+      power-domains = <&rpmhpd SM8450_MMCX>;
+      required-opps = <&rpmhpd_opp_low_svs>;
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...

Documentation/devicetree/bindings/clock/samsung,exynos7885-clock.yaml

@@ -33,6 +33,7 @@ properties:
     enum:
       - samsung,exynos7885-cmu-top
       - samsung,exynos7885-cmu-core
+      - samsung,exynos7885-cmu-fsys
       - samsung,exynos7885-cmu-peri
 
   clocks:
@@ -88,6 +89,32 @@ allOf:
             - const: dout_core_cci
             - const: dout_core_g3d
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynos7885-cmu-fsys
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: CMU_FSYS bus clock (from CMU_TOP)
+            - description: MMC_CARD clock (from CMU_TOP)
+            - description: MMC_EMBD clock (from CMU_TOP)
+            - description: MMC_SDIO clock (from CMU_TOP)
+            - description: USB30DRD clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: dout_fsys_bus
+            - const: dout_fsys_mmc_card
+            - const: dout_fsys_mmc_embd
+            - const: dout_fsys_mmc_sdio
+            - const: dout_fsys_usb30drd
+
   - if:
       properties:
         compatible:

Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml

@@ -78,6 +78,7 @@ if:
       contains:
         enum:
           - st,stm32mp1-rcc-secure
+          - st,stm32mp13-rcc
 then:
   properties:
     clocks:

Documentation/devicetree/bindings/clock/sunplus,sp7021-clkc.yaml

@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) Sunplus Co., Ltd. 2021
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/sunplus,sp7021-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sunplus SP7021 SoC Clock Controller
+
+maintainers:
+  - Qin Jian <qinjian@cqplus1.com>
+
+properties:
+  compatible:
+    const: sunplus,sp7021-clkc
+
+  reg:
+    maxItems: 3
+
+  clocks:
+    maxItems: 1
+
+  "#clock-cells":
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    extclk: osc0 {
+      compatible = "fixed-clock";
+      #clock-cells = <0>;
+      clock-frequency = <27000000>;
+      clock-output-names = "extclk";
+    };
+
+    clkc: clock-controller@9c000004 {
+      compatible = "sunplus,sp7021-clkc";
+      reg = <0x9c000004 0x28>,
+            <0x9c000200 0x44>,
+            <0x9c000268 0x08>;
+      clocks = <&extclk>;
+      #clock-cells = <1>;
+    };
+
+...

Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml

@@ -63,8 +63,8 @@ additionalProperties: true
 examples:
   - |
     / {
-        model = "Qualcomm Technologies, Inc. QCS404";
-        compatible = "qcom,qcs404";
+        model = "Qualcomm Technologies, Inc. QCS404 EVB 1000";
+        compatible = "qcom,qcs404-evb-1000", "qcom,qcs404-evb", "qcom,qcs404";
         #address-cells = <2>;
         #size-cells = <2>;
 

Documentation/devicetree/bindings/devfreq/exynos-bus.txt

@@ -1,488 +0,0 @@
-* Generic Exynos Bus frequency device
-
-The Samsung Exynos SoC has many buses for data transfer between DRAM
-and sub-blocks in SoC. Most Exynos SoCs share the common architecture
-for buses. Generally, each bus of Exynos SoC includes a source clock
-and a power line, which are able to change the clock frequency
-of the bus in runtime. To monitor the usage of each bus in runtime,
-the driver uses the PPMU (Platform Performance Monitoring Unit), which
-is able to measure the current load of sub-blocks.
-
-The Exynos SoC includes the various sub-blocks which have the each AXI bus.
-The each AXI bus has the owned source clock but, has not the only owned
-power line. The power line might be shared among one more sub-blocks.
-So, we can divide into two type of device as the role of each sub-block.
-There are two type of bus devices as following:
-- parent bus device
-- passive bus device
-
-Basically, parent and passive bus device share the same power line.
-The parent bus device can only change the voltage of shared power line
-and the rest bus devices (passive bus device) depend on the decision of
-the parent bus device. If there are three blocks which share the VDD_xxx
-power line, Only one block should be parent device and then the rest blocks
-should depend on the parent device as passive device.
-
-	VDD_xxx |--- A block (parent)
-		|--- B block (passive)
-		|--- C block (passive)
-
-There are a little different composition among Exynos SoC because each Exynos
-SoC has different sub-blocks. Therefore, such difference should be specified
-in devicetree file instead of each device driver. In result, this driver
-is able to support the bus frequency for all Exynos SoCs.
-
-Required properties for all bus devices:
-- compatible: Should be "samsung,exynos-bus".
-- clock-names : the name of clock used by the bus, "bus".
-- clocks : phandles for clock specified in "clock-names" property.
-- operating-points-v2: the OPP table including frequency/voltage information
-  to support DVFS (Dynamic Voltage/Frequency Scaling) feature.
-
-Required properties only for parent bus device:
-- vdd-supply: the regulator to provide the buses with the voltage.
-- devfreq-events: the devfreq-event device to monitor the current utilization
-  of buses.
-
-Required properties only for passive bus device:
-- devfreq: the parent bus device.
-
-Optional properties only for parent bus device:
-- exynos,saturation-ratio: the percentage value which is used to calibrate
-			the performance count against total cycle count.
-
-Optional properties for the interconnect functionality (QoS frequency
-constraints):
-- #interconnect-cells: should be 0.
-- interconnects: as documented in ../interconnect.txt, describes a path at the
-  higher level interconnects used by this interconnect provider.
-  If this interconnect provider is directly linked to a top level interconnect
-  provider the property contains only one phandle. The provider extends
-  the interconnect graph by linking its node to a node registered by provider
-  pointed to by first phandle in the 'interconnects' property.
-
-- samsung,data-clock-ratio: ratio of the data throughput in B/s to minimum data
-   clock frequency in Hz, default value is 8 when this property is missing.
-
-Detailed correlation between sub-blocks and power line according to Exynos SoC:
-- In case of Exynos3250, there are two power line as following:
-	VDD_MIF |--- DMC
-
-	VDD_INT |--- LEFTBUS (parent device)
-		|--- PERIL
-		|--- MFC
-		|--- G3D
-		|--- RIGHTBUS
-		|--- PERIR
-		|--- FSYS
-		|--- LCD0
-		|--- PERIR
-		|--- ISP
-		|--- CAM
-
-- In case of Exynos4210, there is one power line as following:
-	VDD_INT |--- DMC (parent device)
-		|--- LEFTBUS
-		|--- PERIL
-		|--- MFC(L)
-		|--- G3D
-		|--- TV
-		|--- LCD0
-		|--- RIGHTBUS
-		|--- PERIR
-		|--- MFC(R)
-		|--- CAM
-		|--- FSYS
-		|--- GPS
-		|--- LCD0
-		|--- LCD1
-
-- In case of Exynos4x12, there are two power line as following:
-	VDD_MIF |--- DMC
-
-	VDD_INT |--- LEFTBUS (parent device)
-		|--- PERIL
-		|--- MFC(L)
-		|--- G3D
-		|--- TV
-		|--- IMAGE
-		|--- RIGHTBUS
-		|--- PERIR
-		|--- MFC(R)
-		|--- CAM
-		|--- FSYS
-		|--- GPS
-		|--- LCD0
-		|--- ISP
-
-- In case of Exynos5422, there are two power line as following:
-	VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
-	        |--- DREX 1
-
-	VDD_INT |--- NoC_Core (parent device)
-		|--- G2D
-		|--- G3D
-		|--- DISP1
-		|--- NoC_WCORE
-		|--- GSCL
-		|--- MSCL
-		|--- ISP
-		|--- MFC
-		|--- GEN
-		|--- PERIS
-		|--- PERIC
-		|--- FSYS
-		|--- FSYS2
-
-- In case of Exynos5433, there is VDD_INT power line as following:
-	VDD_INT |--- G2D (parent device)
-		|--- MSCL
-		|--- GSCL
-		|--- JPEG
-		|--- MFC
-		|--- HEVC
-		|--- BUS0
-		|--- BUS1
-		|--- BUS2
-		|--- PERIS (Fixed clock rate)
-		|--- PERIC (Fixed clock rate)
-		|--- FSYS  (Fixed clock rate)
-
-Example 1:
-	Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
-	power line (regulator). The MIF (Memory Interface) AXI bus is used to
-	transfer data between DRAM and CPU and uses the VDD_MIF regulator.
-
-	- MIF (Memory Interface) block
-	: VDD_MIF |--- DMC (Dynamic Memory Controller)
-
-	- INT (Internal) block
-	: VDD_INT |--- LEFTBUS (parent device)
-		  |--- PERIL
-		  |--- MFC
-		  |--- G3D
-		  |--- RIGHTBUS
-		  |--- FSYS
-		  |--- LCD0
-		  |--- PERIR
-		  |--- ISP
-		  |--- CAM
-
-	- MIF bus's frequency/voltage table
-	-----------------------
-	|Lv| Freq   | Voltage |
-	-----------------------
-	|L1| 50000  |800000   |
-	|L2| 100000 |800000   |
-	|L3| 134000 |800000   |
-	|L4| 200000 |825000   |
-	|L5| 400000 |875000   |
-	-----------------------
-
-	- INT bus's frequency/voltage table
-	----------------------------------------------------------
-	|Block|LEFTBUS|RIGHTBUS|MCUISP |ISP    |PERIL  ||VDD_INT |
-	| name|       |LCD0    |       |       |       ||        |
-	|     |       |FSYS    |       |       |       ||        |
-	|     |       |MFC     |       |       |       ||        |
-	----------------------------------------------------------
-	|Mode |*parent|passive |passive|passive|passive||        |
-	----------------------------------------------------------
-	|Lv   |Frequency                               ||Voltage |
-	----------------------------------------------------------
-	|L1   |50000  |50000   |50000  |50000  |50000  ||900000  |
-	|L2   |80000  |80000   |80000  |80000  |80000  ||900000  |
-	|L3   |100000 |100000  |100000 |100000 |100000 ||1000000 |
-	|L4   |134000 |134000  |200000 |200000 |       ||1000000 |
-	|L5   |200000 |200000  |400000 |300000 |       ||1000000 |
-	----------------------------------------------------------
-
-Example 2:
-	The bus of DMC (Dynamic Memory Controller) block in exynos3250.dtsi
-	is listed below:
-
-	bus_dmc: bus_dmc {
-		compatible = "samsung,exynos-bus";
-		clocks = <&cmu_dmc CLK_DIV_DMC>;
-		clock-names = "bus";
-		operating-points-v2 = <&bus_dmc_opp_table>;
-		status = "disabled";
-	};
-
-	bus_dmc_opp_table: opp_table1 {
-		compatible = "operating-points-v2";
-		opp-shared;
-
-		opp-50000000 {
-			opp-hz = /bits/ 64 <50000000>;
-			opp-microvolt = <800000>;
-		};
-		opp-100000000 {
-			opp-hz = /bits/ 64 <100000000>;
-			opp-microvolt = <800000>;
-		};
-		opp-134000000 {
-			opp-hz = /bits/ 64 <134000000>;
-			opp-microvolt = <800000>;
-		};
-		opp-200000000 {
-			opp-hz = /bits/ 64 <200000000>;
-			opp-microvolt = <825000>;
-		};
-		opp-400000000 {
-			opp-hz = /bits/ 64 <400000000>;
-			opp-microvolt = <875000>;
-		};
-	};
-
-	bus_leftbus: bus_leftbus {
-		compatible = "samsung,exynos-bus";
-		clocks = <&cmu CLK_DIV_GDL>;
-		clock-names = "bus";
-		operating-points-v2 = <&bus_leftbus_opp_table>;
-		status = "disabled";
-	};
-
-	bus_rightbus: bus_rightbus {
-		compatible = "samsung,exynos-bus";
-		clocks = <&cmu CLK_DIV_GDR>;
-		clock-names = "bus";
-		operating-points-v2 = <&bus_leftbus_opp_table>;
-		status = "disabled";
-	};
-
-	bus_lcd0: bus_lcd0 {
-		compatible = "samsung,exynos-bus";
-		clocks = <&cmu CLK_DIV_ACLK_160>;
-		clock-names = "bus";
-		operating-points-v2 = <&bus_leftbus_opp_table>;
-		status = "disabled";
-	};
-
-	bus_fsys: bus_fsys {
-		compatible = "samsung,exynos-bus";
-		clocks = <&cmu CLK_DIV_ACLK_200>;
-		clock-names = "bus";
-		operating-points-v2 = <&bus_leftbus_opp_table>;
-		status = "disabled";
-	};
-
-	bus_mcuisp: bus_mcuisp {
-		compatible = "samsung,exynos-bus";
-		clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>;
-		clock-names = "bus";
-		operating-points-v2 = <&bus_mcuisp_opp_table>;
-		status = "disabled";
-	};
-
-	bus_isp: bus_isp {
-		compatible = "samsung,exynos-bus";
-		clocks = <&cmu CLK_DIV_ACLK_266>;
-		clock-names = "bus";
-		operating-points-v2 = <&bus_isp_opp_table>;
-		status = "disabled";
-	};
-
-	bus_peril: bus_peril {
-		compatible = "samsung,exynos-bus";
-		clocks = <&cmu CLK_DIV_ACLK_100>;
-		clock-names = "bus";
-		operating-points-v2 = <&bus_peril_opp_table>;
-		status = "disabled";
-	};
-
-	bus_mfc: bus_mfc {
-		compatible = "samsung,exynos-bus";
-		clocks = <&cmu CLK_SCLK_MFC>;
-		clock-names = "bus";
-		operating-points-v2 = <&bus_leftbus_opp_table>;
-		status = "disabled";
-	};
-
-	bus_leftbus_opp_table: opp_table1 {
-		compatible = "operating-points-v2";
-		opp-shared;
-
-		opp-50000000 {
-			opp-hz = /bits/ 64 <50000000>;
-			opp-microvolt = <900000>;
-		};
-		opp-80000000 {
-			opp-hz = /bits/ 64 <80000000>;
-			opp-microvolt = <900000>;
-		};
-		opp-100000000 {
-			opp-hz = /bits/ 64 <100000000>;
-			opp-microvolt = <1000000>;
-		};
-		opp-134000000 {
-			opp-hz = /bits/ 64 <134000000>;
-			opp-microvolt = <1000000>;
-		};
-		opp-200000000 {
-			opp-hz = /bits/ 64 <200000000>;
-			opp-microvolt = <1000000>;
-		};
-	};
-
-	bus_mcuisp_opp_table: opp_table2 {
-		compatible = "operating-points-v2";
-		opp-shared;
-
-		opp-50000000 {
-			opp-hz = /bits/ 64 <50000000>;
-		};
-		opp-80000000 {
-			opp-hz = /bits/ 64 <80000000>;
-		};
-		opp-100000000 {
-			opp-hz = /bits/ 64 <100000000>;
-		};
-		opp-200000000 {
-			opp-hz = /bits/ 64 <200000000>;
-		};
-		opp-400000000 {
-			opp-hz = /bits/ 64 <400000000>;
-		};
-	};
-
-	bus_isp_opp_table: opp_table3 {
-		compatible = "operating-points-v2";
-		opp-shared;
-
-		opp-50000000 {
-			opp-hz = /bits/ 64 <50000000>;
-		};
-		opp-80000000 {
-			opp-hz = /bits/ 64 <80000000>;
-		};
-		opp-100000000 {
-			opp-hz = /bits/ 64 <100000000>;
-		};
-		opp-200000000 {
-			opp-hz = /bits/ 64 <200000000>;
-		};
-		opp-300000000 {
-			opp-hz = /bits/ 64 <300000000>;
-		};
-	};
-
-	bus_peril_opp_table: opp_table4 {
-		compatible = "operating-points-v2";
-		opp-shared;
-
-		opp-50000000 {
-			opp-hz = /bits/ 64 <50000000>;
-		};
-		opp-80000000 {
-			opp-hz = /bits/ 64 <80000000>;
-		};
-		opp-100000000 {
-			opp-hz = /bits/ 64 <100000000>;
-		};
-	};
-
-
-	Usage case to handle the frequency and voltage of bus on runtime
-	in exynos3250-rinato.dts is listed below:
-
-	&bus_dmc {
-		devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
-		vdd-supply = <&buck1_reg>;	/* VDD_MIF */
-		status = "okay";
-	};
-
-	&bus_leftbus {
-		devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
-		vdd-supply = <&buck3_reg>;
-		status = "okay";
-	};
-
-	&bus_rightbus {
-		devfreq = <&bus_leftbus>;
-		status = "okay";
-	};
-
-	&bus_lcd0 {
-		devfreq = <&bus_leftbus>;
-		status = "okay";
-	};
-
-	&bus_fsys {
-		devfreq = <&bus_leftbus>;
-		status = "okay";
-	};
-
-	&bus_mcuisp {
-		devfreq = <&bus_leftbus>;
-		status = "okay";
-	};
-
-	&bus_isp {
-		devfreq = <&bus_leftbus>;
-		status = "okay";
-	};
-
-	&bus_peril {
-		devfreq = <&bus_leftbus>;
-		status = "okay";
-	};
-
-	&bus_mfc {
-		devfreq = <&bus_leftbus>;
-		status = "okay";
-	};
-
-Example 3:
-	An interconnect path "bus_display -- bus_leftbus -- bus_dmc" on
-	Exynos4412 SoC with video mixer as an interconnect consumer device.
-
-	soc {
-		bus_dmc: bus_dmc {
-			compatible = "samsung,exynos-bus";
-			clocks = <&clock CLK_DIV_DMC>;
-			clock-names = "bus";
-			operating-points-v2 = <&bus_dmc_opp_table>;
-			samsung,data-clock-ratio = <4>;
-			#interconnect-cells = <0>;
-		};
-
-		bus_leftbus: bus_leftbus {
-			compatible = "samsung,exynos-bus";
-			clocks = <&clock CLK_DIV_GDL>;
-			clock-names = "bus";
-			operating-points-v2 = <&bus_leftbus_opp_table>;
-			#interconnect-cells = <0>;
-			interconnects = <&bus_dmc>;
-		};
-
-		bus_display: bus_display {
-			compatible = "samsung,exynos-bus";
-			clocks = <&clock CLK_ACLK160>;
-			clock-names = "bus";
-			operating-points-v2 = <&bus_display_opp_table>;
-			#interconnect-cells = <0>;
-			interconnects = <&bus_leftbus &bus_dmc>;
-		};
-
-		bus_dmc_opp_table: opp_table1 {
-			compatible = "operating-points-v2";
-			/* ... */
-		}
-
-		bus_leftbus_opp_table: opp_table3 {
-			compatible = "operating-points-v2";
-			/* ... */
-		};
-
-		bus_display_opp_table: opp_table4 {
-			compatible = "operating-points-v2";
-			/* .. */
-		};
-
-		&mixer {
-			compatible = "samsung,exynos4212-mixer";
-			interconnects = <&bus_display &bus_dmc>;
-			/* ... */
-		};
-	};

Documentation/devicetree/bindings/display/panel/lgphilips,lb035q02.yaml

@@ -21,6 +21,9 @@ properties:
   enable-gpios: true
   port: true
 
+  spi-cpha: true
+  spi-cpol: true
+
 required:
   - compatible
   - enable-gpios

Documentation/devicetree/bindings/display/panel/samsung,ld9040.yaml

@@ -42,6 +42,9 @@ properties:
   panel-height-mm:
     description: physical panel height [mm]
 
+  spi-cpha: true
+  spi-cpol: true
+
 required:
   - compatible
   - reg

Documentation/devicetree/bindings/display/panel/sitronix,st7789v.yaml

@@ -23,6 +23,9 @@ properties:
   backlight: true
   port: true
 
+  spi-cpha: true
+  spi-cpol: true
+
 required:
   - compatible
   - reg

Documentation/devicetree/bindings/display/panel/tpo,td.yaml

@@ -28,6 +28,9 @@ properties:
   backlight: true
   port: true
 
+  spi-cpha: true
+  spi-cpol: true
+
 required:
   - compatible
   - port

Documentation/devicetree/bindings/firmware/arm,scmi.yaml

@@ -183,6 +183,12 @@ properties:
             required:
               - reg
 
+  protocol@18:
+    type: object
+    properties:
+      reg:
+        const: 0x18
+
 additionalProperties: false
 
 patternProperties:
@@ -323,6 +329,10 @@ examples:
                     };
                 };
             };
+
+            scmi_powercap: protocol@18 {
+                reg = <0x18>;
+            };
         };
     };
 

Documentation/devicetree/bindings/firmware/fsl,scu.yaml

@@ -0,0 +1,210 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/fsl,scu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX System Controller Firmware (SCFW)
+
+maintainers:
+  - Dong Aisheng <aisheng.dong@nxp.com>
+
+description:
+  The System Controller Firmware (SCFW) is a low-level system function
+  which runs on a dedicated Cortex-M core to provide power, clock, and
+  resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
+  (QM, QP), and i.MX8QX (QXP, DX).
+  The AP communicates with the SC using a multi-ported MU module found
+  in the LSIO subsystem. The current definition of this MU module provides
+  5 remote AP connections to the SC to support up to 5 execution environments
+  (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
+  with the LSIO DSC IP bus. The SC firmware will communicate with this MU
+  using the MSI bus.
+
+properties:
+  compatible:
+    const: fsl,imx-scu
+
+  clock-controller:
+    description:
+      Clock controller node that provides the clocks controlled by the SCU
+    $ref: /schemas/clock/fsl,scu-clk.yaml
+
+  ocotp:
+    description:
+      OCOTP controller node provided by the SCU
+    $ref: /schemas/nvmem/fsl,scu-ocotp.yaml
+
+  keys:
+    description:
+      Keys provided by the SCU
+    $ref: /schemas/input/fsl,scu-key.yaml
+
+  mboxes:
+    description:
+      A list of phandles of TX MU channels followed by a list of phandles of
+      RX MU channels. The list may include at the end one more optional MU
+      channel for general interrupt. The number of expected tx and rx
+      channels is 1 TX and 1 RX channels if MU instance is "fsl,imx8-mu-scu"
+      compatible, 4 TX and 4 RX channels otherwise. All MU channels must be
+      within the same MU instance. Cross instances are not allowed. The MU
+      instance can only be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users
+      need to ensure that one is used that does not conflict with other
+      execution environments such as ATF.
+    oneOf:
+      - items:
+          - description: TX0 MU channel
+          - description: RX0 MU channel
+      - items:
+          - description: TX0 MU channel
+          - description: RX0 MU channel
+          - description: optional MU channel for general interrupt
+      - items:
+          - description: TX0 MU channel
+          - description: TX1 MU channel
+          - description: TX2 MU channel
+          - description: TX3 MU channel
+          - description: RX0 MU channel
+          - description: RX1 MU channel
+          - description: RX2 MU channel
+          - description: RX3 MU channel
+      - items:
+          - description: TX0 MU channel
+          - description: TX1 MU channel
+          - description: TX2 MU channel
+          - description: TX3 MU channel
+          - description: RX0 MU channel
+          - description: RX1 MU channel
+          - description: RX2 MU channel
+          - description: RX3 MU channel
+          - description: optional MU channel for general interrupt
+
+  mbox-names:
+    oneOf:
+      - items:
+          - const: tx0
+          - const: rx0
+      - items:
+          - const: tx0
+          - const: rx0
+          - const: gip3
+      - items:
+          - const: tx0
+          - const: tx1
+          - const: tx2
+          - const: tx3
+          - const: rx0
+          - const: rx1
+          - const: rx2
+          - const: rx3
+      - items:
+          - const: tx0
+          - const: tx1
+          - const: tx2
+          - const: tx3
+          - const: rx0
+          - const: rx1
+          - const: rx2
+          - const: rx3
+          - const: gip3
+
+  pinctrl:
+    description:
+      Pin controller provided by the SCU
+    $ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml
+
+  power-controller:
+    description:
+      Power domains controller node that provides the power domains
+      controlled by the SCU
+    $ref: /schemas/power/fsl,scu-pd.yaml
+
+  rtc:
+    description:
+      RTC controller provided by the SCU
+    $ref: /schemas/rtc/fsl,scu-rtc.yaml
+
+  thermal-sensor:
+    description:
+      Thermal sensor provided by the SCU
+    $ref: /schemas/thermal/fsl,scu-thermal.yaml
+
+  watchdog:
+    description:
+      Watchdog controller provided by the SCU
+    $ref: /schemas/watchdog/fsl,scu-wdt.yaml
+
+required:
+  - compatible
+  - mbox-names
+  - mboxes
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/firmware/imx/rsrc.h>
+    #include <dt-bindings/input/input.h>
+    #include <dt-bindings/pinctrl/pads-imx8qxp.h>
+
+    firmware {
+        system-controller {
+            compatible = "fsl,imx-scu";
+            mbox-names = "tx0", "tx1", "tx2", "tx3",
+                         "rx0", "rx1", "rx2", "rx3",
+                         "gip3";
+            mboxes = <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 &lsio_mu1 0 3
+                      &lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 &lsio_mu1 1 3
+                      &lsio_mu1 3 3>;
+
+            clock-controller {
+                compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
+                #clock-cells = <2>;
+            };
+
+            pinctrl {
+                compatible = "fsl,imx8qxp-iomuxc";
+
+                pinctrl_lpuart0: lpuart0grp {
+                    fsl,pins = <
+                        IMX8QXP_UART0_RX_ADMA_UART0_RX   0x06000020
+                        IMX8QXP_UART0_TX_ADMA_UART0_TX   0x06000020
+                    >;
+                };
+            };
+
+            ocotp {
+                compatible = "fsl,imx8qxp-scu-ocotp";
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                fec_mac0: mac@2c4 {
+                    reg = <0x2c4 6>;
+                };
+            };
+
+            power-controller {
+                compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
+                #power-domain-cells = <1>;
+            };
+
+            rtc {
+                compatible = "fsl,imx8qxp-sc-rtc";
+            };
+
+            keys {
+                compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
+                linux,keycodes = <KEY_POWER>;
+            };
+
+            watchdog {
+                compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
+                timeout-sec = <60>;
+            };
+
+            thermal-sensor {
+                compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
+                #thermal-sensor-cells = <1>;
+            };
+        };
+    };

Documentation/devicetree/bindings/firmware/qcom,scm.txt

@@ -23,10 +23,13 @@ Required properties:
  * "qcom,scm-msm8994"
  * "qcom,scm-msm8996"
  * "qcom,scm-msm8998"
+ * "qcom,scm-qcs404"
  * "qcom,scm-sc7180"
  * "qcom,scm-sc7280"
+ * "qcom,scm-sm6125"
  * "qcom,scm-sdm845"
  * "qcom,scm-sdx55"
+ * "qcom,scm-sdx65"
  * "qcom,scm-sm6350"
  * "qcom,scm-sm8150"
  * "qcom,scm-sm8250"
@@ -43,6 +46,7 @@ Required properties:
   clock and "bus" for the bus clock per the requirements of the compatible.
 - qcom,dload-mode: phandle to the TCSR hardware block and offset of the
 		   download mode control register (optional)
+- interconnects: Specifies the bandwidth requirements of the SCM interface (optional)
 
 Example for MSM8916:
 

Documentation/devicetree/bindings/gpio/gpio-zynq.yaml

@@ -11,7 +11,11 @@ maintainers:
 
 properties:
   compatible:
-    const: xlnx,zynq-gpio-1.0
+    enum:
+      - xlnx,zynq-gpio-1.0
+      - xlnx,zynqmp-gpio-1.0
+      - xlnx,versal-gpio-1.0
+      - xlnx,pmc-gpio-1.0
 
   reg:
     maxItems: 1
@@ -24,6 +28,11 @@ properties:
 
   gpio-controller: true
 
+  gpio-line-names:
+    description: strings describing the names of each gpio line
+    minItems: 58
+    maxItems: 174
+
   interrupt-controller: true
 
   "#interrupt-cells":
@@ -32,6 +41,54 @@ properties:
   clocks:
     maxItems: 1
 
+  power-domains:
+    maxItems: 1
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          enum:
+            - xlnx,zynqmp-gpio-1.0
+    then:
+      properties:
+        gpio-line-names:
+          minItems: 174
+          maxItems: 174
+
+  - if:
+      properties:
+        compatible:
+          enum:
+            - xlnx,zynq-gpio-1.0
+    then:
+      properties:
+        gpio-line-names:
+          minItems: 118
+          maxItems: 118
+
+  - if:
+      properties:
+        compatible:
+          enum:
+            - xlnx,versal-gpio-1.0
+    then:
+      properties:
+        gpio-line-names:
+          minItems: 58
+          maxItems: 58
+
+  - if:
+      properties:
+        compatible:
+          enum:
+            - xlnx,pmc-gpio-1.0
+    then:
+      properties:
+        gpio-line-names:
+          minItems: 116
+          maxItems: 116
+
 required:
   - compatible
   - reg

Documentation/devicetree/bindings/hwinfo/renesas,prr.yaml

@@ -1,7 +1,7 @@
-# SPDX-License-Identifier: GPL-2.0
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/arm/renesas,prr.yaml#
+$id: http://devicetree.org/schemas/hwinfo/renesas,prr.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Renesas Product Register

Documentation/devicetree/bindings/hwmon/national,lm90.yaml

@@ -16,6 +16,7 @@ properties:
       - adi,adm1032
       - adi,adt7461
       - adi,adt7461a
+      - adi,adt7481
       - dallas,max6646
       - dallas,max6647
       - dallas,max6649
@@ -50,6 +51,12 @@ properties:
   "#thermal-sensor-cells":
     const: 1
 
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 0
+
   vcc-supply:
     description: phandle to the regulator that provides the +VCC supply
 
@@ -61,6 +68,29 @@ required:
   - compatible
   - reg
 
+patternProperties:
+  "^channel@([0-2])$":
+    type: object
+    description: Represents channels of the device and their specific configuration.
+
+    properties:
+      reg:
+        description: The channel number. 0 is local channel, 1-2 are remote channels.
+        items:
+          minimum: 0
+          maximum: 2
+
+      label:
+        description: A descriptive name for this channel, like "ambient" or "psu".
+
+      temperature-offset-millicelsius:
+        description: Temperature offset to be added to or subtracted from remote temperature measurements.
+
+    required:
+      - reg
+
+    additionalProperties: false
+
 allOf:
   - if:
       not:
@@ -70,12 +100,84 @@ allOf:
               enum:
                 - adi,adt7461
                 - adi,adt7461a
+                - adi,adt7481
                 - ti,tmp451
                 - ti,tmp461
     then:
       properties:
         ti,extended-range-enable: false
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - dallas,max6646
+              - dallas,max6647
+              - dallas,max6649
+              - dallas,max6657
+              - dallas,max6658
+              - dallas,max6659
+              - dallas,max6695
+              - dallas,max6696
+    then:
+      patternProperties:
+        "^channel@([0-2])$":
+          properties:
+            temperature-offset-millicelsius: false
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - adi,adt7461
+              - adi,adt7461a
+              - adi,adt7481
+              - onnn,nct1008
+    then:
+      patternProperties:
+        "^channel@([0-2])$":
+          properties:
+            temperature-offset-millicelsius:
+              maximum: 127750
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - adi,adm1032
+              - dallas,max6680
+              - dallas,max6681
+              - gmt,g781
+              - national,lm86
+              - national,lm89
+              - national,lm90
+              - national,lm99
+              - nxp,sa56004
+              - winbond,w83l771
+    then:
+      patternProperties:
+        "^channel@([0-2])$":
+          properties:
+            temperature-offset-millicelsius:
+              maximum: 127875
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - ti,tmp451
+              - ti,tmp461
+    then:
+      patternProperties:
+        "^channel@([0-2])$":
+          properties:
+            temperature-offset-millicelsius:
+              maximum: 127937
+
 additionalProperties: false
 
 examples:
@@ -94,3 +196,32 @@ examples:
             #thermal-sensor-cells = <1>;
         };
     };
+  - |
+    i2c {
+      #address-cells = <1>;
+      #size-cells = <0>;
+
+      sensor@4c {
+        compatible = "adi,adt7481";
+        reg = <0x4c>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        channel@0 {
+          reg = <0x0>;
+          label = "local";
+        };
+
+        channel@1 {
+          reg = <0x1>;
+          label = "front";
+          temperature-offset-millicelsius = <4000>;
+        };
+
+        channel@2 {
+          reg = <0x2>;
+          label = "back";
+          temperature-offset-millicelsius = <750>;
+        };
+      };
+    };

Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml

@@ -21,10 +21,18 @@ properties:
           - enum:
               - allwinner,sun8i-a23-i2c
               - allwinner,sun8i-a83t-i2c
+              - allwinner,sun8i-v536-i2c
               - allwinner,sun50i-a64-i2c
-              - allwinner,sun50i-a100-i2c
               - allwinner,sun50i-h6-i2c
+          - const: allwinner,sun6i-a31-i2c
+      - description: Allwinner SoCs with offload support
+        items:
+          - enum:
+              - allwinner,sun20i-d1-i2c
+              - allwinner,sun50i-a100-i2c
               - allwinner,sun50i-h616-i2c
+              - allwinner,sun50i-r329-i2c
+          - const: allwinner,sun8i-v536-i2c
           - const: allwinner,sun6i-a31-i2c
       - const: marvell,mv64xxx-i2c
       - const: marvell,mv78230-i2c

Documentation/devicetree/bindings/input/da9062-onkey.txt

@@ -2,7 +2,7 @@
 
 This module is part of the DA9061/DA9062/DA9063. For more details about entire
 DA9062 and DA9061 chips see Documentation/devicetree/bindings/mfd/da9062.txt
-For DA9063 see Documentation/devicetree/bindings/mfd/da9063.txt
+For DA9063 see Documentation/devicetree/bindings/mfd/dlg,da9063.yaml
 
 This module provides the KEY_POWER event.
 

Documentation/devicetree/bindings/input/fsl,scu-key.yaml

@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/fsl,scu-key.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX SCU Client Device Node - SCU key bindings based on SCU Message Protocol
+
+maintainers:
+  - Dong Aisheng <aisheng.dong@nxp.com>
+
+description: i.MX SCU Client Device Node
+  Client nodes are maintained as children of the relevant IMX-SCU device node.
+
+allOf:
+  - $ref: input.yaml#
+
+properties:
+  compatible:
+    items:
+      - const: fsl,imx8qxp-sc-key
+      - const: fsl,imx-sc-key
+
+  linux,keycodes:
+    maxItems: 1
+
+required:
+  - compatible
+  - linux,keycodes
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/input/input.h>
+
+    keys {
+        compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
+        linux,keycodes = <KEY_POWER>;
+    };

Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml

@@ -0,0 +1,141 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
+
+maintainers:
+  - Jia-Wei Chang <jia-wei.chang@mediatek.com>
+  - Johnson Wang <johnson.wang@mediatek.com>
+
+description: |
+  MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by
+  MT8183 and MT8186 SoCs to scale the frequency and adjust the voltage in
+  hardware. It can also optimize the voltage to reduce the power consumption.
+
+properties:
+  compatible:
+    enum:
+      - mediatek,mt8183-cci
+      - mediatek,mt8186-cci
+
+  clocks:
+    items:
+      - description:
+          The multiplexer for clock input of the bus.
+      - description:
+          A parent of "bus" clock which is used as an intermediate clock source
+          when the original clock source (PLL) is under transition and not
+          stable yet.
+
+  clock-names:
+    items:
+      - const: cci
+      - const: intermediate
+
+  operating-points-v2: true
+  opp-table: true
+
+  proc-supply:
+    description:
+      Phandle of the regulator for CCI that provides the supply voltage.
+
+  sram-supply:
+    description:
+      Phandle of the regulator for sram of CCI that provides the supply
+      voltage. When it is present, the implementation needs to do
+      "voltage tracking" to step by step scale up/down Vproc and Vsram to fit
+      SoC specific needs. When absent, the voltage scaling flow is handled by
+      hardware, hence no software "voltage tracking" is needed.
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - operating-points-v2
+  - proc-supply
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mt8183-clk.h>
+    cci: cci {
+        compatible = "mediatek,mt8183-cci";
+        clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+                 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+        clock-names = "cci", "intermediate";
+        operating-points-v2 = <&cci_opp>;
+        proc-supply = <&mt6358_vproc12_reg>;
+    };
+
+    cci_opp: opp-table-cci {
+        compatible = "operating-points-v2";
+        opp-shared;
+        opp2_00: opp-273000000 {
+            opp-hz = /bits/ 64 <273000000>;
+            opp-microvolt = <650000>;
+        };
+        opp2_01: opp-338000000 {
+            opp-hz = /bits/ 64 <338000000>;
+            opp-microvolt = <687500>;
+        };
+        opp2_02: opp-403000000 {
+            opp-hz = /bits/ 64 <403000000>;
+            opp-microvolt = <718750>;
+        };
+        opp2_03: opp-463000000 {
+            opp-hz = /bits/ 64 <463000000>;
+            opp-microvolt = <756250>;
+        };
+        opp2_04: opp-546000000 {
+            opp-hz = /bits/ 64 <546000000>;
+            opp-microvolt = <800000>;
+        };
+        opp2_05: opp-624000000 {
+            opp-hz = /bits/ 64 <624000000>;
+            opp-microvolt = <818750>;
+        };
+        opp2_06: opp-689000000 {
+            opp-hz = /bits/ 64 <689000000>;
+            opp-microvolt = <850000>;
+        };
+        opp2_07: opp-767000000 {
+            opp-hz = /bits/ 64 <767000000>;
+            opp-microvolt = <868750>;
+        };
+        opp2_08: opp-845000000 {
+            opp-hz = /bits/ 64 <845000000>;
+            opp-microvolt = <893750>;
+        };
+        opp2_09: opp-871000000 {
+            opp-hz = /bits/ 64 <871000000>;
+            opp-microvolt = <906250>;
+        };
+        opp2_10: opp-923000000 {
+            opp-hz = /bits/ 64 <923000000>;
+            opp-microvolt = <931250>;
+        };
+        opp2_11: opp-962000000 {
+            opp-hz = /bits/ 64 <962000000>;
+            opp-microvolt = <943750>;
+        };
+        opp2_12: opp-1027000000 {
+            opp-hz = /bits/ 64 <1027000000>;
+            opp-microvolt = <975000>;
+        };
+        opp2_13: opp-1092000000 {
+            opp-hz = /bits/ 64 <1092000000>;
+            opp-microvolt = <1000000>;
+        };
+        opp2_14: opp-1144000000 {
+            opp-hz = /bits/ 64 <1144000000>;
+            opp-microvolt = <1025000>;
+        };
+        opp2_15: opp-1196000000 {
+            opp-hz = /bits/ 64 <1196000000>;
+            opp-microvolt = <1050000>;
+        };
+    };

Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml

@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,msm8998-bwmon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Interconnect Bandwidth Monitor
+
+maintainers:
+  - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+description: |
+  Bandwidth Monitor measures current throughput on buses between various NoC
+  fabrics and provides information when it crosses configured thresholds.
+
+  Certain SoCs might have more than one Bandwidth Monitors, for example on SDM845::
+   - Measuring the bandwidth between CPUs and Last Level Cache Controller -
+     called just BWMON,
+   - Measuring the bandwidth between Last Level Cache Controller and memory
+     (DDR) - called LLCC BWMON.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - qcom,sdm845-bwmon
+          - const: qcom,msm8998-bwmon
+      - const: qcom,msm8998-bwmon       # BWMON v4
+
+  interconnects:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  operating-points-v2: true
+  opp-table: true
+
+  reg:
+    # BWMON v4 (currently described) and BWMON v5 use one register address
+    # space.  BWMON v2 uses two register spaces - not yet described.
+    maxItems: 1
+
+required:
+  - compatible
+  - interconnects
+  - interrupts
+  - operating-points-v2
+  - opp-table
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interconnect/qcom,sdm845.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    pmu@1436400 {
+        compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon";
+        reg = <0x01436400 0x600>;
+        interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+        interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
+
+        operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+        cpu_bwmon_opp_table: opp-table {
+            compatible = "operating-points-v2";
+            opp-0 {
+                opp-peak-kBps = <4800000>;
+            };
+            opp-1 {
+                opp-peak-kBps = <9216000>;
+            };
+            opp-2 {
+                opp-peak-kBps = <15052800>;
+            };
+            opp-3 {
+                opp-peak-kBps = <20889600>;
+            };
+            opp-4 {
+                opp-peak-kBps = <25497600>;
+            };
+        };
+    };

Documentation/devicetree/bindings/interconnect/samsung,exynos-bus.yaml

@@ -0,0 +1,290 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos SoC Bus and Interconnect
+
+maintainers:
+  - Chanwoo Choi <cw00.choi@samsung.com>
+  - Krzysztof Kozlowski <krzk@kernel.org>
+
+description: |
+  The Samsung Exynos SoC has many buses for data transfer between DRAM and
+  sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
+  Generally, each bus of Exynos SoC includes a source clock and a power line,
+  which are able to change the clock frequency of the bus in runtime. To
+  monitor the usage of each bus in runtime, the driver uses the PPMU (Platform
+  Performance Monitoring Unit), which is able to measure the current load of
+  sub-blocks.
+
+  The Exynos SoC includes the various sub-blocks which have the each AXI bus.
+  The each AXI bus has the owned source clock but, has not the only owned power
+  line. The power line might be shared among one more sub-blocks.  So, we can
+  divide into two type of device as the role of each sub-block.  There are two
+  type of bus devices as following::
+   - parent bus device
+   - passive bus device
+
+  Basically, parent and passive bus device share the same power line.  The
+  parent bus device can only change the voltage of shared power line and the
+  rest bus devices (passive bus device) depend on the decision of the parent
+  bus device. If there are three blocks which share the VDD_xxx power line,
+  Only one block should be parent device and then the rest blocks should depend
+  on the parent device as passive device.
+
+    VDD_xxx |--- A block (parent)
+      |--- B block (passive)
+      |--- C block (passive)
+
+  There are a little different composition among Exynos SoC because each Exynos
+  SoC has different sub-blocks. Therefore, such difference should be specified
+  in devicetree file instead of each device driver. In result, this driver is
+  able to support the bus frequency for all Exynos SoCs.
+
+  Detailed correlation between sub-blocks and power line according
+  to Exynos SoC::
+   - In case of Exynos3250, there are two power line as following::
+     VDD_MIF |--- DMC (Dynamic Memory Controller)
+
+     VDD_INT |--- LEFTBUS (parent device)
+       |--- PERIL
+       |--- MFC
+       |--- G3D
+       |--- RIGHTBUS
+       |--- PERIR
+       |--- FSYS
+       |--- LCD0
+       |--- PERIR
+       |--- ISP
+       |--- CAM
+
+     - MIF bus's frequency/voltage table
+       -----------------------
+       |Lv| Freq   | Voltage |
+       -----------------------
+       |L1| 50000  |800000   |
+       |L2| 100000 |800000   |
+       |L3| 134000 |800000   |
+       |L4| 200000 |825000   |
+       |L5| 400000 |875000   |
+       -----------------------
+
+     - INT bus's frequency/voltage table
+       ----------------------------------------------------------
+       |Block|LEFTBUS|RIGHTBUS|MCUISP |ISP    |PERIL  ||VDD_INT |
+       | name|       |LCD0    |       |       |       ||        |
+       |     |       |FSYS    |       |       |       ||        |
+       |     |       |MFC     |       |       |       ||        |
+       ----------------------------------------------------------
+       |Mode |*parent|passive |passive|passive|passive||        |
+       ----------------------------------------------------------
+       |Lv   |Frequency                               ||Voltage |
+       ----------------------------------------------------------
+       |L1   |50000  |50000   |50000  |50000  |50000  ||900000  |
+       |L2   |80000  |80000   |80000  |80000  |80000  ||900000  |
+       |L3   |100000 |100000  |100000 |100000 |100000 ||1000000 |
+       |L4   |134000 |134000  |200000 |200000 |       ||1000000 |
+       |L5   |200000 |200000  |400000 |300000 |       ||1000000 |
+       ----------------------------------------------------------
+
+   - In case of Exynos4210, there is one power line as following::
+     VDD_INT |--- DMC (parent device, Dynamic Memory Controller)
+       |--- LEFTBUS
+       |--- PERIL
+       |--- MFC(L)
+       |--- G3D
+       |--- TV
+       |--- LCD0
+       |--- RIGHTBUS
+       |--- PERIR
+       |--- MFC(R)
+       |--- CAM
+       |--- FSYS
+       |--- GPS
+       |--- LCD0
+       |--- LCD1
+
+   - In case of Exynos4x12, there are two power line as following::
+     VDD_MIF |--- DMC (Dynamic Memory Controller)
+
+     VDD_INT |--- LEFTBUS (parent device)
+       |--- PERIL
+       |--- MFC(L)
+       |--- G3D
+       |--- TV
+       |--- IMAGE
+       |--- RIGHTBUS
+       |--- PERIR
+       |--- MFC(R)
+       |--- CAM
+       |--- FSYS
+       |--- GPS
+       |--- LCD0
+       |--- ISP
+
+   - In case of Exynos5422, there are two power line as following::
+     VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
+             |--- DREX 1
+
+     VDD_INT |--- NoC_Core (parent device)
+       |--- G2D
+       |--- G3D
+       |--- DISP1
+       |--- NoC_WCORE
+       |--- GSCL
+       |--- MSCL
+       |--- ISP
+       |--- MFC
+       |--- GEN
+       |--- PERIS
+       |--- PERIC
+       |--- FSYS
+       |--- FSYS2
+
+   - In case of Exynos5433, there is VDD_INT power line as following::
+     VDD_INT |--- G2D (parent device)
+       |--- MSCL
+       |--- GSCL
+       |--- JPEG
+       |--- MFC
+       |--- HEVC
+       |--- BUS0
+       |--- BUS1
+       |--- BUS2
+       |--- PERIS (Fixed clock rate)
+       |--- PERIC (Fixed clock rate)
+       |--- FSYS  (Fixed clock rate)
+
+properties:
+  compatible:
+    enum:
+      - samsung,exynos-bus
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: bus
+
+  devfreq:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Parent bus device. Valid and required only for the passive bus devices.
+
+  devfreq-events:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    minItems: 1
+    maxItems: 4
+    description:
+      Devfreq-event device to monitor the current utilization of buses. Valid
+      and required only for the parent bus devices.
+
+  exynos,saturation-ratio:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Percentage value which is used to calibrate the performance count against
+      total cycle count.  Valid only for the parent bus devices.
+
+  '#interconnect-cells':
+    const: 0
+
+  interconnects:
+    minItems: 1
+    maxItems: 2
+
+  operating-points-v2: true
+
+  samsung,data-clock-ratio:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    default: 8
+    description:
+      Ratio of the data throughput in B/s to minimum data clock frequency in
+      Hz.
+
+  vdd-supply:
+    description:
+      Main bus power rail. Valid and required only for the parent bus devices.
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - operating-points-v2
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/exynos3250.h>
+
+    bus-dmc {
+        compatible = "samsung,exynos-bus";
+        clocks = <&cmu_dmc CLK_DIV_DMC>;
+        clock-names = "bus";
+        operating-points-v2 = <&bus_dmc_opp_table>;
+        devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+        vdd-supply = <&buck1_reg>;
+    };
+
+    ppmu_dmc0: ppmu@106a0000 {
+        compatible = "samsung,exynos-ppmu";
+        reg = <0x106a0000 0x2000>;
+        events {
+            ppmu_dmc0_3: ppmu-event3-dmc0 {
+                event-name = "ppmu-event3-dmc0";
+            };
+        };
+    };
+
+    bus_leftbus: bus-leftbus {
+        compatible = "samsung,exynos-bus";
+        clocks = <&cmu CLK_DIV_GDL>;
+        clock-names = "bus";
+        operating-points-v2 = <&bus_leftbus_opp_table>;
+        devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+        vdd-supply = <&buck3_reg>;
+    };
+
+    bus-rightbus {
+        compatible = "samsung,exynos-bus";
+        clocks = <&cmu CLK_DIV_GDR>;
+        clock-names = "bus";
+        operating-points-v2 = <&bus_leftbus_opp_table>;
+        devfreq = <&bus_leftbus>;
+    };
+
+  - |
+    dmc: bus-dmc {
+        compatible = "samsung,exynos-bus";
+        clocks = <&clock CLK_DIV_DMC>;
+        clock-names = "bus";
+        operating-points-v2 = <&bus_dmc_opp_table>;
+        samsung,data-clock-ratio = <4>;
+        #interconnect-cells = <0>;
+        devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
+        vdd-supply = <&buck1_reg>;
+    };
+
+    leftbus: bus-leftbus {
+        compatible = "samsung,exynos-bus";
+        clocks = <&clock CLK_DIV_GDL>;
+        clock-names = "bus";
+        operating-points-v2 = <&bus_leftbus_opp_table>;
+        interconnects = <&dmc>;
+        #interconnect-cells = <0>;
+        devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
+        vdd-supply = <&buck3_reg>;
+    };
+
+    display: bus-display {
+        compatible = "samsung,exynos-bus";
+        clocks = <&clock CLK_DIV_ACLK_266>;
+        clock-names = "bus";
+        operating-points-v2 = <&bus_display_opp_table>;
+        interconnects = <&leftbus &dmc>;
+        #interconnect-cells = <0>;
+        devfreq = <&leftbus>;
+    };

Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml

@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
+
+maintainers:
+  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+  - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description: |
+  IA55 performs various interrupt controls including synchronization for the external
+  interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral
+  interrupts output by each IP. And it notifies the interrupt to the GIC
+    - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
+    - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
+    - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
+      stand-up edge detection interrupts)
+
+allOf:
+  - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - renesas,r9a07g044-irqc    # RZ/G2{L,LC}
+          - renesas,r9a07g054-irqc    # RZ/V2L
+      - const: renesas,rzg2l-irqc
+
+  '#interrupt-cells':
+    description: The first cell should contain external interrupt number (IRQ0-7) and the
+                 second cell is used to specify the flag.
+    const: 2
+
+  '#address-cells':
+    const: 0
+
+  interrupt-controller: true
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 41
+
+  clocks:
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: clk
+      - const: pclk
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+required:
+  - compatible
+  - '#interrupt-cells'
+  - '#address-cells'
+  - interrupt-controller
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - power-domains
+  - resets
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/r9a07g044-cpg.h>
+
+    irqc: interrupt-controller@110a0000 {
+            compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
+            reg = <0x110a0000 0x10000>;
+            #interrupt-cells = <2>;
+            #address-cells = <0>;
+            interrupt-controller;
+            interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
+            clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
+                     <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
+            clock-names = "clk", "pclk";
+            power-domains = <&cpg>;
+            resets = <&cpg R9A07G044_IA55_RESETN>;
+    };

Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

@@ -26,9 +26,14 @@ description:
   with priority below this threshold will not cause the PLIC to raise its
   interrupt line leading to the context.
 
-  While the PLIC supports both edge-triggered and level-triggered interrupts,
-  interrupt handlers are oblivious to this distinction and therefore it is not
-  specified in the PLIC device-tree binding.
+  The PLIC supports both edge-triggered and level-triggered interrupts. For
+  edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
+  seen while an interrupt handler is active; the PLIC may either queue them or
+  ignore them. In the first case, handlers are oblivious to the trigger type, so
+  it is not included in the interrupt specifier. In the second case, software
+  needs to know the trigger type, so it can reorder the interrupt flow to avoid
+  missing interrupts. This special handling is needed by at least the Renesas
+  RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
 
   While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
   "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
@@ -47,6 +52,10 @@ maintainers:
 properties:
   compatible:
     oneOf:
+      - items:
+          - enum:
+              - renesas,r9a07g043-plic
+          - const: andestech,nceplic100
       - items:
           - enum:
               - sifive,fu540-c000-plic
@@ -64,8 +73,7 @@ properties:
   '#address-cells':
     const: 0
 
-  '#interrupt-cells':
-    const: 1
+  '#interrupt-cells': true
 
   interrupt-controller: true
 
@@ -82,6 +90,12 @@ properties:
     description:
       Specifies how many external interrupts are supported by this controller.
 
+  clocks: true
+
+  power-domains: true
+
+  resets: true
+
 required:
   - compatible
   - '#address-cells'
@@ -91,6 +105,47 @@ required:
   - interrupts-extended
   - riscv,ndev
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - andestech,nceplic100
+              - thead,c900-plic
+
+    then:
+      properties:
+        '#interrupt-cells':
+          const: 2
+
+    else:
+      properties:
+        '#interrupt-cells':
+          const: 1
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: renesas,r9a07g043-plic
+
+    then:
+      properties:
+        clocks:
+          maxItems: 1
+
+        power-domains:
+          maxItems: 1
+
+        resets:
+          maxItems: 1
+
+      required:
+        - clocks
+        - power-domains
+        - resets
+
 additionalProperties: false
 
 examples:

Documentation/devicetree/bindings/interrupt-controller/sunplus,sp7021-intc.yaml

@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) Sunplus Co., Ltd. 2021
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/sunplus,sp7021-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sunplus SP7021 SoC Interrupt Controller
+
+maintainers:
+  - Qin Jian <qinjian@cqplus1.com>
+
+properties:
+  compatible:
+    items:
+      - const: sunplus,sp7021-intc
+
+  reg:
+    maxItems: 2
+    description:
+      Specifies base physical address(s) and size of the controller regs.
+      The 1st region include type/polarity/priority/mask regs.
+      The 2nd region include clear/masked_ext0/masked_ext1/group regs.
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 2
+    description:
+      The first cell is the IRQ number, the second cell is the trigger
+      type as defined in interrupt.txt in this directory.
+
+  interrupts:
+    maxItems: 2
+    description:
+      EXT_INT0 & EXT_INT1, 2 interrupts references to primary interrupt
+      controller.
+
+required:
+  - compatible
+  - reg
+  - interrupt-controller
+  - "#interrupt-cells"
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    intc: interrupt-controller@9c000780 {
+        compatible = "sunplus,sp7021-intc";
+        reg = <0x9c000780 0x80>, <0x9c000a80 0x80>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        interrupt-parent = <&gic>;
+        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, /* EXT_INT0 */
+                     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; /* EXT_INT1 */
+    };
+
+...

Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml

@@ -32,6 +32,7 @@ properties:
           - mediatek,mt2701-smi-common
           - mediatek,mt2712-smi-common
           - mediatek,mt6779-smi-common
+          - mediatek,mt6795-smi-common
           - mediatek,mt8167-smi-common
           - mediatek,mt8173-smi-common
           - mediatek,mt8183-smi-common

Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml

@@ -20,6 +20,7 @@ properties:
           - mediatek,mt2701-smi-larb
           - mediatek,mt2712-smi-larb
           - mediatek,mt6779-smi-larb
+          - mediatek,mt6795-smi-larb
           - mediatek,mt8167-smi-larb
           - mediatek,mt8173-smi-larb
           - mediatek,mt8183-smi-larb

Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml

@@ -22,6 +22,7 @@ properties:
           - enum:
               - allwinner,sun20i-d1-emac
               - allwinner,sun50i-h6-emac
+              - allwinner,sun50i-h616-emac0
           - const: allwinner,sun50i-a64-emac
 
   reg:

Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml

@@ -0,0 +1,171 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/pcs/renesas,rzn1-miic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/N1 MII converter
+
+maintainers:
+  - Clément Léger <clement.leger@bootlin.com>
+
+description: |
+  This MII converter is present on the Renesas RZ/N1 SoC family. It is
+  responsible to do MII passthrough or convert it to RMII/RGMII.
+
+properties:
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 0
+
+  compatible:
+    items:
+      - enum:
+          - renesas,r9a06g032-miic
+      - const: renesas,rzn1-miic
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: MII reference clock
+      - description: RGMII reference clock
+      - description: RMII reference clock
+      - description: AHB clock used for the MII converter register interface
+
+  clock-names:
+    items:
+      - const: mii_ref
+      - const: rgmii_ref
+      - const: rmii_ref
+      - const: hclk
+
+  renesas,miic-switch-portin:
+    description: MII Switch PORTIN configuration. This value should use one of
+      the values defined in dt-bindings/net/pcs-rzn1-miic.h.
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [1, 2]
+
+  power-domains:
+    maxItems: 1
+
+patternProperties:
+  "^mii-conv@[0-5]$":
+    type: object
+    description: MII converter port
+
+    properties:
+      reg:
+        description: MII Converter port number.
+        enum: [1, 2, 3, 4, 5]
+
+      renesas,miic-input:
+        description: Converter input port configuration. This value should use
+          one of the values defined in dt-bindings/net/pcs-rzn1-miic.h.
+        $ref: /schemas/types.yaml#/definitions/uint32
+
+    required:
+      - reg
+      - renesas,miic-input
+
+    additionalProperties: false
+
+    allOf:
+      - if:
+          properties:
+            reg:
+              const: 1
+        then:
+          properties:
+            renesas,miic-input:
+              const: 0
+      - if:
+          properties:
+            reg:
+              const: 2
+        then:
+          properties:
+            renesas,miic-input:
+              enum: [1, 11]
+      - if:
+          properties:
+            reg:
+              const: 3
+        then:
+          properties:
+            renesas,miic-input:
+              enum: [7, 10]
+      - if:
+          properties:
+            reg:
+              const: 4
+        then:
+          properties:
+            renesas,miic-input:
+              enum: [4, 6, 9, 13]
+      - if:
+          properties:
+            reg:
+              const: 5
+        then:
+          properties:
+            renesas,miic-input:
+              enum: [3, 5, 8, 12]
+
+required:
+  - '#address-cells'
+  - '#size-cells'
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - power-domains
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/net/pcs-rzn1-miic.h>
+    #include <dt-bindings/clock/r9a06g032-sysctrl.h>
+
+    eth-miic@44030000 {
+      #address-cells = <1>;
+      #size-cells = <0>;
+      compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic";
+      reg = <0x44030000 0x10000>;
+      clocks = <&sysctrl R9A06G032_CLK_MII_REF>,
+              <&sysctrl R9A06G032_CLK_RGMII_REF>,
+              <&sysctrl R9A06G032_CLK_RMII_REF>,
+              <&sysctrl R9A06G032_HCLK_SWITCH_RG>;
+      clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk";
+      renesas,miic-switch-portin = <MIIC_GMAC2_PORT>;
+      power-domains = <&sysctrl>;
+
+      mii_conv1: mii-conv@1 {
+        renesas,miic-input = <MIIC_GMAC1_PORT>;
+        reg = <1>;
+      };
+
+      mii_conv2: mii-conv@2 {
+        renesas,miic-input = <MIIC_SWITCH_PORTD>;
+        reg = <2>;
+      };
+
+      mii_conv3: mii-conv@3 {
+        renesas,miic-input = <MIIC_SWITCH_PORTC>;
+        reg = <3>;
+      };
+
+      mii_conv4: mii-conv@4 {
+        renesas,miic-input = <MIIC_SWITCH_PORTB>;
+        reg = <4>;
+      };
+
+      mii_conv5: mii-conv@5 {
+        renesas,miic-input = <MIIC_SWITCH_PORTA>;
+        reg = <5>;
+      };
+    };

Documentation/devicetree/bindings/nvmem/fsl,scu-ocotp.yaml

@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/fsl,scu-ocotp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX SCU Client Device Node - OCOTP bindings based on SCU Message Protocol
+
+maintainers:
+  - Dong Aisheng <aisheng.dong@nxp.com>
+
+description: i.MX SCU Client Device Node
+  Client nodes are maintained as children of the relevant IMX-SCU device node.
+
+allOf:
+  - $ref: nvmem.yaml#
+
+properties:
+  compatible:
+    enum:
+      - fsl,imx8qm-scu-ocotp
+      - fsl,imx8qxp-scu-ocotp
+
+patternProperties:
+  '^mac@[0-9a-f]*$':
+    type: object
+    description:
+      MAC address.
+
+    properties:
+      reg:
+        description:
+          Byte offset within OCOTP where the MAC address is stored
+        maxItems: 1
+
+    required:
+      - reg
+
+    additionalProperties: false
+
+required:
+  - compatible
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    ocotp {
+        compatible = "fsl,imx8qxp-scu-ocotp";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        fec_mac0: mac@2c4 {
+            reg = <0x2c4 6>;
+        };
+    };

Documentation/devicetree/bindings/pci/mediatek-pcie.txt

@@ -7,6 +7,7 @@ Required properties:
 	"mediatek,mt7622-pcie"
 	"mediatek,mt7623-pcie"
 	"mediatek,mt7629-pcie"
+	"airoha,en7523-pcie"
 - device_type: Must be "pci"
 - reg: Base addresses and lengths of the root ports.
 - reg-names: Names of the above areas to use during resource lookup.

Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie-ep.yaml

@@ -0,0 +1,319 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based)
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+  - Vidya Sagar <vidyas@nvidia.com>
+
+description: |
+  This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
+  inherits all the common properties defined in snps,dw-pcie-ep.yaml.  Some
+  of the controller instances are dual mode; they can work either in Root
+  Port mode or Endpoint mode but one at a time.
+
+  On Tegra194, controllers C0, C4 and C5 support Endpoint mode.
+  On Tegra234, controllers C5, C6, C7 and C10 support Endpoint mode.
+
+  Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
+  operate in the Endpoint mode because of the way the platform is designed.
+
+properties:
+  compatible:
+    enum:
+      - nvidia,tegra194-pcie-ep
+      - nvidia,tegra234-pcie-ep
+
+  reg:
+    items:
+      - description: controller's application logic registers
+      - description: iATU and DMA registers. This is where the iATU (internal
+          Address Translation Unit) registers of the PCIe core are made
+          available for software access.
+      - description: aperture where the Root Port's own configuration
+          registers are available.
+      - description: aperture used to map the remote Root Complex address space
+
+  reg-names:
+    items:
+      - const: appl
+      - const: atu_dma
+      - const: dbi
+      - const: addr_space
+
+  interrupts:
+    items:
+      - description: controller interrupt
+
+  interrupt-names:
+    items:
+      - const: intr
+
+  clocks:
+    items:
+      - description: module clock
+
+  clock-names:
+    items:
+      - const: core
+
+  resets:
+    items:
+      - description: APB bus interface reset
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: apb
+      - const: core
+
+  reset-gpios:
+    description: Must contain a phandle to a GPIO controller followed by GPIO
+      that is being used as PERST input signal. Please refer to pci.txt.
+
+  phys:
+    minItems: 1
+    maxItems: 8
+
+  phy-names:
+    minItems: 1
+    items:
+      - const: p2u-0
+      - const: p2u-1
+      - const: p2u-2
+      - const: p2u-3
+      - const: p2u-4
+      - const: p2u-5
+      - const: p2u-6
+      - const: p2u-7
+
+  power-domains:
+    maxItems: 1
+    description: |
+      A phandle to the node that controls power to the respective PCIe
+      controller and a specifier name for the PCIe controller.
+
+      Tegra194 specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h"
+      Tegra234 specifiers are defined in "include/dt-bindings/power/tegra234-powergate.h"
+
+  interconnects:
+    items:
+      - description: memory read client
+      - description: memory write client
+
+  interconnect-names:
+    items:
+      - const: dma-mem # read
+      - const: write
+
+  dma-coherent: true
+
+  nvidia,bpmp:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description: |
+      Must contain a pair of phandles to BPMP controller node followed by
+      controller ID. Following are the controller IDs for each controller:
+
+      Tegra194
+
+        0: C0
+        1: C1
+        2: C2
+        3: C3
+        4: C4
+        5: C5
+
+      Tegra234
+
+        0 : C0
+        1 : C1
+        2 : C2
+        3 : C3
+        4 : C4
+        5 : C5
+        6 : C6
+        7 : C7
+        8 : C8
+        9 : C9
+        10: C10
+
+    items:
+      - items:
+          - description: phandle to BPMP controller node
+          - description: PCIe controller ID
+            maximum: 10
+
+  nvidia,aspm-cmrt-us:
+    description: Common Mode Restore Time for proper operation of ASPM to be
+      specified in microseconds
+
+  nvidia,aspm-pwr-on-t-us:
+    description: Power On time for proper operation of ASPM to be specified in
+      microseconds
+
+  nvidia,aspm-l0s-entrance-latency-us:
+    description: ASPM L0s entrance latency to be specified in microseconds
+
+  vddio-pex-ctl-supply:
+    description: A phandle to the regulator supply for PCIe side band signals
+
+  nvidia,refclk-select-gpios:
+    maxItems: 1
+    description: GPIO used to enable REFCLK to controller from the host
+
+  nvidia,enable-ext-refclk:
+    description: |
+      This boolean property needs to be present if the controller is configured
+      to receive Reference Clock from the host.
+      NOTE: This is applicable only for Tegra234.
+
+    $ref: /schemas/types.yaml#/definitions/flag
+
+  nvidia,enable-srns:
+    description: |
+      This boolean property needs to be present if the controller is
+      configured to operate in SRNS (Separate Reference Clocks with No
+      Spread-Spectrum Clocking).  NOTE: This is applicable only for
+      Tegra234.
+
+    $ref: /schemas/types.yaml#/definitions/flag
+
+allOf:
+  - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
+
+unevaluatedProperties: false
+
+required:
+  - interrupts
+  - interrupt-names
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - power-domains
+  - reset-gpios
+  - vddio-pex-ctl-supply
+  - num-lanes
+  - phys
+  - phy-names
+  - nvidia,bpmp
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra194-clock.h>
+    #include <dt-bindings/gpio/tegra194-gpio.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/tegra194-powergate.h>
+    #include <dt-bindings/reset/tegra194-reset.h>
+
+    bus@0 {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges = <0x0 0x0 0x0 0x8 0x0>;
+
+        pcie-ep@141a0000 {
+            compatible = "nvidia,tegra194-pcie-ep";
+            reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
+                  <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
+                  <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
+                  <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */
+            reg-names = "appl", "atu_dma", "dbi", "addr_space";
+            interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+            interrupt-names = "intr";
+
+            clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
+            clock-names = "core";
+
+            resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
+                     <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
+            reset-names = "apb", "core";
+
+            power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
+            pinctrl-names = "default";
+            pinctrl-0 = <&clkreq_c5_bi_dir_state>;
+
+            nvidia,bpmp = <&bpmp 5>;
+
+            nvidia,aspm-cmrt-us = <60>;
+            nvidia,aspm-pwr-on-t-us = <20>;
+            nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+            vddio-pex-ctl-supply = <&vdd_1v8ao>;
+
+            reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
+
+            nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
+                                          GPIO_ACTIVE_HIGH>;
+
+            num-lanes = <8>;
+
+            phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
+                   <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
+                   <&p2u_nvhs_6>, <&p2u_nvhs_7>;
+
+            phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+                        "p2u-5", "p2u-6", "p2u-7";
+        };
+    };
+
+  - |
+    #include <dt-bindings/clock/tegra234-clock.h>
+    #include <dt-bindings/gpio/tegra234-gpio.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/tegra234-powergate.h>
+    #include <dt-bindings/reset/tegra234-reset.h>
+
+    bus@0 {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges = <0x0 0x0 0x0 0x8 0x0>;
+
+        pcie-ep@141a0000 {
+            compatible = "nvidia,tegra234-pcie-ep";
+            power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
+            reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K)      */
+                  <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
+                  <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K)       */
+                  <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G)        */
+            reg-names = "appl", "atu_dma", "dbi", "addr_space";
+
+            interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
+            interrupt-names = "intr";
+
+            clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
+            clock-names = "core";
+
+            resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
+                     <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
+            reset-names = "apb", "core";
+
+            nvidia,bpmp = <&bpmp 5>;
+
+            nvidia,enable-ext-refclk;
+            nvidia,aspm-cmrt-us = <60>;
+            nvidia,aspm-pwr-on-t-us = <20>;
+            nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+            vddio-pex-ctl-supply = <&p3701_vdd_1v8_ls>;
+
+            reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>;
+
+            nvidia,refclk-select-gpios = <&gpio_aon
+                                          TEGRA234_AON_GPIO(AA, 4)
+                                          GPIO_ACTIVE_HIGH>;
+
+            num-lanes = <8>;
+
+            phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
+                   <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
+                   <&p2u_nvhs_6>, <&p2u_nvhs_7>;
+
+            phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
+                        "p2u-5", "p2u-6", "p2u-7";
+        };
+    };

Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt

@@ -1,245 +0,0 @@
-NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based)
-
-This PCIe controller is based on the Synopsis Designware PCIe IP
-and thus inherits all the common properties defined in snps,dw-pcie.yaml and
-snps,dw-pcie-ep.yaml.
-Some of the controller instances are dual mode where in they can work either
-in root port mode or endpoint mode but one at a time.
-
-Required properties:
-- power-domains: A phandle to the node that controls power to the respective
-  PCIe controller and a specifier name for the PCIe controller. Following are
-  the specifiers for the different PCIe controllers
-    TEGRA194_POWER_DOMAIN_PCIEX8B: C0
-    TEGRA194_POWER_DOMAIN_PCIEX1A: C1
-    TEGRA194_POWER_DOMAIN_PCIEX1A: C2
-    TEGRA194_POWER_DOMAIN_PCIEX1A: C3
-    TEGRA194_POWER_DOMAIN_PCIEX4A: C4
-    TEGRA194_POWER_DOMAIN_PCIEX8A: C5
-  these specifiers are defined in
-  "include/dt-bindings/power/tegra194-powergate.h" file.
-- reg: A list of physical base address and length pairs for each set of
-  controller registers. Must contain an entry for each entry in the reg-names
-  property.
-- reg-names: Must include the following entries:
-  "appl": Controller's application logic registers
-  "config": As per the definition in snps,dw-pcie.yaml
-  "atu_dma": iATU and DMA registers. This is where the iATU (internal Address
-             Translation Unit) registers of the PCIe core are made available
-             for SW access.
-  "dbi": The aperture where root port's own configuration registers are
-         available
-- interrupts: A list of interrupt outputs of the controller. Must contain an
-  entry for each entry in the interrupt-names property.
-- interrupt-names: Must include the following entries:
-  "intr": The Tegra interrupt that is asserted for controller interrupts
-- clocks: Must contain an entry for each entry in clock-names.
-  See ../clocks/clock-bindings.txt for details.
-- clock-names: Must include the following entries:
-  - core
-- resets: Must contain an entry for each entry in reset-names.
-  See ../reset/reset.txt for details.
-- reset-names: Must include the following entries:
-  - apb
-  - core
-- phys: Must contain a phandle to P2U PHY for each entry in phy-names.
-- phy-names: Must include an entry for each active lane.
-  "p2u-N": where N ranges from 0 to one less than the total number of lanes
-- nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed
-  by controller-id. Following are the controller ids for each controller.
-    0: C0
-    1: C1
-    2: C2
-    3: C3
-    4: C4
-    5: C5
-- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
-
-RC mode:
-- compatible: Tegra19x must contain  "nvidia,tegra194-pcie"
-- device_type: Must be "pci" for RC mode
-- interrupt-names: Must include the following entries:
-  "msi": The Tegra interrupt that is asserted when an MSI is received
-- bus-range: Range of bus numbers associated with this controller
-- #address-cells: Address representation for root ports (must be 3)
-  - cell 0 specifies the bus and device numbers of the root port:
-    [23:16]: bus number
-    [15:11]: device number
-  - cell 1 denotes the upper 32 address bits and should be 0
-  - cell 2 contains the lower 32 address bits and is used to translate to the
-    CPU address space
-- #size-cells: Size representation for root ports (must be 2)
-- ranges: Describes the translation of addresses for root ports and standard
-  PCI regions. The entries must be 7 cells each, where the first three cells
-  correspond to the address as described for the #address-cells property
-  above, the fourth and fifth cells are for the physical CPU address to
-  translate to and the sixth and seventh cells are as described for the
-  #size-cells property above.
-  - Entries setup the mapping for the standard I/O, memory and
-    prefetchable PCI regions. The first cell determines the type of region
-    that is setup:
-    - 0x81000000: I/O memory region
-    - 0x82000000: non-prefetchable memory region
-    - 0xc2000000: prefetchable memory region
-  Please refer to the standard PCI bus binding document for a more detailed
-  explanation.
-- #interrupt-cells: Size representation for interrupts (must be 1)
-- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
-  Please refer to the standard PCI bus binding document for a more detailed
-  explanation.
-
-EP mode:
-In Tegra194, Only controllers C0, C4 & C5 support EP mode.
-- compatible: Tegra19x must contain "nvidia,tegra194-pcie-ep"
-- reg-names: Must include the following entries:
-  "addr_space": Used to map remote RC address space
-- reset-gpios: Must contain a phandle to a GPIO controller followed by
-  GPIO that is being used as PERST input signal. Please refer to pci.txt
-  document.
-
-Optional properties:
-- pinctrl-names: A list of pinctrl state names.
-  It is mandatory for C5 controller and optional for other controllers.
-  - "default": Configures PCIe I/O for proper operation.
-- pinctrl-0: phandle for the 'default' state of pin configuration.
-  It is mandatory for C5 controller and optional for other controllers.
-- supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt
-- nvidia,update-fc-fixup: This is a boolean property and needs to be present to
-    improve performance when a platform is designed in such a way that it
-    satisfies at least one of the following conditions thereby enabling root
-    port to exchange optimum number of FC (Flow Control) credits with
-    downstream devices
-    1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
-    2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
-       a) speed is Gen-2 and MPS is 256B
-       b) speed is >= Gen-3 with any MPS
-- nvidia,aspm-cmrt-us: Common Mode Restore Time for proper operation of ASPM
-   to be specified in microseconds
-- nvidia,aspm-pwr-on-t-us: Power On time for proper operation of ASPM to be
-   specified in microseconds
-- nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be
-   specified in microseconds
-
-RC mode:
-- vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot
-  if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
-  in p2972-0000 platform).
-- vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot
-  if the platform has one such slot. (Ex:- x16 slot owned by C5 controller
-  in p2972-0000 platform).
-
-EP mode:
-- nvidia,refclk-select-gpios: Must contain a phandle to a GPIO controller
-  followed by GPIO that is being used to enable REFCLK to controller from host
-
-NOTE:- On Tegra194's P2972-0000 platform, only C5 controller can be enabled to
-operate in the endpoint mode because of the way the platform is designed.
-
-Examples:
-=========
-
-Tegra194 RC mode:
------------------
-
-	pcie@14180000 {
-		compatible = "nvidia,tegra194-pcie";
-		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
-		reg = <0x00 0x14180000 0x0 0x00020000   /* appl registers (128K)      */
-		       0x00 0x38000000 0x0 0x00040000   /* configuration space (256K) */
-		       0x00 0x38040000 0x0 0x00040000>; /* iATU_DMA reg space (256K)  */
-		reg-names = "appl", "config", "atu_dma";
-
-		#address-cells = <3>;
-		#size-cells = <2>;
-		device_type = "pci";
-		num-lanes = <8>;
-		linux,pci-domain = <0>;
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
-
-		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
-		clock-names = "core";
-
-		resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
-			 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
-		reset-names = "apb", "core";
-
-		interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,	/* controller interrupt */
-			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;	/* MSI interrupt */
-		interrupt-names = "intr", "msi";
-
-		#interrupt-cells = <1>;
-		interrupt-map-mask = <0 0 0 0>;
-		interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
-
-		nvidia,bpmp = <&bpmp 0>;
-
-		supports-clkreq;
-		nvidia,aspm-cmrt-us = <60>;
-		nvidia,aspm-pwr-on-t-us = <20>;
-		nvidia,aspm-l0s-entrance-latency-us = <3>;
-
-		bus-range = <0x0 0xff>;
-		ranges = <0x81000000 0x0  0x38100000 0x0  0x38100000 0x0 0x00100000    /* downstream I/O (1MB) */
-			  0x82000000 0x0  0x38200000 0x0  0x38200000 0x0 0x01E00000    /* non-prefetchable memory (30MB) */
-			  0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>;  /* prefetchable memory (16GB) */
-
-		vddio-pex-ctl-supply = <&vdd_1v8ao>;
-		vpcie3v3-supply = <&vdd_3v3_pcie>;
-		vpcie12v-supply = <&vdd_12v_pcie>;
-
-		phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
-		       <&p2u_hsio_5>;
-		phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
-	};
-
-Tegra194 EP mode:
------------------
-
-	pcie-ep@141a0000 {
-		compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep";
-		power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>;
-		reg = <0x00 0x141a0000 0x0 0x00020000   /* appl registers (128K)      */
-		       0x00 0x3a040000 0x0 0x00040000   /* iATU_DMA reg space (256K)  */
-		       0x00 0x3a080000 0x0 0x00040000   /* DBI reg space (256K)       */
-		       0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G)        */
-		reg-names = "appl", "atu_dma", "dbi", "addr_space";
-
-		num-lanes = <8>;
-		num-ib-windows = <2>;
-		num-ob-windows = <8>;
-
-		pinctrl-names = "default";
-		pinctrl-0 = <&clkreq_c5_bi_dir_state>;
-
-		clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>;
-		clock-names = "core";
-
-		resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>,
-			 <&bpmp TEGRA194_RESET_PEX1_CORE_5>;
-		reset-names = "apb", "core";
-
-		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;	/* controller interrupt */
-		interrupt-names = "intr";
-
-		nvidia,bpmp = <&bpmp 5>;
-
-		nvidia,aspm-cmrt-us = <60>;
-		nvidia,aspm-pwr-on-t-us = <20>;
-		nvidia,aspm-l0s-entrance-latency-us = <3>;
-
-		vddio-pex-ctl-supply = <&vdd_1v8ao>;
-
-		reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>;
-
-		nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5)
-					      GPIO_ACTIVE_HIGH>;
-
-		phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
-		       <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
-		       <&p2u_nvhs_6>, <&p2u_nvhs_7>;
-
-		phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
-			    "p2u-5", "p2u-6", "p2u-7";
-	};

Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.yaml

@@ -0,0 +1,350 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
+
+maintainers:
+  - Thierry Reding <thierry.reding@gmail.com>
+  - Jon Hunter <jonathanh@nvidia.com>
+  - Vidya Sagar <vidyas@nvidia.com>
+
+description: |
+  This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
+  inherits all the common properties defined in snps,dw-pcie.yaml. Some of
+  the controller instances are dual mode where in they can work either in
+  Root Port mode or Endpoint mode but one at a time.
+
+  See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
+  tree bindings.
+
+properties:
+  compatible:
+    enum:
+      - nvidia,tegra194-pcie
+      - nvidia,tegra234-pcie
+
+  reg:
+    items:
+      - description: controller's application logic registers
+      - description: configuration registers
+      - description: iATU and DMA registers. This is where the iATU (internal
+          Address Translation Unit) registers of the PCIe core are made
+          available for software access.
+      - description: aperture where the Root Port's own configuration
+          registers are available.
+
+  reg-names:
+    items:
+      - const: appl
+      - const: config
+      - const: atu_dma
+      - const: dbi
+
+  interrupts:
+    items:
+      - description: controller interrupt
+      - description: MSI interrupt
+
+  interrupt-names:
+    items:
+      - const: intr
+      - const: msi
+
+  clocks:
+    items:
+      - description: module clock
+
+  clock-names:
+    items:
+      - const: core
+
+  resets:
+    items:
+      - description: APB bus interface reset
+      - description: module reset
+
+  reset-names:
+    items:
+      - const: apb
+      - const: core
+
+  phys:
+    minItems: 1
+    maxItems: 8
+
+  phy-names:
+    minItems: 1
+    items:
+      - const: p2u-0
+      - const: p2u-1
+      - const: p2u-2
+      - const: p2u-3
+      - const: p2u-4
+      - const: p2u-5
+      - const: p2u-6
+      - const: p2u-7
+
+  power-domains:
+    maxItems: 1
+    description: |
+      A phandle to the node that controls power to the respective PCIe
+      controller and a specifier name for the PCIe controller.
+
+      Tegra194 specifiers defined in "include/dt-bindings/power/tegra194-powergate.h"
+      Tegra234 specifiers defined in "include/dt-bindings/power/tegra234-powergate.h"
+
+  interconnects:
+    items:
+      - description: memory read client
+      - description: memory write client
+
+  interconnect-names:
+    items:
+      - const: dma-mem # read
+      - const: write
+
+  dma-coherent: true
+
+  nvidia,bpmp:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description: |
+      Must contain a pair of phandles to BPMP controller node followed by
+      controller ID. Following are the controller IDs for each controller:
+
+      Tegra194
+
+        0: C0
+        1: C1
+        2: C2
+        3: C3
+        4: C4
+        5: C5
+
+      Tegra234
+
+        0 : C0
+        1 : C1
+        2 : C2
+        3 : C3
+        4 : C4
+        5 : C5
+        6 : C6
+        7 : C7
+        8 : C8
+        9 : C9
+        10: C10
+
+    items:
+      - items:
+          - description: phandle to BPMP controller node
+          - description: PCIe controller ID
+            maximum: 10
+
+  nvidia,update-fc-fixup:
+    description: |
+      This is a boolean property and needs to be present to improve performance
+      when a platform is designed in such a way that it satisfies at least one
+      of the following conditions thereby enabling Root Port to exchange
+      optimum number of FC (Flow Control) credits with downstream devices:
+
+      NOTE: This is applicable only for Tegra194.
+
+        1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
+        2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
+          a) speed is Gen-2 and MPS is 256B
+          b) speed is >= Gen-3 with any MPS
+
+    $ref: /schemas/types.yaml#/definitions/flag
+
+  nvidia,aspm-cmrt-us:
+    description: Common Mode Restore Time for proper operation of ASPM to be
+      specified in microseconds
+
+  nvidia,aspm-pwr-on-t-us:
+    description: Power On time for proper operation of ASPM to be specified in
+      microseconds
+
+  nvidia,aspm-l0s-entrance-latency-us:
+    description: ASPM L0s entrance latency to be specified in microseconds
+
+  vddio-pex-ctl-supply:
+    description: A phandle to the regulator supply for PCIe side band signals.
+
+  vpcie3v3-supply:
+    description: A phandle to the regulator node that supplies 3.3V to the slot
+      if the platform has one such slot, e.g., x16 slot owned by C5 controller
+      in p2972-0000 platform.
+
+  vpcie12v-supply:
+    description: A phandle to the regulator node that supplies 12V to the slot
+      if the platform has one such slot, e.g., x16 slot owned by C5 controller
+      in p2972-0000 platform.
+
+  nvidia,enable-srns:
+    description: |
+      This boolean property needs to be present if the controller is
+      configured to operate in SRNS (Separate Reference Clocks with No
+      Spread-Spectrum Clocking).  NOTE: This is applicable only for
+      Tegra234.
+
+    $ref: /schemas/types.yaml#/definitions/flag
+
+  nvidia,enable-ext-refclk:
+    description: |
+      This boolean property needs to be present if the controller is
+      configured to use the reference clocking coming in from an external
+      clock source instead of using the internal clock source.
+
+    $ref: /schemas/types.yaml#/definitions/flag
+
+allOf:
+  - $ref: /schemas/pci/snps,dw-pcie.yaml#
+
+unevaluatedProperties: false
+
+required:
+  - interrupts
+  - interrupt-names
+  - interrupt-map
+  - interrupt-map-mask
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - power-domains
+  - vddio-pex-ctl-supply
+  - num-lanes
+  - phys
+  - phy-names
+  - nvidia,bpmp
+
+examples:
+  - |
+    #include <dt-bindings/clock/tegra194-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/tegra194-powergate.h>
+    #include <dt-bindings/reset/tegra194-reset.h>
+
+    bus@0 {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges = <0x0 0x0 0x0 0x8 0x0>;
+
+        pcie@14180000 {
+            compatible = "nvidia,tegra194-pcie";
+            power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
+            reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
+                  <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
+                  <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
+                  <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K)       */
+            reg-names = "appl", "config", "atu_dma", "dbi";
+
+            #address-cells = <3>;
+            #size-cells = <2>;
+            device_type = "pci";
+            num-lanes = <8>;
+            linux,pci-domain = <0>;
+
+            pinctrl-names = "default";
+            pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
+
+            clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
+            clock-names = "core";
+
+            resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
+                     <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
+            reset-names = "apb", "core";
+
+            interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+                         <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+            interrupt-names = "intr", "msi";
+
+            #interrupt-cells = <1>;
+            interrupt-map-mask = <0 0 0 0>;
+            interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+
+            nvidia,bpmp = <&bpmp 0>;
+
+            supports-clkreq;
+            nvidia,aspm-cmrt-us = <60>;
+            nvidia,aspm-pwr-on-t-us = <20>;
+            nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+            bus-range = <0x0 0xff>;
+            ranges = <0x81000000 0x0  0x38100000 0x0  0x38100000 0x0 0x00100000>, /* downstream I/O */
+                     <0x82000000 0x0  0x38200000 0x0  0x38200000 0x0 0x01e00000>, /* non-prefetch memory */
+                     <0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory */
+
+            vddio-pex-ctl-supply = <&vdd_1v8ao>;
+            vpcie3v3-supply = <&vdd_3v3_pcie>;
+            vpcie12v-supply = <&vdd_12v_pcie>;
+
+            phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
+                   <&p2u_hsio_5>;
+            phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
+        };
+    };
+
+  - |
+    #include <dt-bindings/clock/tegra234-clock.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/power/tegra234-powergate.h>
+    #include <dt-bindings/reset/tegra234-reset.h>
+
+    bus@0 {
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges = <0x0 0x0 0x0 0x8 0x0>;
+
+        pcie@14160000 {
+            compatible = "nvidia,tegra234-pcie";
+            power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
+            reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
+                  <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
+                  <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
+                  <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K)       */
+            reg-names = "appl", "config", "atu_dma", "dbi";
+
+            #address-cells = <3>;
+            #size-cells = <2>;
+            device_type = "pci";
+            num-lanes = <4>;
+            num-viewport = <8>;
+            linux,pci-domain = <4>;
+
+            clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
+            clock-names = "core";
+
+            resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
+                     <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
+            reset-names = "apb", "core";
+
+            interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
+                         <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
+            interrupt-names = "intr", "msi";
+
+            #interrupt-cells = <1>;
+            interrupt-map-mask = <0 0 0 0>;
+            interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+
+            nvidia,bpmp = <&bpmp 4>;
+
+            nvidia,aspm-cmrt-us = <60>;
+            nvidia,aspm-pwr-on-t-us = <20>;
+            nvidia,aspm-l0s-entrance-latency-us = <3>;
+
+            bus-range = <0x0 0xff>;
+            ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable */
+                     <0x02000000 0x0  0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable */
+                     <0x01000000 0x0  0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O */
+
+            vddio-pex-ctl-supply = <&p3701_vdd_AO_1v8>;
+
+            phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
+                   <&p2u_hsio_7>;
+            phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
+        };
+    };

Documentation/devicetree/bindings/pci/pci-rcar-gen2.txt

@@ -1,84 +0,0 @@
-Renesas AHB to PCI bridge
--------------------------
-
-This is the bridge used internally to connect the USB controllers to the
-AHB. There is one bridge instance per USB port connected to the internal
-OHCI and EHCI controllers.
-
-Required properties:
-- compatible: "renesas,pci-r8a7742" for the R8A7742 SoC;
-	      "renesas,pci-r8a7743" for the R8A7743 SoC;
-	      "renesas,pci-r8a7744" for the R8A7744 SoC;
-	      "renesas,pci-r8a7745" for the R8A7745 SoC;
-	      "renesas,pci-r8a7790" for the R8A7790 SoC;
-	      "renesas,pci-r8a7791" for the R8A7791 SoC;
-	      "renesas,pci-r8a7793" for the R8A7793 SoC;
-	      "renesas,pci-r8a7794" for the R8A7794 SoC;
-	      "renesas,pci-rcar-gen2" for a generic R-Car Gen2 or
-				      RZ/G1 compatible device.
-
-
-	      When compatible with the generic version, nodes must list the
-	      SoC-specific version corresponding to the platform first
-	      followed by the generic version.
-
-- reg:	A list of physical regions to access the device: the first is
-	the operational registers for the OHCI/EHCI controllers and the
-	second is for the bridge configuration and control registers.
-- interrupts: interrupt for the device.
-- clocks: The reference to the device clock.
-- bus-range: The PCI bus number range; as this is a single bus, the range
-	     should be specified as the same value twice.
-- #address-cells: must be 3.
-- #size-cells: must be 2.
-- #interrupt-cells: must be 1.
-- interrupt-map: standard property used to define the mapping of the PCI
-  interrupts to the GIC interrupts.
-- interrupt-map-mask: standard property that helps to define the interrupt
-  mapping.
-
-Optional properties:
-- dma-ranges: a single range for the inbound memory region. If not supplied,
-  defaults to 1GiB at 0x40000000. Note there are hardware restrictions on the
-  allowed combinations of address and size.
-
-Example SoC configuration:
-
-	pci0: pci@ee090000  {
-		compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
-		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
-		reg = <0x0 0xee090000 0x0 0xc00>,
-		      <0x0 0xee080000 0x0 0x1100>;
-		interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
-		status = "disabled";
-
-		bus-range = <0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-		#interrupt-cells = <1>;
-		dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
-		interrupt-map-mask = <0xff00 0 0 0x7>;
-		interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
-				 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
-				 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
-
-		usb@1,0 {
-			reg = <0x800 0 0 0 0>;
-			phys = <&usb0 0>;
-			phy-names = "usb";
-		};
-
-		usb@2,0 {
-			reg = <0x1000 0 0 0 0>;
-			phys = <&usb0 0>;
-			phy-names = "usb";
-		};
-	};
-
-Example board setup:
-
-&pci0 {
-	status = "okay";
-	pinctrl-0 = <&usb0_pins>;
-	pinctrl-names = "default";
-};

Documentation/devicetree/bindings/pci/qcom,pcie.yaml

@@ -11,7 +11,7 @@ maintainers:
   - Stanimir Varbanov <svarbanov@mm-sol.com>
 
 description: |
-  Qualcomm PCIe root complex controller is bansed on the Synopsys DesignWare
+  Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
   PCIe IP.
 
 properties:
@@ -43,11 +43,12 @@ properties:
     maxItems: 5
 
   interrupts:
-    maxItems: 1
+    minItems: 1
+    maxItems: 8
 
   interrupt-names:
-    items:
-      - const: msi
+    minItems: 1
+    maxItems: 8
 
   # Common definitions for clocks, clock-names and reset.
   # Platform constraints are described later.
@@ -614,7 +615,7 @@ allOf:
   - if:
       not:
         properties:
-          compatibles:
+          compatible:
             contains:
               enum:
                 - qcom,pcie-msm8996
@@ -623,6 +624,50 @@ allOf:
         - resets
         - reset-names
 
+    # Newer chipsets support either 1 or 8 MSI vectors
+    # On older chipsets it's always 1 MSI vector
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - qcom,pcie-msm8996
+              - qcom,pcie-sc7280
+              - qcom,pcie-sc8180x
+              - qcom,pcie-sdm845
+              - qcom,pcie-sm8150
+              - qcom,pcie-sm8250
+              - qcom,pcie-sm8450-pcie0
+              - qcom,pcie-sm8450-pcie1
+    then:
+      oneOf:
+        - properties:
+            interrupts:
+              maxItems: 1
+            interrupt-names:
+              items:
+                - const: msi
+        - properties:
+            interrupts:
+              minItems: 8
+            interrupt-names:
+              items:
+                - const: msi0
+                - const: msi1
+                - const: msi2
+                - const: msi3
+                - const: msi4
+                - const: msi5
+                - const: msi6
+                - const: msi7
+    else:
+      properties:
+        interrupts:
+          maxItems: 1
+        interrupt-names:
+          items:
+            - const: msi
+
 unevaluatedProperties: false
 
 examples:

Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml

@@ -0,0 +1,186 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/renesas,pci-rcar-gen2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas AHB to PCI bridge
+
+maintainers:
+  - Marek Vasut <marek.vasut+renesas@gmail.com>
+  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+
+description: |
+  This is the bridge used internally to connect the USB controllers to the
+  AHB. There is one bridge instance per USB port connected to the internal
+  OHCI and EHCI controllers.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - renesas,pci-r8a7742      # RZ/G1H
+              - renesas,pci-r8a7743      # RZ/G1M
+              - renesas,pci-r8a7744      # RZ/G1N
+              - renesas,pci-r8a7745      # RZ/G1E
+              - renesas,pci-r8a7790      # R-Car H2
+              - renesas,pci-r8a7791      # R-Car M2-W
+              - renesas,pci-r8a7793      # R-Car M2-N
+              - renesas,pci-r8a7794      # R-Car E2
+          - const: renesas,pci-rcar-gen2 # R-Car Gen2 and RZ/G1
+      - items:
+          - enum:
+              - renesas,pci-r9a06g032     # RZ/N1D
+          - const: renesas,pci-rzn1       # RZ/N1
+
+  reg:
+    items:
+      - description: Operational registers for the OHCI/EHCI controllers.
+      - description: Bridge configuration and control registers.
+
+  interrupts:
+    maxItems: 1
+
+  clocks: true
+
+  clock-names: true
+
+  resets:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  bus-range:
+    description: |
+      The PCI bus number range; as this is a single bus, the range
+      should be specified as the same value twice.
+
+  dma-ranges:
+    description: |
+      A single range for the inbound memory region. If not supplied,
+      defaults to 1GiB at 0x40000000. Note there are hardware restrictions on
+      the allowed combinations of address and size.
+    maxItems: 1
+
+patternProperties:
+  'usb@[0-1],0':
+    type: object
+
+    description:
+      This a USB controller PCI device
+
+    properties:
+      reg:
+        description:
+          Identify the correct bus, device and function number in the
+          form <bdf 0 0 0 0>.
+
+        items:
+          minItems: 5
+          maxItems: 5
+
+      phys:
+        description:
+          Reference to the USB phy
+        maxItems: 1
+
+      phy-names:
+        maxItems: 1
+
+    required:
+      - reg
+      - phys
+      - phy-names
+
+    unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-map
+  - interrupt-map-mask
+  - clocks
+  - power-domains
+  - bus-range
+  - "#address-cells"
+  - "#size-cells"
+  - "#interrupt-cells"
+
+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,pci-rzn1
+    then:
+      properties:
+        clocks:
+          items:
+            - description: Internal bus clock (AHB) for HOST
+            - description: Internal bus clock (AHB) Power Management
+            - description: PCI clock for USB subsystem
+        clock-names:
+          items:
+            - const: hclkh
+            - const: hclkpm
+            - const: pciclk
+      required:
+        - clock-names
+    else:
+      properties:
+        clocks:
+          items:
+            - description: Device clock
+        clock-names:
+          items:
+            - const: pclk
+      required:
+        - resets
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
+    #include <dt-bindings/power/r8a7790-sysc.h>
+
+    pci@ee090000  {
+        compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
+        device_type = "pci";
+        reg = <0xee090000 0xc00>,
+              <0xee080000 0x1100>;
+        clocks = <&cpg CPG_MOD 703>;
+        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
+        resets = <&cpg 703>;
+        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+        bus-range = <0 0>;
+        #address-cells = <3>;
+        #size-cells = <2>;
+        #interrupt-cells = <1>;
+        ranges = <0x02000000 0 0xee080000 0xee080000 0 0x00010000>;
+        dma-ranges = <0x42000000 0 0x40000000 0x40000000 0 0x40000000>;
+        interrupt-map-mask = <0xf800 0 0 0x7>;
+        interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+
+        usb@1,0 {
+            reg = <0x800 0 0 0 0>;
+            phys = <&usb0 0>;
+            phy-names = "usb";
+        };
+
+        usb@2,0 {
+            reg = <0x1000 0 0 0 0>;
+            phys = <&usb0 0>;
+            phy-names = "usb";
+        };
+    };

Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml

@@ -34,8 +34,8 @@ properties:
     minItems: 2
     maxItems: 5
     items:
-      enum: [ dbi, dbi2, config, atu, app, elbi, mgmt, ctrl, parf, cfg, link,
-              ulreg, smu, mpu, apb, phy ]
+      enum: [ dbi, dbi2, config, atu, atu_dma, app, appl, elbi, mgmt, ctrl,
+              parf, cfg, link, ulreg, smu, mpu, apb, phy ]
 
   num-lanes:
     description: |