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arm64: dts: freescale: Add support for Variscite VAR-SOM-MX91
Add device tree support for the Variscite VAR-SOM-MX91 system on module. This SOM is designed to be used with various carrier boards. The module includes: - NXP i.MX91 MPU processor - Up to 2GB of LPDDR4 memory - Up to 128GB of eMMC storage memory - Integrated 10/100/1000 Mbps Ethernet Transceiver - Codec audio WM8904 - WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth Only SOM-specific peripherals are enabled by default. Carrier board specific interfaces are left disabled to be enabled in the respective carrier board device trees. Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/var-som-mx91/ Signed-off-by: Stefano Radaelli <stefano.r@variscite.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Frank Li <Frank.Li@nxp.com>
This commit is contained in:
Stefano Radaelli
Frank Li
parent
05bee22e1a
commit
92e5a1654e
456
arch/arm64/boot/dts/freescale/imx91-var-som.dtsi
Normal file
456
arch/arm64/boot/dts/freescale/imx91-var-som.dtsi
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@ -0,0 +1,456 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Common dtsi for Variscite VAR-SOM-MX91
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*
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* Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/var-som-mx91/
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*
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* Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
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*
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*/
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/dts-v1/;
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#include "imx91.dtsi"
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/{
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model = "Variscite VAR-SOM-MX91 module";
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compatible = "variscite,var-som-mx91", "fsl,imx91";
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usdhc3_pwrseq: mmc-pwrseq {
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compatible = "mmc-pwrseq-simple";
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post-power-on-delay-ms = <100>;
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power-off-delay-us = <10000>;
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reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
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<&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
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};
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sound {
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compatible = "simple-audio-card";
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simple-audio-card,bitclock-master = <&codec_dai>;
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simple-audio-card,format = "i2s";
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simple-audio-card,frame-master = <&codec_dai>;
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simple-audio-card,name = "wm8904-audio";
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simple-audio-card,routing =
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"Headphone Jack", "HPOUTL",
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"Headphone Jack", "HPOUTR",
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"IN2L", "Line In Jack",
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"IN2R", "Line In Jack",
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"IN1L", "Microphone Jack",
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"IN1R", "Microphone Jack";
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simple-audio-card,widgets =
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"Microphone", "Microphone Jack",
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"Headphone", "Headphone Jack",
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"Line", "Line In Jack";
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simple-audio-card,mclk-fs = <256>;
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codec_dai: simple-audio-card,codec {
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sound-dai = <&wm8904>;
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};
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simple-audio-card,cpu {
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sound-dai = <&sai1>;
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};
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};
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};
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&eqos {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_eqos>;
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pinctrl-1 = <&pinctrl_eqos_sleep>;
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/*
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* The required RGMII TX and RX 2ns delays are implemented directly
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* in hardware via passive delay elements on the SOM PCB.
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* No delay configuration is needed in software via PHY driver.
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*/
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phy-mode = "rgmii";
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phy-handle = <ðphy0>;
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snps,clk-csr = <5>;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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eee-broken-1000t;
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reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
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reset-assert-us = <15000>;
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reset-deassert-us = <100000>;
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};
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};
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};
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&lpi2c3 {
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clock-frequency = <400000>;
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pinctrl-names = "default", "sleep", "gpio";
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pinctrl-0 = <&pinctrl_lpi2c3>;
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pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
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pinctrl-2 = <&pinctrl_lpi2c3_gpio>;
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scl-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
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status = "okay";
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pmic@25 {
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compatible = "nxp,pca9451a";
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reg = <0x25>;
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regulators {
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buck1: BUCK1 {
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regulator-name = "BUCK1";
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regulator-min-microvolt = <650000>;
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regulator-max-microvolt = <2237500>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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buck2: BUCK2 {
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regulator-name = "BUCK2";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <2187500>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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buck4: BUCK4 {
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regulator-name = "BUCK4";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck5: BUCK5 {
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regulator-name = "BUCK5";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck6: BUCK6 {
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regulator-name = "BUCK6";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1: LDO1 {
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regulator-name = "LDO1";
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regulator-min-microvolt = <1600000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo4: LDO4 {
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regulator-name = "LDO4";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo5: LDO5 {
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regulator-name = "LDO5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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};
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wm8904: audio-codec@1a {
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compatible = "wlf,wm8904";
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reg = <0x1a>;
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#sound-dai-cells = <0>;
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clocks = <&clk IMX93_CLK_SAI1_GATE>;
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clock-names = "mclk";
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AVDD-supply = <&buck5>;
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CPVDD-supply = <&buck5>;
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DBVDD-supply = <&buck4>;
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DCVDD-supply = <&buck5>;
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MICVDD-supply = <&buck5>;
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wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
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"soft", "music";
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/*
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* Config registers per name, respectively:
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* KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
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* KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
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* KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
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* KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
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* KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
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*/
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wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
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/bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
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/bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
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/bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
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/bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
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/* GPIO1 = DMIC_CLK, don't touch others */
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wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
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};
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};
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&lpspi8 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpspi8>;
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cs-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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/* BT module */
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&lpuart5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart5>, <&pinctrl_bluetooth>;
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uart-has-rtscts;
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status = "okay";
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bluetooth {
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compatible = "nxp,88w8987-bt";
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};
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};
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&sai1 {
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&pinctrl_sai1>;
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pinctrl-1 = <&pinctrl_sai1_sleep>;
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assigned-clocks = <&clk IMX93_CLK_SAI1>;
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assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
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assigned-clock-rates = <12288000>;
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fsl,sai-mclk-direction-output;
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status = "okay";
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};
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/* eMMC */
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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/* WiFi */
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
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pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>;
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pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>;
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bus-width = <4>;
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keep-power-in-suspend;
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mmc-pwrseq = <&usdhc3_pwrseq>;
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non-removable;
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wakeup-source;
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status = "okay";
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};
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&iomuxc {
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pinctrl_bluetooth: bluetoothgrp {
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fsl,pins = <
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MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
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>;
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};
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pinctrl_eqos: eqosgrp {
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fsl,pins = <
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MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e
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MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
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MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
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MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
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MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
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MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
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MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe
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MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
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MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
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MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e
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MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
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MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
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MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
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MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
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MX91_PAD_UART2_TXD__GPIO1_IO7 0x51e
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>;
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};
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pinctrl_eqos_sleep: eqos-sleepgrp {
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fsl,pins = <
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MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e
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MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e
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MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e
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MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e
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MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e
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MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e
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MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e
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MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e
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MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e
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MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e
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MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e
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MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e
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MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e
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MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e
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>;
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};
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pinctrl_lpi2c3: lpi2c3grp {
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fsl,pins = <
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MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
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MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
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>;
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};
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pinctrl_lpi2c3_gpio: lpi2c3-gpiogrp {
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fsl,pins = <
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MX91_PAD_GPIO_IO28__GPIO2_IO28 0x40000b9e
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MX91_PAD_GPIO_IO29__GPIO2_IO29 0x40000b9e
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>;
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};
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pinctrl_lpspi8: lpspi8grp {
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fsl,pins = <
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MX91_PAD_GPIO_IO12__GPIO2_IO12 0x31e
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MX91_PAD_GPIO_IO13__LPSPI8_SIN 0x31e
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MX91_PAD_GPIO_IO14__LPSPI8_SOUT 0x31e
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MX91_PAD_GPIO_IO15__LPSPI8_SCK 0x31e
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>;
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};
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pinctrl_lpuart5: lpuart5grp {
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fsl,pins = <
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MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e
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MX91_PAD_DAP_TDI__LPUART5_RX 0x31e
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MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e
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MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e
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>;
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};
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pinctrl_sai1: sai1grp {
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fsl,pins = <
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MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
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MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
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MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e
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MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e
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MX91_PAD_I2C2_SDA__SAI1_RX_BCLK 0x31e
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MX91_PAD_I2C2_SCL__SAI1_RX_SYNC 0x31e
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MX91_PAD_UART2_RXD__SAI1_MCLK 0x31e
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>;
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};
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pinctrl_sai1_sleep: sai1-sleepgrp {
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fsl,pins = <
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MX91_PAD_SAI1_TXC__GPIO1_IO12 0x31e
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MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x31e
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MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x31e
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MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x31e
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MX91_PAD_UART2_RXD__GPIO1_IO6 0x31e
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MX91_PAD_I2C2_SDA__GPIO1_IO3 0x31e
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MX91_PAD_I2C2_SCL__GPIO1_IO2 0x31e
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582
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MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382
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MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382
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MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382
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MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382
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MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382
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MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382
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MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382
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MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382
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MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382
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MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
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fsl,pins = <
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MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e
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MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e
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MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
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MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
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MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
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MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
|
||||
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
|
||||
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
|
||||
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
|
||||
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
|
||||
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe
|
||||
MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe
|
||||
MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
|
||||
MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
|
||||
MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
|
||||
MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
|
||||
MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
|
||||
MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
|
||||
MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
|
||||
MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
|
||||
MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582
|
||||
MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382
|
||||
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382
|
||||
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382
|
||||
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382
|
||||
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e
|
||||
MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e
|
||||
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e
|
||||
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e
|
||||
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e
|
||||
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe
|
||||
MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe
|
||||
MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe
|
||||
MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe
|
||||
MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe
|
||||
MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_sleep: usdhc3-sleepgrp {
|
||||
fsl,pins = <
|
||||
MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e
|
||||
MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e
|
||||
MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e
|
||||
MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e
|
||||
MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e
|
||||
MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_wlan: usdhc3-wlangrp {
|
||||
fsl,pins = <
|
||||
MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e
|
||||
MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x51e
|
||||
>;
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user