diff --git a/include/dt-bindings/clock/qcom,camcc-pineapple.h b/include/dt-bindings/clock/qcom,camcc-pineapple.h index 8eb1ce5a294e..4035ed9cf514 100644 --- a/include/dt-bindings/clock/qcom,camcc-pineapple.h +++ b/include/dt-bindings/clock/qcom,camcc-pineapple.h @@ -141,29 +141,30 @@ #define CAM_CC_PLL8_OUT_EVEN 131 #define CAM_CC_PLL9 132 #define CAM_CC_PLL9_OUT_EVEN 133 -#define CAM_CC_QDSS_DEBUG_CLK 134 -#define CAM_CC_QDSS_DEBUG_CLK_SRC 135 -#define CAM_CC_QDSS_DEBUG_XO_CLK 136 -#define CAM_CC_SBI_CLK 137 -#define CAM_CC_SBI_FAST_AHB_CLK 138 -#define CAM_CC_SBI_SHIFT_CLK 139 -#define CAM_CC_SFE_0_CLK 140 -#define CAM_CC_SFE_0_CLK_SRC 141 -#define CAM_CC_SFE_0_FAST_AHB_CLK 142 -#define CAM_CC_SFE_0_SHIFT_CLK 143 -#define CAM_CC_SFE_1_CLK 144 -#define CAM_CC_SFE_1_CLK_SRC 145 -#define CAM_CC_SFE_1_FAST_AHB_CLK 146 -#define CAM_CC_SFE_1_SHIFT_CLK 147 -#define CAM_CC_SFE_2_CLK 148 -#define CAM_CC_SFE_2_CLK_SRC 149 -#define CAM_CC_SFE_2_FAST_AHB_CLK 150 -#define CAM_CC_SFE_2_SHIFT_CLK 151 -#define CAM_CC_SLEEP_CLK 152 -#define CAM_CC_SLEEP_CLK_SRC 153 -#define CAM_CC_SLOW_AHB_CLK_SRC 154 -#define CAM_CC_TITAN_TOP_SHIFT_CLK 155 -#define CAM_CC_XO_CLK_SRC 156 +#define CAM_CC_PLL9_OUT_ODD 134 +#define CAM_CC_QDSS_DEBUG_CLK 135 +#define CAM_CC_QDSS_DEBUG_CLK_SRC 136 +#define CAM_CC_QDSS_DEBUG_XO_CLK 137 +#define CAM_CC_SBI_CLK 138 +#define CAM_CC_SBI_FAST_AHB_CLK 139 +#define CAM_CC_SBI_SHIFT_CLK 140 +#define CAM_CC_SFE_0_CLK 141 +#define CAM_CC_SFE_0_CLK_SRC 142 +#define CAM_CC_SFE_0_FAST_AHB_CLK 143 +#define CAM_CC_SFE_0_SHIFT_CLK 144 +#define CAM_CC_SFE_1_CLK 145 +#define CAM_CC_SFE_1_CLK_SRC 146 +#define CAM_CC_SFE_1_FAST_AHB_CLK 147 +#define CAM_CC_SFE_1_SHIFT_CLK 148 +#define CAM_CC_SFE_2_CLK 149 +#define CAM_CC_SFE_2_CLK_SRC 150 +#define CAM_CC_SFE_2_FAST_AHB_CLK 151 +#define CAM_CC_SFE_2_SHIFT_CLK 152 +#define CAM_CC_SLEEP_CLK 153 +#define CAM_CC_SLEEP_CLK_SRC 154 +#define CAM_CC_SLOW_AHB_CLK_SRC 155 +#define CAM_CC_TITAN_TOP_SHIFT_CLK 156 +#define CAM_CC_XO_CLK_SRC 157 /* CAM_CC resets */ #define CAM_CC_BPS_BCR 0