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arm64: dts: exynos: gs101: define Multi Core Timer (MCT) node

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MCT has one global timer and 8 CPU local timers. The global timer
can generate 4 interrupts, and each local timer can generate an
interrupt making 12 interrupts in total.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20231222165355.1462740-4-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
This commit is contained in:
Peter Griffin 2023-12-22 16:53:55 +00:00 committed by Krzysztof Kozlowski
parent bc8cc7fb55
commit 927b46b543
1 changed files with 20 additions and 0 deletions
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20
arch/arm64/boot/dts/exynos/google/gs101.dtsi
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@ -292,6 +292,26 @@ cmu_misc: clock-controller@10010000 {
clock-names = "dout_cmu_misc_bus", "dout_cmu_misc_sss";
};
timer@10050000 {
compatible = "google,gs101-mct",
"samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 755 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 756 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 757 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 758 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 759 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 760 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 762 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 763 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&ext_24_5m>, <&cmu_misc CLK_GOUT_MISC_MCT_PCLK>;
clock-names = "fin_pll", "mct";
};
watchdog_cl0: watchdog@10060000 {
compatible = "google,gs101-wdt";
reg = <0x10060000 0x100>;