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drm/i915/xe2lpd: Handle port AUX interrupts

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Differently from previous version, Xe2_LPD groups all port AUX interrupt
bits into PICA interrupt registers.

While at it, drop some trailing newlines.

BSpec: 68958, 69697
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230919192128.2045154-13-lucas.demarchi@intel.com
This commit is contained in:
Gustavo Sousa 2023-09-19 12:21:19 -07:00 committed by Lucas De Marchi
parent 449f87e66d
commit 925163b4af
3 changed files with 8 additions and 4 deletions
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4
drivers/gpu/drm/i915/display/intel_display_irq.c
View File

@ -792,7 +792,9 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
{
u32 mask;
if (DISPLAY_VER(dev_priv) >= 14)
if (DISPLAY_VER(dev_priv) >= 20)
return 0;
else if (DISPLAY_VER(dev_priv) >= 14)
return TGL_DE_PORT_AUX_DDIA |
TGL_DE_PORT_AUX_DDIB;
else if (DISPLAY_VER(dev_priv) >= 13)

3
drivers/gpu/drm/i915/display/intel_hotplug_irq.c
View File

@ -514,6 +514,9 @@ void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
u32 pin_mask = 0, long_mask = 0;
if (DISPLAY_VER(i915) >= 20)
trigger_aux |= iir & XE2LPD_AUX_DDI_MASK;
for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
u32 val;

5
drivers/gpu/drm/i915/i915_reg.h
View File

@ -4467,13 +4467,12 @@
#define PICAINTERRUPT_IMR _MMIO(0x16FE54)
#define PICAINTERRUPT_IIR _MMIO(0x16FE58)
#define PICAINTERRUPT_IER _MMIO(0x16FE5C)
#define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
#define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16)
#define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin))
#define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8)
#define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin))
#define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6)
#define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
#define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)