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bus: mhi: host: pci_generic: Add support for QDU100 device

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Add MHI controller configuration for QDU100 device.

The Qualcomm X100 5G RAN Accelerator card is designed to enhance Open vRAN
servers by offloading CPUs from intensive 5G baseband functions.

Link: https://docs.qualcomm.com/bundle/publicresource/87-79371-1_REV_A_Qualcomm_X100_5G_RAN_Accelerator_Card_Product_Brief.pdf

Signed-off-by: Vivek Pernamitta <quic_vpernami@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20241212-qdu100_us-v5-1-3349fb23512a@quicinc.com
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
This commit is contained in:
Vivek Pernamitta 2024-12-12 17:27:27 +05:30 committed by Manivannan Sadhasivam
parent 7222ae1d3e
commit 9241459b3c
1 changed files with 55 additions and 0 deletions
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55
drivers/bus/mhi/host/pci_generic.c
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@ -245,6 +245,58 @@ struct mhi_pci_dev_info {
.channel = ch_num, \
}
static const struct mhi_channel_config mhi_qcom_qdu100_channels[] = {
MHI_CHANNEL_CONFIG_UL(0, "LOOPBACK", 32, 2),
MHI_CHANNEL_CONFIG_DL(1, "LOOPBACK", 32, 2),
MHI_CHANNEL_CONFIG_UL_SBL(2, "SAHARA", 128, 1),
MHI_CHANNEL_CONFIG_DL_SBL(3, "SAHARA", 128, 1),
MHI_CHANNEL_CONFIG_UL(4, "DIAG", 64, 3),
MHI_CHANNEL_CONFIG_DL(5, "DIAG", 64, 3),
MHI_CHANNEL_CONFIG_UL(9, "QDSS", 64, 3),
MHI_CHANNEL_CONFIG_UL(14, "NMEA", 32, 4),
MHI_CHANNEL_CONFIG_DL(15, "NMEA", 32, 4),
MHI_CHANNEL_CONFIG_UL(16, "CSM_CTRL", 32, 4),
MHI_CHANNEL_CONFIG_DL(17, "CSM_CTRL", 32, 4),
MHI_CHANNEL_CONFIG_UL(40, "MHI_PHC", 32, 4),
MHI_CHANNEL_CONFIG_DL(41, "MHI_PHC", 32, 4),
MHI_CHANNEL_CONFIG_UL(46, "IP_SW0", 256, 5),
MHI_CHANNEL_CONFIG_DL(47, "IP_SW0", 256, 5),
};
static struct mhi_event_config mhi_qcom_qdu100_events[] = {
/* first ring is control+data ring */
MHI_EVENT_CONFIG_CTRL(0, 64),
/* SAHARA dedicated event ring */
MHI_EVENT_CONFIG_SW_DATA(1, 256),
/* Software channels dedicated event ring */
MHI_EVENT_CONFIG_SW_DATA(2, 64),
MHI_EVENT_CONFIG_SW_DATA(3, 256),
MHI_EVENT_CONFIG_SW_DATA(4, 256),
/* Software IP channels dedicated event ring */
MHI_EVENT_CONFIG_SW_DATA(5, 512),
MHI_EVENT_CONFIG_SW_DATA(6, 512),
MHI_EVENT_CONFIG_SW_DATA(7, 512),
};
static const struct mhi_controller_config mhi_qcom_qdu100_config = {
.max_channels = 128,
.timeout_ms = 120000,
.num_channels = ARRAY_SIZE(mhi_qcom_qdu100_channels),
.ch_cfg = mhi_qcom_qdu100_channels,
.num_events = ARRAY_SIZE(mhi_qcom_qdu100_events),
.event_cfg = mhi_qcom_qdu100_events,
};
static const struct mhi_pci_dev_info mhi_qcom_qdu100_info = {
.name = "qcom-qdu100",
.fw = "qcom/qdu100/xbl_s.melf",
.edl_trigger = true,
.config = &mhi_qcom_qdu100_config,
.bar_num = MHI_PCI_DEFAULT_BAR_NUM,
.dma_data_width = 32,
.sideband_wake = false,
};
static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = {
MHI_CHANNEL_CONFIG_UL(4, "DIAG", 16, 1),
MHI_CHANNEL_CONFIG_DL(5, "DIAG", 16, 1),
@ -742,6 +794,9 @@ static const struct pci_device_id mhi_pci_id_table[] = {
.driver_data = (kernel_ulong_t) &mhi_qcom_sdx65_info },
{ PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0309),
.driver_data = (kernel_ulong_t) &mhi_qcom_sdx75_info },
/* QDU100, x100-DU */
{ PCI_DEVICE(PCI_VENDOR_ID_QCOM, 0x0601),
.driver_data = (kernel_ulong_t) &mhi_qcom_qdu100_info },
{ PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1001), /* EM120R-GL (sdx24) */
.driver_data = (kernel_ulong_t) &mhi_quectel_em1xx_info },
{ PCI_DEVICE(PCI_VENDOR_ID_QUECTEL, 0x1002), /* EM160R-GL (sdx24) */