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mmc: mtk-sd: Add condition to enable 'single' burst type

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This change add a condition for 'single' burst type selection.

Read AXI_LEN field from EMMC50_CFG2(AHB2AXI wrapper) register, if the
value is not 0, it means the HWIP is using AXI as AMBA bus, which do
not support 'single' burst type.

Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Axe Yang <axe.yang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20250411054134.31822-1-axe.yang@mediatek.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Axe Yang 2025-04-11 13:40:25 +08:00 committed by Ulf Hansson
parent 1c7387579d
commit 920e6bfa6a
1 changed files with 12 additions and 4 deletions
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16
drivers/mmc/host/mtk-sd.c
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@ -84,6 +84,7 @@
#define EMMC51_CFG0 0x204
#define EMMC50_CFG0 0x208
#define EMMC50_CFG1 0x20c
#define EMMC50_CFG2 0x21c
#define EMMC50_CFG3 0x220
#define SDC_FIFO_CFG 0x228
#define CQHCI_SETTING 0x7fc
@ -306,7 +307,10 @@
/* EMMC50_CFG1 mask */
#define EMMC50_CFG1_DS_CFG BIT(28) /* RW */
#define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */
/* EMMC50_CFG2 mask */
#define EMMC50_CFG2_AXI_SET_LEN GENMASK(27, 24) /* RW */
#define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */
#define SDC_FIFO_CFG_WRVALIDSEL BIT(24) /* RW */
#define SDC_FIFO_CFG_RDVALIDSEL BIT(25) /* RW */
@ -1917,9 +1921,13 @@ static void msdc_init_hw(struct msdc_host *host)
pb1_val |= FIELD_PREP(MSDC_PATCH_BIT1_CMDTA, 1);
pb1_val |= MSDC_PB1_DDR_CMD_FIX_SEL;
/* Set single burst mode, auto sync state clear, block gap stop clk */
pb1_val |= MSDC_PB1_SINGLE_BURST | MSDC_PB1_RSVD20 |
MSDC_PB1_AUTO_SYNCST_CLR | MSDC_PB1_MARK_POP_WATER;
/* Support 'single' burst type only when AXI_LEN is 0 */
sdr_get_field(host->base + EMMC50_CFG2, EMMC50_CFG2_AXI_SET_LEN, &val);
if (!val)
pb1_val |= MSDC_PB1_SINGLE_BURST;
/* Set auto sync state clear, block gap stop clk */
pb1_val |= MSDC_PB1_RSVD20 | MSDC_PB1_AUTO_SYNCST_CLR | MSDC_PB1_MARK_POP_WATER;
/* Set low power DCM, use HCLK for GDMA, use MSDC CLK for everything else */
pb1_val |= MSDC_PB1_LP_DCM_EN | MSDC_PB1_RSVD3 |