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dmaengine updates for v6.15

Browse Source 
New support:
   - Microchip sama7d65 dma controller
   - Yaml conversion of atmel dma binding and Freescale Elo DMA Controller
     binding
 
  Core:
   - Remove device_prep_dma_imm_data() API as users are removed
   - Reduce scope of some less frequently used DMA request channel APIs with
     aim to cleanup these in future
 
  Updates:
   - Drop Fenghua Yu from idxd maintainers, as he changed jobs
   - AMD ptdma support for multiqueue and ae4dma deprecated PCI IDs removal
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Merge tag 'dmaengine-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine

Pull dmaengine updates from Vinod Koul:
 "The dmaengine subsystem updates for this cycle consist of a new driver
  (Microchip) along with couple of yaml binding conversions, core api
  updates and bunch of driver updates etc.

  New HW support:

   - Microchip sama7d65 dma controller

   - Yaml conversion of atmel dma binding and Freescale Elo DMA
     Controller binding

  Core:

   - Remove device_prep_dma_imm_data() API as users are removed

   - Reduce scope of some less frequently used DMA request channel APIs
     with aim to cleanup these in future

  Updates:

   - Drop Fenghua Yu from idxd maintainers, as he changed jobs

   - AMD ptdma support for multiqueue and ae4dma deprecated PCI IDs
     removal"

* tag 'dmaengine-6.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (29 commits)
  dmaengine: ptdma: Utilize the AE4DMA engine's multi-queue functionality
  dmaengine: ae4dma: Use the MSI count and its corresponding IRQ number
  dmaengine: ae4dma: Remove deprecated PCI IDs
  dmaengine: Remove device_prep_dma_imm_data from struct dma_device
  dmaengine: ti: edma: support sw triggered chans in of_edma_xlate()
  dmaengine: ti: k3-udma: Enable second resource range for BCDMA and PKTDMA
  dmaengine: fsl-edma: free irq correctly in remove path
  dmaengine: fsl-edma: cleanup chan after dma_async_device_unregister
  dt-bindings: dma: snps,dw-axi-dmac: Allow devices to be marked as noncoherent
  dmaengine: dmatest: Fix dmatest waiting less when interrupted
  dt-bindings: dma: Convert fsl,elo*-dma to YAML
  dt-bindings: dma: fsl-mxs-dma: Add compatible string for i.MX8 chips
  dmaengine: Fix typo in comment
  dmaengine: ti: k3-udma-glue: Drop skip_fdq argument from k3_udma_glue_reset_rx_chn
  dmaengine: bcm2835-dma: fix warning when CONFIG_PM=n
  dt-bindings: dma: fsl,edma: Add i.MX94 support
  dt-bindings: dma: atmel: add microchip,sama7d65-dma
  dmaengine: img-mdc: remove incorrect of_match_ptr annotation
  dmaengine: idxd: Delete unnecessary NULL check
  dmaengine: pxa: Enable compile test
  ...
This commit is contained in:
Linus Torvalds 2025-04-01 12:57:14 -07:00
commit 91e5bfe317
37 changed files with 682 additions and 319 deletions
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68
Documentation/devicetree/bindings/dma/atmel,at91sam9g45-dma.yaml Normal file
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@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/atmel,at91sam9g45-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel Direct Memory Access Controller (DMA)
maintainers:
- Ludovic Desroches <ludovic.desroches@microchip.com>
description:
The Atmel Direct Memory Access Controller (DMAC) transfers data from a source
peripheral to a destination peripheral over one or more AMBA buses. One channel
is required for each source/destination pair. In the most basic configuration,
the DMAC has one master interface and one channel. The master interface reads
the data from a source and writes it to a destination. Two AMBA transfers are
required for each DMAC data transfer. This is also known as a dual-access transfer.
The DMAC is programmed via the APB interface.
properties:
compatible:
enum:
- atmel,at91sam9g45-dma
- atmel,at91sam9rl-dma
reg:
maxItems: 1
interrupts:
maxItems: 1
"#dma-cells":
description:
Must be <2>, used to represent the number of integer cells in the dma
property of client devices. The two cells in order are
1. The first cell represents the channel number.
2. The second cell is 0 for RX and 1 for TX transfers.
const: 2
clocks:
maxItems: 1
clock-names:
const: dma_clk
required:
- compatible
- reg
- interrupts
- "#dma-cells"
- clocks
- clock-names
additionalProperties: false
examples:
- |
dma-controller@ffffec00 {
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffec00 0x200>;
interrupts = <21>;
#dma-cells = <2>;
clocks = <&pmc 2 20>;
clock-names = "dma_clk";
};
...

3
Documentation/devicetree/bindings/dma/atmel,sama5d4-dma.yaml
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@ -32,6 +32,9 @@ properties:
- microchip,sam9x60-dma
- microchip,sam9x7-dma
- const: atmel,sama5d4-dma
- items:
- const: microchip,sama7d65-dma
- const: microchip,sama7g5-dma
"#dma-cells":
description: |

42
Documentation/devicetree/bindings/dma/atmel-dma.txt
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@ -1,42 +0,0 @@
* Atmel Direct Memory Access Controller (DMA)
Required properties:
- compatible: Should be "atmel,<chip>-dma".
- reg: Should contain DMA registers location and length.
- interrupts: Should contain DMA interrupt.
- #dma-cells: Must be <2>, used to represent the number of integer cells in
the dmas property of client devices.
Example:
dma0: dma@ffffec00 {
compatible = "atmel,at91sam9g45-dma";
reg = <0xffffec00 0x200>;
interrupts = <21>;
#dma-cells = <2>;
};
DMA clients connected to the Atmel DMA controller must use the format
described in the dma.txt file, using a three-cell specifier for each channel:
a phandle plus two integer cells.
The three cells in order are:
1. A phandle pointing to the DMA controller.
2. The memory interface (16 most significant bits), the peripheral interface
(16 less significant bits).
3. Parameters for the at91 DMA configuration register which are device
dependent:
- bit 7-0: peripheral identifier for the hardware handshaking interface. The
identifier can be different for tx and rx.
- bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 2 for ASAP.
Example:
i2c0@i2c@f8010000 {
compatible = "atmel,at91sam9x5-i2c";
reg = <0xf8010000 0x100>;
interrupts = <9 4 6>;
dmas = <&dma0 1 7>,
<&dma0 1 8>;
dma-names = "tx", "rx";
};

8
Documentation/devicetree/bindings/dma/fsl,edma.yaml
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@ -27,6 +27,14 @@ properties:
- fsl,imx93-edma4
- fsl,imx95-edma5
- nxp,s32g2-edma
- items:
- enum:
- fsl,imx94-edma3
- const: fsl,imx93-edma3
- items:
- enum:
- fsl,imx94-edma5
- const: fsl,imx95-edma5
- items:
- const: fsl,ls1028a-edma
- const: fsl,vf610-edma

137
Documentation/devicetree/bindings/dma/fsl,elo-dma.yaml Normal file
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@ -0,0 +1,137 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/fsl,elo-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Elo DMA Controller
maintainers:
- J. Neuschäfer <j.ne@posteo.net>
description:
This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
series chips such as mpc8315, mpc8349, mpc8379 etc.
properties:
compatible:
items:
- enum:
- fsl,mpc8313-dma
- fsl,mpc8315-dma
- fsl,mpc8323-dma
- fsl,mpc8347-dma
- fsl,mpc8349-dma
- fsl,mpc8360-dma
- fsl,mpc8377-dma
- fsl,mpc8378-dma
- fsl,mpc8379-dma
- const: fsl,elo-dma
reg:
items:
- description:
DMA General Status Register, i.e. DGSR which contains status for
all the 4 DMA channels.
cell-index:
$ref: /schemas/types.yaml#/definitions/uint32
description: Controller index. 0 for controller @ 0x8100.
ranges: true
"#address-cells":
const: 1
"#size-cells":
const: 1
interrupts:
maxItems: 1
description: Controller interrupt.
required:
- compatible
- reg
patternProperties:
"^dma-channel@[0-9a-f]+$":
type: object
additionalProperties: false
properties:
compatible:
oneOf:
# native DMA channel
- items:
- enum:
- fsl,mpc8315-dma-channel
- fsl,mpc8323-dma-channel
- fsl,mpc8347-dma-channel
- fsl,mpc8349-dma-channel
- fsl,mpc8360-dma-channel
- fsl,mpc8377-dma-channel
- fsl,mpc8378-dma-channel
- fsl,mpc8379-dma-channel
- const: fsl,elo-dma-channel
# audio DMA channel, see fsl,ssi.yaml
- const: fsl,ssi-dma-channel
reg:
maxItems: 1
cell-index:
description: DMA channel index starts at 0.
interrupts:
maxItems: 1
description:
Per-channel interrupt. Only necessary if no controller interrupt has
been provided.
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
dma@82a8 {
compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
reg = <0x82a8 4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8100 0x1a4>;
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
reg = <0 0x80>;
cell-index = <0>;
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
};
dma-channel@80 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
};
dma-channel@100 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
};
dma-channel@180 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupts = <71 IRQ_TYPE_LEVEL_LOW>;
};
};
...

125
Documentation/devicetree/bindings/dma/fsl,elo3-dma.yaml Normal file
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@ -0,0 +1,125 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/fsl,elo3-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Elo3 DMA Controller
maintainers:
- J. Neuschäfer <j.ne@posteo.net>
description:
DMA controller which has same function as EloPlus except that Elo3 has 8
channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx
series chips, such as t1040, t4240, b4860.
properties:
compatible:
const: fsl,elo3-dma
reg:
items:
- description:
DMA General Status Registers starting from DGSR0, for channel 1~4
- description:
DMA General Status Registers starting from DGSR1, for channel 5~8
ranges: true
"#address-cells":
const: 1
"#size-cells":
const: 1
interrupts:
maxItems: 1
patternProperties:
"^dma-channel@[0-9a-f]+$":
type: object
additionalProperties: false
properties:
compatible:
enum:
# native DMA channel
- fsl,eloplus-dma-channel
# audio DMA channel, see fsl,ssi.yaml
- fsl,ssi-dma-channel
reg:
maxItems: 1
interrupts:
maxItems: 1
description:
Per-channel interrupt. Only necessary if no controller interrupt has
been provided.
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
dma@100300 {
compatible = "fsl,elo3-dma";
reg = <0x100300 0x4>,
<0x100600 0x4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x100100 0x500>;
dma-channel@0 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
interrupts = <28 IRQ_TYPE_EDGE_FALLING 0 0>;
};
dma-channel@80 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
interrupts = <29 IRQ_TYPE_EDGE_FALLING 0 0>;
};
dma-channel@100 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
interrupts = <30 IRQ_TYPE_EDGE_FALLING 0 0>;
};
dma-channel@180 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
interrupts = <31 IRQ_TYPE_EDGE_FALLING 0 0>;
};
dma-channel@300 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x300 0x80>;
interrupts = <76 IRQ_TYPE_EDGE_FALLING 0 0>;
};
dma-channel@380 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x380 0x80>;
interrupts = <77 IRQ_TYPE_EDGE_FALLING 0 0>;
};
dma-channel@400 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x400 0x80>;
interrupts = <78 IRQ_TYPE_EDGE_FALLING 0 0>;
};
dma-channel@480 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x480 0x80>;
interrupts = <79 IRQ_TYPE_EDGE_FALLING 0 0>;
};
};
...

132
Documentation/devicetree/bindings/dma/fsl,eloplus-dma.yaml Normal file
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@ -0,0 +1,132 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/fsl,eloplus-dma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale EloPlus DMA Controller
maintainers:
- J. Neuschäfer <j.ne@posteo.net>
description:
This is a 4-channel DMA controller with extended addresses and chaining,
mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as
mpc8540, mpc8641 p4080, bsc9131 etc.
properties:
compatible:
oneOf:
- items:
- enum:
- fsl,mpc8540-dma
- fsl,mpc8541-dma
- fsl,mpc8548-dma
- fsl,mpc8555-dma
- fsl,mpc8560-dma
- fsl,mpc8572-dma
- fsl,mpc8641-dma
- const: fsl,eloplus-dma
- const: fsl,eloplus-dma
reg:
items:
- description:
DMA General Status Register, i.e. DGSR which contains
status for all the 4 DMA channels
cell-index:
$ref: /schemas/types.yaml#/definitions/uint32
description:
controller index. 0 for controller @ 0x21000, 1 for controller @ 0xc000
ranges: true
"#address-cells":
const: 1
"#size-cells":
const: 1
interrupts:
maxItems: 1
description: Controller interrupt.
patternProperties:
"^dma-channel@[0-9a-f]+$":
type: object
additionalProperties: false
properties:
compatible:
oneOf:
# native DMA channel
- items:
- enum:
- fsl,mpc8540-dma-channel
- fsl,mpc8541-dma-channel
- fsl,mpc8548-dma-channel
- fsl,mpc8555-dma-channel
- fsl,mpc8560-dma-channel
- fsl,mpc8572-dma-channel
- const: fsl,eloplus-dma-channel
# audio DMA channel, see fsl,ssi.yaml
- const: fsl,ssi-dma-channel
reg:
maxItems: 1
cell-index:
description: DMA channel index starts at 0.
interrupts:
maxItems: 1
description:
Per-channel interrupt. Only necessary if no controller interrupt has
been provided.
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
dma@21300 {
compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
reg = <0x21300 4>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
reg = <0 0x80>;
cell-index = <0>;
interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
};
dma-channel@80 {
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
};
dma-channel@100 {
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupts = <22 IRQ_TYPE_EDGE_FALLING>;
};
dma-channel@180 {
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupts = <23 IRQ_TYPE_EDGE_FALLING>;
};
};
...

6
Documentation/devicetree/bindings/dma/fsl,mxs-dma.yaml
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@ -31,6 +31,12 @@ properties:
- fsl,imx6q-dma-apbh
- fsl,imx6sx-dma-apbh
- fsl,imx7d-dma-apbh
- fsl,imx8dxl-dma-apbh
- fsl,imx8mm-dma-apbh
- fsl,imx8mn-dma-apbh
- fsl,imx8mp-dma-apbh
- fsl,imx8mq-dma-apbh
- fsl,imx8qm-dma-apbh
- fsl,imx8qxp-dma-apbh
- const: fsl,imx28-dma-apbh
- enum:

2
Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
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@ -59,6 +59,8 @@ properties:
minimum: 1
maximum: 8
dma-noncoherent: true
resets:
minItems: 1
maxItems: 2

204
Documentation/devicetree/bindings/powerpc/fsl/dma.txt
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@ -1,204 +0,0 @@
* Freescale DMA Controllers
** Freescale Elo DMA Controller
This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
series chips such as mpc8315, mpc8349, mpc8379 etc.
Required properties:
- compatible : must include "fsl,elo-dma"
- reg : DMA General Status Register, i.e. DGSR which contains
status for all the 4 DMA channels
- ranges : describes the mapping between the address space of the
DMA channels and the address space of the DMA controller
- cell-index : controller index. 0 for controller @ 0x8100
- interrupts : interrupt specifier for DMA IRQ
- DMA channel nodes:
- compatible : must include "fsl,elo-dma-channel"
However, see note below.
- reg : DMA channel specific registers
- cell-index : DMA channel index starts at 0.
Optional properties:
- interrupts : interrupt specifier for DMA channel IRQ
(on 83xx this is expected to be identical to
the interrupts property of the parent node)
Example:
dma@82a8 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
reg = <0x82a8 4>;
ranges = <0 0x8100 0x1a4>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
cell-index = <0>;
reg = <0 0x80>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@80 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
cell-index = <1>;
reg = <0x80 0x80>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@100 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
cell-index = <2>;
reg = <0x100 0x80>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
dma-channel@180 {
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
cell-index = <3>;
reg = <0x180 0x80>;
interrupt-parent = <&ipic>;
interrupts = <71 8>;
};
};
** Freescale EloPlus DMA Controller
This is a 4-channel DMA controller with extended addresses and chaining,
mainly used in Freescale mpc85xx/86xx, Pxxx and BSC series chips, such as
mpc8540, mpc8641 p4080, bsc9131 etc.
Required properties:
- compatible : must include "fsl,eloplus-dma"
- reg : DMA General Status Register, i.e. DGSR which contains
status for all the 4 DMA channels
- cell-index : controller index. 0 for controller @ 0x21000,
1 for controller @ 0xc000
- ranges : describes the mapping between the address space of the
DMA channels and the address space of the DMA controller
- DMA channel nodes:
- compatible : must include "fsl,eloplus-dma-channel"
However, see note below.
- cell-index : DMA channel index starts at 0.
- reg : DMA channel specific registers
- interrupts : interrupt specifier for DMA channel IRQ
Example:
dma@21300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
reg = <0x21300 4>;
ranges = <0 0x21100 0x200>;
cell-index = <0>;
dma-channel@0 {
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
reg = <0 0x80>;
cell-index = <0>;
interrupt-parent = <&mpic>;
interrupts = <20 2>;
};
dma-channel@80 {
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
cell-index = <1>;
interrupt-parent = <&mpic>;
interrupts = <21 2>;
};
dma-channel@100 {
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
cell-index = <2>;
interrupt-parent = <&mpic>;
interrupts = <22 2>;
};
dma-channel@180 {
compatible = "fsl,mpc8540-dma-channel", "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
cell-index = <3>;
interrupt-parent = <&mpic>;
interrupts = <23 2>;
};
};
** Freescale Elo3 DMA Controller
DMA controller which has same function as EloPlus except that Elo3 has 8
channels while EloPlus has only 4, it is used in Freescale Txxx and Bxxx
series chips, such as t1040, t4240, b4860.
Required properties:
- compatible : must include "fsl,elo3-dma"
- reg : contains two entries for DMA General Status Registers,
i.e. DGSR0 which includes status for channel 1~4, and
DGSR1 for channel 5~8
- ranges : describes the mapping between the address space of the
DMA channels and the address space of the DMA controller
- DMA channel nodes:
- compatible : must include "fsl,eloplus-dma-channel"
- reg : DMA channel specific registers
- interrupts : interrupt specifier for DMA channel IRQ
Example:
dma@100300 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,elo3-dma";
reg = <0x100300 0x4>,
<0x100600 0x4>;
ranges = <0x0 0x100100 0x500>;
dma-channel@0 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x0 0x80>;
interrupts = <28 2 0 0>;
};
dma-channel@80 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x80 0x80>;
interrupts = <29 2 0 0>;
};
dma-channel@100 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x100 0x80>;
interrupts = <30 2 0 0>;
};
dma-channel@180 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x180 0x80>;
interrupts = <31 2 0 0>;
};
dma-channel@300 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x300 0x80>;
interrupts = <76 2 0 0>;
};
dma-channel@380 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x380 0x80>;
interrupts = <77 2 0 0>;
};
dma-channel@400 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x400 0x80>;
interrupts = <78 2 0 0>;
};
dma-channel@480 {
compatible = "fsl,eloplus-dma-channel";
reg = <0x480 0x80>;
interrupts = <79 2 0 0>;
};
};
Note on DMA channel compatible properties: The compatible property must say
"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel" to be used by the Elo DMA
driver (fsldma). Any DMA channel used by fsldma cannot be used by another
DMA driver, such as the SSI sound drivers for the MPC8610. Therefore, any DMA
channel that should be used for another driver should not use
"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel". For the SSI drivers, for
example, the compatible property should be "fsl,ssi-dma-channel". See ssi.txt
for more information.

4
MAINTAINERS
View File

@ -11968,7 +11968,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git
F: drivers/idle/intel_idle.c
INTEL IDXD DRIVER
M: Fenghua Yu <fenghua.yu@intel.com>
M: Vinicius Costa Gomes <vinicius.gomes@intel.com>
R: Dave Jiang <dave.jiang@intel.com>
L: dmaengine@vger.kernel.org
S: Supported
@ -15648,7 +15648,7 @@ M: Ludovic Desroches <ludovic.desroches@microchip.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: dmaengine@vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/dma/atmel-dma.txt
F: Documentation/devicetree/bindings/dma/atmel,at91sam9g45-dma.yaml
F: drivers/dma/at_hdmac.c
F: drivers/dma/at_xdmac.c
F: include/dt-bindings/dma/at91.h

2
drivers/dma/Kconfig
View File

@ -546,7 +546,7 @@ config PL330_DMA
config PXA_DMA
bool "PXA DMA support"
depends on (ARCH_MMP || ARCH_PXA)
depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST
select DMA_ENGINE
select DMA_VIRTUAL_CHANNELS
help

6
drivers/dma/amd/ae4dma/ae4dma-pci.c
View File

@ -46,8 +46,8 @@ static int ae4_get_irqs(struct ae4_device *ae4)
} else {
ae4_msix->msix_count = ret;
for (i = 0; i < MAX_AE4_HW_QUEUES; i++)
ae4->ae4_irq[i] = ae4_msix->msix_entry[i].vector;
for (i = 0; i < ae4_msix->msix_count; i++)
ae4->ae4_irq[i] = pci_irq_vector(pdev, i);
}
return ret;
@ -137,8 +137,6 @@ static void ae4_pci_remove(struct pci_dev *pdev)
}
static const struct pci_device_id ae4_pci_table[] = {
{ PCI_VDEVICE(AMD, 0x14C8), },
{ PCI_VDEVICE(AMD, 0x14DC), },
{ PCI_VDEVICE(AMD, 0x149B), },
/* Last entry must be zero */
{ 0, }

2
drivers/dma/amd/ae4dma/ae4dma.h
View File

@ -37,6 +37,8 @@
#define AE4_DMA_VERSION 4
#define CMD_AE4_DESC_DW0_VAL 2
#define AE4_TIME_OUT 5000
struct ae4_msix {
int msix_count;
struct msix_entry msix_entry[MAX_AE4_HW_QUEUES];

90
drivers/dma/amd/ptdma/ptdma-dmaengine.c
View File

@ -198,8 +198,10 @@ static struct pt_dma_desc *pt_handle_active_desc(struct pt_dma_chan *chan,
{
struct dma_async_tx_descriptor *tx_desc;
struct virt_dma_desc *vd;
struct pt_device *pt;
unsigned long flags;
pt = chan->pt;
/* Loop over descriptors until one is found with commands */
do {
if (desc) {
@ -217,7 +219,7 @@ static struct pt_dma_desc *pt_handle_active_desc(struct pt_dma_chan *chan,
spin_lock_irqsave(&chan->vc.lock, flags);
if (desc) {
if (pt->ver != AE4_DMA_VERSION && desc) {
if (desc->status != DMA_COMPLETE) {
if (desc->status != DMA_ERROR)
desc->status = DMA_COMPLETE;
@ -235,7 +237,7 @@ static struct pt_dma_desc *pt_handle_active_desc(struct pt_dma_chan *chan,
spin_unlock_irqrestore(&chan->vc.lock, flags);
if (tx_desc) {
if (pt->ver != AE4_DMA_VERSION && tx_desc) {
dmaengine_desc_get_callback_invoke(tx_desc, NULL);
dma_run_dependencies(tx_desc);
vchan_vdesc_fini(vd);
@ -245,11 +247,25 @@ static struct pt_dma_desc *pt_handle_active_desc(struct pt_dma_chan *chan,
return NULL;
}
static inline bool ae4_core_queue_full(struct pt_cmd_queue *cmd_q)
{
u32 front_wi = readl(cmd_q->reg_control + AE4_WR_IDX_OFF);
u32 rear_ri = readl(cmd_q->reg_control + AE4_RD_IDX_OFF);
if (((MAX_CMD_QLEN + front_wi - rear_ri) % MAX_CMD_QLEN) >= (MAX_CMD_QLEN - 1))
return true;
return false;
}
static void pt_cmd_callback(void *data, int err)
{
struct pt_dma_desc *desc = data;
struct ae4_cmd_queue *ae4cmd_q;
struct dma_chan *dma_chan;
struct pt_dma_chan *chan;
struct ae4_device *ae4;
struct pt_device *pt;
int ret;
if (err == -EINPROGRESS)
@ -257,11 +273,32 @@ static void pt_cmd_callback(void *data, int err)
dma_chan = desc->vd.tx.chan;
chan = to_pt_chan(dma_chan);
pt = chan->pt;
if (err)
desc->status = DMA_ERROR;
while (true) {
if (pt->ver == AE4_DMA_VERSION) {
ae4 = container_of(pt, struct ae4_device, pt);
ae4cmd_q = &ae4->ae4cmd_q[chan->id];
if (ae4cmd_q->q_cmd_count >= (CMD_Q_LEN - 1) ||
ae4_core_queue_full(&ae4cmd_q->cmd_q)) {
wake_up(&ae4cmd_q->q_w);
if (wait_for_completion_timeout(&ae4cmd_q->cmp,
msecs_to_jiffies(AE4_TIME_OUT))
== 0) {
dev_err(pt->dev, "TIMEOUT %d:\n", ae4cmd_q->id);
break;
}
reinit_completion(&ae4cmd_q->cmp);
continue;
}
}
/* Check for DMA descriptor completion */
desc = pt_handle_active_desc(chan, desc);
@ -296,6 +333,49 @@ static struct pt_dma_desc *pt_alloc_dma_desc(struct pt_dma_chan *chan,
return desc;
}
static void pt_cmd_callback_work(void *data, int err)
{
struct dma_async_tx_descriptor *tx_desc;
struct pt_dma_desc *desc = data;
struct dma_chan *dma_chan;
struct virt_dma_desc *vd;
struct pt_dma_chan *chan;
unsigned long flags;
dma_chan = desc->vd.tx.chan;
chan = to_pt_chan(dma_chan);
if (err == -EINPROGRESS)
return;
tx_desc = &desc->vd.tx;
vd = &desc->vd;
if (err)
desc->status = DMA_ERROR;
spin_lock_irqsave(&chan->vc.lock, flags);
if (desc) {
if (desc->status != DMA_COMPLETE) {
if (desc->status != DMA_ERROR)
desc->status = DMA_COMPLETE;
dma_cookie_complete(tx_desc);
dma_descriptor_unmap(tx_desc);
} else {
tx_desc = NULL;
}
}
spin_unlock_irqrestore(&chan->vc.lock, flags);
if (tx_desc) {
dmaengine_desc_get_callback_invoke(tx_desc, NULL);
dma_run_dependencies(tx_desc);
list_del(&desc->vd.node);
vchan_vdesc_fini(vd);
}
}
static struct pt_dma_desc *pt_create_desc(struct dma_chan *dma_chan,
dma_addr_t dst,
dma_addr_t src,
@ -327,6 +407,7 @@ static struct pt_dma_desc *pt_create_desc(struct dma_chan *dma_chan,
desc->len = len;
if (pt->ver == AE4_DMA_VERSION) {
pt_cmd->pt_cmd_callback = pt_cmd_callback_work;
ae4 = container_of(pt, struct ae4_device, pt);
ae4cmd_q = &ae4->ae4cmd_q[chan->id];
mutex_lock(&ae4cmd_q->cmd_lock);
@ -367,13 +448,16 @@ static void pt_issue_pending(struct dma_chan *dma_chan)
{
struct pt_dma_chan *chan = to_pt_chan(dma_chan);
struct pt_dma_desc *desc;
struct pt_device *pt;
unsigned long flags;
bool engine_is_idle = true;
pt = chan->pt;
spin_lock_irqsave(&chan->vc.lock, flags);
desc = pt_next_dma_desc(chan);
if (desc)
if (desc && pt->ver != AE4_DMA_VERSION)
engine_is_idle = false;
vchan_issue_pending(&chan->vc);

2
drivers/dma/bcm2835-dma.c
View File

@ -893,7 +893,7 @@ static int bcm2835_dma_suspend_late(struct device *dev)
}
static const struct dev_pm_ops bcm2835_dma_pm_ops = {
SET_LATE_SYSTEM_SLEEP_PM_OPS(bcm2835_dma_suspend_late, NULL)
LATE_SYSTEM_SLEEP_PM_OPS(bcm2835_dma_suspend_late, NULL)
};
static int bcm2835_dma_probe(struct platform_device *pdev)

16
drivers/dma/dmaengine.c
View File

@ -40,6 +40,8 @@
#include <linux/dmaengine.h>
#include <linux/hardirq.h>
#include <linux/spinlock.h>
#include <linux/of.h>
#include <linux/property.h>
#include <linux/percpu.h>
#include <linux/rcupdate.h>
#include <linux/mutex.h>
@ -812,15 +814,13 @@ static const struct dma_slave_map *dma_filter_match(struct dma_device *device,
*/
struct dma_chan *dma_request_chan(struct device *dev, const char *name)
{
struct fwnode_handle *fwnode = dev_fwnode(dev);
struct dma_device *d, *_d;
struct dma_chan *chan = NULL;
/* If device-tree is present get slave info from here */
if (dev->of_node)
chan = of_dma_request_slave_channel(dev->of_node, name);
/* If device was enumerated by ACPI get slave info from here */
if (has_acpi_companion(dev) && !chan)
if (is_of_node(fwnode))
chan = of_dma_request_slave_channel(to_of_node(fwnode), name);
else if (is_acpi_device_node(fwnode))
chan = acpi_dma_request_slave_chan_by_name(dev, name);
if (PTR_ERR(chan) == -EPROBE_DEFER)
@ -854,8 +854,8 @@ struct dma_chan *dma_request_chan(struct device *dev, const char *name)
found:
#ifdef CONFIG_DEBUG_FS
chan->dbg_client_name = kasprintf(GFP_KERNEL, "%s:%s", dev_name(dev),
name);
chan->dbg_client_name = kasprintf(GFP_KERNEL, "%s:%s", dev_name(dev), name);
/* No functional issue if it fails, users are supposed to test before use */
#endif
chan->name = kasprintf(GFP_KERNEL, "dma:%s", name);

6
drivers/dma/dmatest.c
View File

@ -841,9 +841,9 @@ static int dmatest_func(void *data)
} else {
dma_async_issue_pending(chan);
wait_event_freezable_timeout(thread->done_wait,
done->done,
msecs_to_jiffies(params->timeout));
wait_event_timeout(thread->done_wait,
done->done,
msecs_to_jiffies(params->timeout));
status = dma_async_is_tx_complete(chan, cookie, NULL,
NULL);

6
drivers/dma/dw-edma/dw-edma-core.c
View File

@ -15,6 +15,7 @@
#include <linux/irq.h>
#include <linux/dma/edma.h>
#include <linux/dma-mapping.h>
#include <linux/string_choices.h>
#include "dw-edma-core.h"
#include "dw-edma-v0-core.h"
@ -746,7 +747,7 @@ static int dw_edma_channel_setup(struct dw_edma *dw, u32 wr_alloc, u32 rd_alloc)
chan->ll_max -= 1;
dev_vdbg(dev, "L. List:\tChannel %s[%u] max_cnt=%u\n",
chan->dir == EDMA_DIR_WRITE ? "write" : "read",
str_write_read(chan->dir == EDMA_DIR_WRITE),
chan->id, chan->ll_max);
if (dw->nr_irqs == 1)
@ -767,7 +768,8 @@ static int dw_edma_channel_setup(struct dw_edma *dw, u32 wr_alloc, u32 rd_alloc)
memcpy(&chan->msi, &irq->msi, sizeof(chan->msi));
dev_vdbg(dev, "MSI:\t\tChannel %s[%u] addr=0x%.8x%.8x, data=0x%.8x\n",
chan->dir == EDMA_DIR_WRITE ? "write" : "read", chan->id,
str_write_read(chan->dir == EDMA_DIR_WRITE),
chan->id,
chan->msi.address_hi, chan->msi.address_lo,
chan->msi.data);

8
drivers/dma/dw/pci.c
View File

@ -76,8 +76,6 @@ static void dw_pci_remove(struct pci_dev *pdev)
dev_warn(&pdev->dev, "can't remove device properly: %d\n", ret);
}
#ifdef CONFIG_PM_SLEEP
static int dw_pci_suspend_late(struct device *dev)
{
struct dw_dma_chip_pdata *data = dev_get_drvdata(dev);
@ -94,10 +92,8 @@ static int dw_pci_resume_early(struct device *dev)
return do_dw_dma_enable(chip);
};
#endif /* CONFIG_PM_SLEEP */
static const struct dev_pm_ops dw_pci_dev_pm_ops = {
SET_LATE_SYSTEM_SLEEP_PM_OPS(dw_pci_suspend_late, dw_pci_resume_early)
LATE_SYSTEM_SLEEP_PM_OPS(dw_pci_suspend_late, dw_pci_resume_early)
};
static const struct pci_device_id dw_pci_id_table[] = {
@ -136,7 +132,7 @@ static struct pci_driver dw_pci_driver = {
.probe = dw_pci_probe,
.remove = dw_pci_remove,
.driver = {
.pm = &dw_pci_dev_pm_ops,
.pm = pm_sleep_ptr(&dw_pci_dev_pm_ops),
},
};

8
drivers/dma/dw/platform.c
View File

@ -157,8 +157,6 @@ static const struct acpi_device_id dw_dma_acpi_id_table[] = {
MODULE_DEVICE_TABLE(acpi, dw_dma_acpi_id_table);
#endif
#ifdef CONFIG_PM_SLEEP
static int dw_suspend_late(struct device *dev)
{
struct dw_dma_chip_pdata *data = dev_get_drvdata(dev);
@ -183,10 +181,8 @@ static int dw_resume_early(struct device *dev)
return do_dw_dma_enable(chip);
}
#endif /* CONFIG_PM_SLEEP */
static const struct dev_pm_ops dw_dev_pm_ops = {
SET_LATE_SYSTEM_SLEEP_PM_OPS(dw_suspend_late, dw_resume_early)
LATE_SYSTEM_SLEEP_PM_OPS(dw_suspend_late, dw_resume_early)
};
static struct platform_driver dw_driver = {
@ -195,7 +191,7 @@ static struct platform_driver dw_driver = {
.shutdown = dw_shutdown,
.driver = {
.name = DRV_NAME,
.pm = &dw_dev_pm_ops,
.pm = pm_sleep_ptr(&dw_dev_pm_ops),
.of_match_table = of_match_ptr(dw_dma_of_id_table),
.acpi_match_table = ACPI_PTR(dw_dma_acpi_id_table),
},

18
drivers/dma/fsl-edma-main.c
View File

@ -164,7 +164,7 @@ static bool fsl_edma_srcid_in_use(struct fsl_edma_engine *fsl_edma, u32 srcid)
fsl_chan = &fsl_edma->chans[i];
if (fsl_chan->srcid && srcid == fsl_chan->srcid) {
dev_err(&fsl_chan->pdev->dev, "The srcid is in use, can't use!");
dev_err(&fsl_chan->pdev->dev, "The srcid is in use, can't use!\n");
return true;
}
}
@ -401,6 +401,7 @@ fsl_edma2_irq_init(struct platform_device *pdev,
/* The last IRQ is for eDMA err */
if (i == count - 1) {
fsl_edma->errirq = irq;
ret = devm_request_irq(&pdev->dev, irq,
fsl_edma_err_handler,
0, "eDMA2-ERR", fsl_edma);
@ -420,10 +421,13 @@ static void fsl_edma_irq_exit(
struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
{
if (fsl_edma->txirq == fsl_edma->errirq) {
devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
if (fsl_edma->txirq >= 0)
devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
} else {
devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma);
if (fsl_edma->txirq >= 0)
devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
if (fsl_edma->errirq >= 0)
devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma);
}
}
@ -620,6 +624,8 @@ static int fsl_edma_probe(struct platform_device *pdev)
if (!fsl_edma)
return -ENOMEM;
fsl_edma->errirq = -EINVAL;
fsl_edma->txirq = -EINVAL;
fsl_edma->drvdata = drvdata;
fsl_edma->n_chans = chans;
mutex_init(&fsl_edma->fsl_edma_mutex);
@ -802,9 +808,9 @@ static void fsl_edma_remove(struct platform_device *pdev)
struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev);
fsl_edma_irq_exit(pdev, fsl_edma);
fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
of_dma_controller_free(np);
dma_async_device_unregister(&fsl_edma->dma_dev);
fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
}
@ -822,7 +828,7 @@ static int fsl_edma_suspend_late(struct device *dev)
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
/* Make sure chan is idle or will force disable. */
if (unlikely(fsl_chan->status == DMA_IN_PROGRESS)) {
dev_warn(dev, "WARN: There is non-idle channel.");
dev_warn(dev, "WARN: There is non-idle channel.\n");
fsl_edma_disable_request(fsl_chan);
fsl_edma_chan_mux(fsl_chan, 0, false);
}

3
drivers/dma/idxd/init.c
View File

@ -912,8 +912,7 @@ static void idxd_device_config_restore(struct idxd_device *idxd,
idxd->rdbuf_limit = idxd_saved->saved_idxd.rdbuf_limit;
if (saved_evl)
idxd->evl->size = saved_evl->size;
idxd->evl->size = saved_evl->size;
for (i = 0; i < idxd->max_groups; i++) {
struct idxd_group *saved_group, *group;

2
drivers/dma/img-mdc-dma.c
View File

@ -1073,7 +1073,7 @@ static struct platform_driver mdc_dma_driver = {
.driver = {
.name = "img-mdc-dma",
.pm = &img_mdc_pm_ops,
.of_match_table = of_match_ptr(mdc_dma_of_match),
.of_match_table = mdc_dma_of_match,
},
.probe = mdc_dma_probe,
.remove = mdc_dma_remove,

3
drivers/dma/imx-dma.c
View File

@ -17,6 +17,7 @@
#include <linux/device.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/string_choices.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/dmaengine.h>
@ -942,7 +943,7 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
" src_sgl=%s dst_sgl=%s numf=%zu frame_size=%zu\n", __func__,
imxdmac->channel, (unsigned long long)xt->src_start,
(unsigned long long) xt->dst_start,
xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
str_true_false(xt->src_sgl), str_true_false(xt->dst_sgl),
xt->numf, xt->frame_size);
if (list_empty(&imxdmac->ld_free) ||

5
drivers/dma/imx-sdma.c
View File

@ -1459,9 +1459,8 @@ static int sdma_alloc_chan_resources(struct dma_chan *chan)
* dmatest, thus create 'struct imx_dma_data mem_data' for this case.
* Please note in any other slave case, you have to setup chan->private
* with 'struct imx_dma_data' in your own filter function if you want to
* request dma channel by dma_request_channel() rather than
* dma_request_slave_channel(). Othwise, 'MEMCPY in case?' will appear
* to warn you to correct your filter function.
* request DMA channel by dma_request_channel(), otherwise, 'MEMCPY in
* case?' will appear to warn you to correct your filter function.
*/
if (!data) {
dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n");

4
drivers/dma/pxa_dma.c
View File

@ -10,6 +10,7 @@
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/string_choices.h>
#include <linux/dmaengine.h>
#include <linux/platform_device.h>
#include <linux/device.h>
@ -277,8 +278,7 @@ static int chan_state_show(struct seq_file *s, void *p)
seq_printf(s, "\tPriority : %s\n",
str_prio[(phy->idx & 0xf) / 4]);
seq_printf(s, "\tUnaligned transfer bit: %s\n",
_phy_readl_relaxed(phy, DALGN) & BIT(phy->idx) ?
"yes" : "no");
str_yes_no(_phy_readl_relaxed(phy, DALGN) & BIT(phy->idx)));
seq_printf(s, "\tDCSR = %08x (%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
dcsr, PXA_DCSR_STR(RUN), PXA_DCSR_STR(NODESC),
PXA_DCSR_STR(STOPIRQEN), PXA_DCSR_STR(EORIRQEN),

2
drivers/dma/sh/shdma-base.c
View File

@ -725,7 +725,7 @@ static struct dma_async_tx_descriptor *shdma_prep_dma_cyclic(
slave_addr = ops->slave_addr(schan);
/*
* Allocate the sg list dynamically as it would consumer too much stack
* Allocate the sg list dynamically as it would consume too much stack
* space.
*/
sgl = kmalloc_array(sg_len, sizeof(*sgl), GFP_KERNEL);

3
drivers/dma/sun6i-dma.c
View File

@ -19,6 +19,7 @@
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/slab.h>
#include <linux/string_choices.h>
#include <linux/types.h>
#include "virt-dma.h"
@ -553,7 +554,7 @@ static irqreturn_t sun6i_dma_interrupt(int irq, void *dev_id)
continue;
dev_dbg(sdev->slave.dev, "DMA irq status %s: 0x%x\n",
i ? "high" : "low", status);
str_high_low(i), status);
writel(status, sdev->base + DMA_IRQ_STAT(i));

11
drivers/dma/ti/edma.c
View File

@ -16,6 +16,7 @@
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/string_choices.h>
#include <linux/of.h>
#include <linux/of_dma.h>
#include <linux/of_irq.h>
@ -2047,7 +2048,7 @@ static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
dev_dbg(dev, "num_qchannels: %u\n", ecc->num_qchannels);
dev_dbg(dev, "num_slots: %u\n", ecc->num_slots);
dev_dbg(dev, "num_tc: %u\n", ecc->num_tc);
dev_dbg(dev, "chmap_exist: %s\n", ecc->chmap_exist ? "yes" : "no");
dev_dbg(dev, "chmap_exist: %s\n", str_yes_no(ecc->chmap_exist));
/* Nothing need to be done if queue priority is provided */
if (pdata->queue_priority_mapping)
@ -2258,8 +2259,12 @@ static struct dma_chan *of_edma_xlate(struct of_phandle_args *dma_spec,
return NULL;
out:
/* The channel is going to be used as HW synchronized */
echan->hw_triggered = true;
/*
* The channel is going to be HW synchronized, unless it was
* reserved as a memcpy channel
*/
echan->hw_triggered =
!edma_is_memcpy_channel(i, ecc->info->memcpy_channels);
return dma_get_slave_channel(chan);
}
#else

15
drivers/dma/ti/k3-udma-glue.c
View File

@ -84,6 +84,7 @@ struct k3_udma_glue_rx_channel {
struct k3_udma_glue_rx_flow *flows;
u32 flow_num;
u32 flows_ready;
bool single_fdq; /* one FDQ for all flows */
};
static void k3_udma_chan_dev_release(struct device *dev)
@ -970,10 +971,13 @@ k3_udma_glue_request_rx_chn_priv(struct device *dev, const char *name,
ep_cfg = rx_chn->common.ep_config;
if (xudma_is_pktdma(rx_chn->common.udmax))
if (xudma_is_pktdma(rx_chn->common.udmax)) {
rx_chn->udma_rchan_id = ep_cfg->mapped_channel_id;
else
rx_chn->single_fdq = false;
} else {
rx_chn->udma_rchan_id = -1;
rx_chn->single_fdq = true;
}
/* request and cfg UDMAP RX channel */
rx_chn->udma_rchanx = xudma_rchan_get(rx_chn->common.udmax,
@ -1103,6 +1107,9 @@ k3_udma_glue_request_remote_rx_chn_common(struct k3_udma_glue_rx_channel *rx_chn
rx_chn->common.chan_dev.dma_coherent = true;
dma_coerce_mask_and_coherent(&rx_chn->common.chan_dev,
DMA_BIT_MASK(48));
rx_chn->single_fdq = false;
} else {
rx_chn->single_fdq = true;
}
ret = k3_udma_glue_allocate_rx_flows(rx_chn, cfg);
@ -1453,7 +1460,7 @@ EXPORT_SYMBOL_GPL(k3_udma_glue_tdown_rx_chn);
void k3_udma_glue_reset_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
u32 flow_num, void *data,
void (*cleanup)(void *data, dma_addr_t desc_dma), bool skip_fdq)
void (*cleanup)(void *data, dma_addr_t desc_dma))
{
struct k3_udma_glue_rx_flow *flow = &rx_chn->flows[flow_num];
struct device *dev = rx_chn->common.dev;
@ -1465,7 +1472,7 @@ void k3_udma_glue_reset_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
dev_dbg(dev, "RX reset flow %u occ_rx %u\n", flow_num, occ_rx);
/* Skip RX FDQ in case one FDQ is used for the set of flows */
if (skip_fdq)
if (rx_chn->single_fdq && flow_num)
goto do_reset;
/*

36
drivers/dma/ti/k3-udma.c
View File

@ -4886,6 +4886,12 @@ static int bcdma_setup_resources(struct udma_dev *ud)
irq_res.desc[i].start = rm_res->desc[i].start +
oes->bcdma_bchan_ring;
irq_res.desc[i].num = rm_res->desc[i].num;
if (rm_res->desc[i].num_sec) {
irq_res.desc[i].start_sec = rm_res->desc[i].start_sec +
oes->bcdma_bchan_ring;
irq_res.desc[i].num_sec = rm_res->desc[i].num_sec;
}
}
}
} else {
@ -4909,6 +4915,15 @@ static int bcdma_setup_resources(struct udma_dev *ud)
irq_res.desc[i + 1].start = rm_res->desc[j].start +
oes->bcdma_tchan_ring;
irq_res.desc[i + 1].num = rm_res->desc[j].num;
if (rm_res->desc[j].num_sec) {
irq_res.desc[i].start_sec = rm_res->desc[j].start_sec +
oes->bcdma_tchan_data;
irq_res.desc[i].num_sec = rm_res->desc[j].num_sec;
irq_res.desc[i + 1].start_sec = rm_res->desc[j].start_sec +
oes->bcdma_tchan_ring;
irq_res.desc[i + 1].num_sec = rm_res->desc[j].num_sec;
}
}
}
}
@ -4929,6 +4944,15 @@ static int bcdma_setup_resources(struct udma_dev *ud)
irq_res.desc[i + 1].start = rm_res->desc[j].start +
oes->bcdma_rchan_ring;
irq_res.desc[i + 1].num = rm_res->desc[j].num;
if (rm_res->desc[j].num_sec) {
irq_res.desc[i].start_sec = rm_res->desc[j].start_sec +
oes->bcdma_rchan_data;
irq_res.desc[i].num_sec = rm_res->desc[j].num_sec;
irq_res.desc[i + 1].start_sec = rm_res->desc[j].start_sec +
oes->bcdma_rchan_ring;
irq_res.desc[i + 1].num_sec = rm_res->desc[j].num_sec;
}
}
}
}
@ -5063,6 +5087,12 @@ static int pktdma_setup_resources(struct udma_dev *ud)
irq_res.desc[i].start = rm_res->desc[i].start +
oes->pktdma_tchan_flow;
irq_res.desc[i].num = rm_res->desc[i].num;
if (rm_res->desc[i].num_sec) {
irq_res.desc[i].start_sec = rm_res->desc[i].start_sec +
oes->pktdma_tchan_flow;
irq_res.desc[i].num_sec = rm_res->desc[i].num_sec;
}
}
}
rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW];
@ -5074,6 +5104,12 @@ static int pktdma_setup_resources(struct udma_dev *ud)
irq_res.desc[i].start = rm_res->desc[j].start +
oes->pktdma_rchan_flow;
irq_res.desc[i].num = rm_res->desc[j].num;
if (rm_res->desc[j].num_sec) {
irq_res.desc[i].start_sec = rm_res->desc[j].start_sec +
oes->pktdma_rchan_flow;
irq_res.desc[i].num_sec = rm_res->desc[j].num_sec;
}
}
}
ret = ti_sci_inta_msi_domain_alloc_irqs(ud->dev, &irq_res);

3
drivers/dma/xilinx/xilinx_dma.c
View File

@ -46,6 +46,7 @@
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/string_choices.h>
#include <linux/clk.h>
#include <linux/io-64-nonatomic-lo-hi.h>
@ -2940,7 +2941,7 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
XILINX_DMA_DMASR_SG_MASK)
chan->has_sg = true;
dev_dbg(chan->dev, "ch %d: SG %s\n", chan->id,
chan->has_sg ? "enabled" : "disabled");
str_enabled_disabled(chan->has_sg));
}
/* Initialize the tasklet */

4
drivers/net/ethernet/ti/am65-cpsw-nuss.c
View File

@ -516,7 +516,7 @@ static void am65_cpsw_destroy_rxq(struct am65_cpsw_common *common, int id)
napi_disable(&flow->napi_rx);
hrtimer_cancel(&flow->rx_hrtimer);
k3_udma_glue_reset_rx_chn(rx_chn->rx_chn, id, rx_chn,
am65_cpsw_nuss_rx_cleanup, !!id);
am65_cpsw_nuss_rx_cleanup);
for (port = 0; port < common->port_num; port++) {
if (!common->ports[port].ndev)
@ -3332,7 +3332,7 @@ static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common)
for (i = 0; i < common->rx_ch_num_flows; i++)
k3_udma_glue_reset_rx_chn(rx_chan->rx_chn, i,
rx_chan,
am65_cpsw_nuss_rx_cleanup, !!i);
am65_cpsw_nuss_rx_cleanup);
k3_udma_glue_disable_rx_chn(rx_chan->rx_chn);

2
drivers/net/ethernet/ti/icssg/icssg_common.c
View File

@ -1212,7 +1212,7 @@ void prueth_reset_rx_chan(struct prueth_rx_chn *chn,
for (i = 0; i < num_flows; i++)
k3_udma_glue_reset_rx_chn(chn->rx_chn, i, chn,
prueth_rx_cleanup, !!i);
prueth_rx_cleanup);
if (disable)
k3_udma_glue_disable_rx_chn(chn->rx_chn);

3
include/linux/dma/k3-udma-glue.h
View File

@ -138,8 +138,7 @@ int k3_udma_glue_rx_get_irq(struct k3_udma_glue_rx_channel *rx_chn,
u32 flow_num);
void k3_udma_glue_reset_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
u32 flow_num, void *data,
void (*cleanup)(void *data, dma_addr_t desc_dma),
bool skip_fdq);
void (*cleanup)(void *data, dma_addr_t desc_dma));
int k3_udma_glue_rx_flow_enable(struct k3_udma_glue_rx_channel *rx_chn,
u32 flow_idx);
int k3_udma_glue_rx_flow_disable(struct k3_udma_glue_rx_channel *rx_chn,

10
include/linux/dmaengine.h
View File

@ -839,7 +839,6 @@ struct dma_filter {
* The function takes a buffer of size buf_len. The callback function will
* be called after period_len bytes have been transferred.
* @device_prep_interleaved_dma: Transfer expression in a generic way.
* @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
* @device_caps: May be used to override the generic DMA slave capabilities
* with per-channel specific ones
* @device_config: Pushes a new configuration to a channel, return 0 or an error
@ -942,9 +941,6 @@ struct dma_device {
struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
struct dma_chan *chan, struct dma_interleaved_template *xt,
unsigned long flags);
struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)(
struct dma_chan *chan, dma_addr_t dst, u64 data,
unsigned long flags);
void (*device_caps)(struct dma_chan *chan, struct dma_slave_caps *caps);
int (*device_config)(struct dma_chan *chan, struct dma_slave_config *config);
@ -1639,14 +1635,14 @@ static inline struct dma_chan
{
struct dma_chan *chan;
chan = dma_request_slave_channel(dev, name);
if (chan)
chan = dma_request_chan(dev, name);
if (!IS_ERR(chan))
return chan;
if (!fn || !fn_param)
return NULL;
return __dma_request_channel(&mask, fn, fn_param, NULL);
return dma_request_channel(mask, fn, fn_param);
}
static inline char *