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ARM: dts: aspeed-g6: Add nodes for i3c controllers

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Add the i3c controller devices to the ast2600 g6 common dts. We add all
6 busses to the common g6 definition, but leave disabled through the
status property, to be enabled per-platform.

Suggested-by: Jeremy Kerr <jk@codeconstruct.com.au>
Signed-off-by: Dawid Glazik <dawid.glazik@linux.intel.com>
Link: https://patch.msgid.link/7a94a5f4cf84c11c7fba7485e666ecbaddfbe5cf.1777058942.git.dawid.glazik@linux.intel.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
This commit is contained in:
Dawid Glazik 2026-04-24 22:21:01 +02:00 committed by Andrew Jeffery
parent 46ed8942ab
commit 91b9aed738
1 changed files with 91 additions and 0 deletions
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91
arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
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@ -1066,6 +1066,97 @@ i2c15: i2c@800 {
};
};
bus@1e7a0000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1e7a0000 0x8000>;
i3c_global: syscon@0 {
compatible = "aspeed,ast2600-i3c-global", "syscon";
reg = <0x0 0x1000>;
resets = <&syscon ASPEED_RESET_I3C_DMA>;
};
i3c0: i3c@2000 {
compatible = "aspeed,ast2600-i3c";
reg = <0x2000 0x1000>;
#address-cells = <3>;
#size-cells = <0>;
clocks = <&syscon ASPEED_CLK_GATE_I3C0CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i3c1_default>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
aspeed,global-regs = <&i3c_global 0>;
status = "disabled";
};
i3c1: i3c@3000 {
compatible = "aspeed,ast2600-i3c";
reg = <0x3000 0x1000>;
#address-cells = <3>;
#size-cells = <0>;
clocks = <&syscon ASPEED_CLK_GATE_I3C1CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i3c2_default>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
aspeed,global-regs = <&i3c_global 1>;
status = "disabled";
};
i3c2: i3c@4000 {
compatible = "aspeed,ast2600-i3c";
reg = <0x4000 0x1000>;
#address-cells = <3>;
#size-cells = <0>;
clocks = <&syscon ASPEED_CLK_GATE_I3C2CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i3c3_default>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
aspeed,global-regs = <&i3c_global 2>;
status = "disabled";
};
i3c3: i3c@5000 {
compatible = "aspeed,ast2600-i3c";
reg = <0x5000 0x1000>;
#address-cells = <3>;
#size-cells = <0>;
clocks = <&syscon ASPEED_CLK_GATE_I3C3CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i3c4_default>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
aspeed,global-regs = <&i3c_global 3>;
status = "disabled";
};
i3c4: i3c@6000 {
compatible = "aspeed,ast2600-i3c";
reg = <0x6000 0x1000>;
#address-cells = <3>;
#size-cells = <0>;
clocks = <&syscon ASPEED_CLK_GATE_I3C4CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i3c5_default>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
aspeed,global-regs = <&i3c_global 4>;
status = "disabled";
};
i3c5: i3c@7000 {
compatible = "aspeed,ast2600-i3c";
reg = <0x7000 0x1000>;
#address-cells = <3>;
#size-cells = <0>;
clocks = <&syscon ASPEED_CLK_GATE_I3C5CLK>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i3c6_default>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
aspeed,global-regs = <&i3c_global 5>;
status = "disabled";
};
};
fsim0: fsi@1e79b000 {
#interrupt-cells = <1>;
compatible = "aspeed,ast2600-fsi-master";