From 796010d53f992efcb549381d4055d5ff7226154c Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Wed, 1 Oct 2025 19:31:13 +0100 Subject: [PATCH 1/6] arm64: dts: xilinx: add soc-specific spi compatibles for zynqmp/versal-net Unlike zynq, which has a specific compatible for the Cadence spi controller, zynqmp and versal-net do not have specific compatibles. In order to "encourage" people to use soc-specific compatibles for new devices using this IP, add specific compatibles for these devices, with a fallback to the existing compatible for the r1p6 version of the IP so that there will be no functional change. Signed-off-by: Conor Dooley Acked-by: Michal Simek Link: https://lore.kernel.org/r/20251001-cheesy-shucking-c55431bbcae3@spud Signed-off-by: Michal Simek --- arch/arm64/boot/dts/xilinx/versal-net.dtsi | 4 ++-- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/versal-net.dtsi b/arch/arm64/boot/dts/xilinx/versal-net.dtsi index 412af9a394aa..15f767608e67 100644 --- a/arch/arm64/boot/dts/xilinx/versal-net.dtsi +++ b/arch/arm64/boot/dts/xilinx/versal-net.dtsi @@ -1018,7 +1018,7 @@ smmu: iommu@ec000000 { }; spi0: spi@f1960000 { - compatible = "cdns,spi-r1p6"; + compatible = "xlnx,versal-net-spi-r1p6", "cdns,spi-r1p6"; status = "disabled"; interrupts = <0 23 4>; reg = <0 0xf1960000 0 0x1000>; @@ -1026,7 +1026,7 @@ spi0: spi@f1960000 { }; spi1: spi@f1970000 { - compatible = "cdns,spi-r1p6"; + compatible = "xlnx,versal-net-spi-r1p6", "cdns,spi-r1p6"; status = "disabled"; interrupts = <0 24 4>; reg = <0 0xf1970000 0 0x1000>; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 938b014ca923..4486c67b2a30 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -1080,7 +1080,7 @@ smmu: iommu@fd800000 { }; spi0: spi@ff040000 { - compatible = "cdns,spi-r1p6"; + compatible = "xlnx,zynqmp-spi-r1p6", "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = ; @@ -1092,7 +1092,7 @@ spi0: spi@ff040000 { }; spi1: spi@ff050000 { - compatible = "cdns,spi-r1p6"; + compatible = "xlnx,zynqmp-spi-r1p6", "cdns,spi-r1p6"; status = "disabled"; interrupt-parent = <&gic>; interrupts = ; From 801c03446205af4c94736b4892805c10697e6f61 Mon Sep 17 00:00:00 2001 From: Harini T Date: Thu, 30 Jan 2025 17:32:33 +0530 Subject: [PATCH 2/6] dt-bindings: watchdog: xlnx,versal-wwdt: Add optional power-domains property AMD/Xilinx Versal Window Watchdog Timer has its own power domain, so add an optional property to describe it. Signed-off-by: Harini T Acked-by: Conor Dooley Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20250130120233.742879-1-harini.t@amd.com --- .../devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml b/Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml index 14b069599740..fccfc785a077 100644 --- a/Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/xlnx,versal-wwdt.yaml @@ -32,6 +32,9 @@ properties: clocks: maxItems: 1 + power-domains: + maxItems: 1 + required: - compatible - reg From 138cb5c1bc67058542ea83109dd6e2d0d2451528 Mon Sep 17 00:00:00 2001 From: Neal Frager Date: Tue, 11 Nov 2025 07:05:55 +0000 Subject: [PATCH 3/6] arm64: dts: xilinx: fix zynqmp opp-table-cpu Since the following commit, the zynqmp clk driver uses the common divider_round_rate() when determining the appropriate clock divider for a requested clock frequency: https://github.com/torvalds/linux/commit/1fe15be1fb613534ecbac5f8c3f8744f757d237d This means that all the calculations will be in kHz when determining the appropriate clock divider for a given cpufreq request. The problem with this is that the zynqmp.dtsi and zynqmp-clk-ccf.dtsi files have frequency definitions in Hz, so when dividing requested values in kHz, errors can occur with the rounding. For example, the current pss_ref_clk frequency is 33333333 Hz which generates a cpufreq parent clock frequency of 1199999988 Hz which is the same as the highest opp-table-cpu frequency in the zynqmp.dtsi. But if a user requests the value 1199999 kHz as recommended in the available frequencies: root@zynqmp:/sys/kernel/tracing# cat /sys/devices/system/cpu/cpufreq/policy0/scaling_available_frequencies 299999 399999 599999 1199999 root@zynqmp:/ # echo 1199999 > /sys/devices/system/cpu/cpufreq/policy0/scaling_setspeed The calculation will be: 1199999988 / 1199999000 = 1.000001 This will get rounded up to a divider value of 2 giving the following result. root@zynqmp:/ # cat /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq 599999 Also, if a user tries to work around this calculation by using any larger values, it still will not fix the problem because the driver will use the largest opp in kHz which leads to the same calculation error. User requests 1200000 root@zynqmp:/ # echo 1200000 > /sys/devices/system/cpu/cpufreq/policy0/scaling_setspeed Driver converts any value greater than 1199999 to the largest opp which is 1199999 and then calculates the divider value with the same calculation. The calculation will still be: 1199999988 / 1199999000 = 1.000001 This will get rounded up to a divider value of 2 giving the following result. root@zynqmp:/ # cat /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq 599999 This means there is no way to configure the zynqmp for the fastest opp using the current dtsi files. To fix this issue, this patch updates the zynqmp opp-table-cpu and pss_ref_clk, so the clock rates are calculated correctly. root@zynqmp:/sys/kernel/tracing# cat /sys/devices/system/cpu/cpufreq/policy0/scaling_available_frequencies 300000 400000 600000 1200000 root@zynqmp:/ # echo 1200000 > /sys/devices/system/cpu/cpufreq/policy0/scaling_setspeed root@zynqmp:/ # cat /sys/devices/system/cpu/cpufreq/policy0/cpuinfo_cur_freq 1200000 Signed-off-by: Neal Frager Acked-by: Jay Buddhabhatti Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20251111070555.1169130-1-neal.frager@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi | 2 +- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi index 52e122fc7c9e..482f432ba7f3 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi @@ -14,7 +14,7 @@ pss_ref_clk: pss-ref-clk { bootph-all; compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <33333333>; + clock-frequency = <33333000>; clock-output-names = "pss_ref_clk"; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 4486c67b2a30..4dfcaa9927b0 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -103,23 +103,23 @@ CPU_SLEEP_0: cpu-sleep-0 { cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; - opp00 { - opp-hz = /bits/ 64 <1199999988>; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; - opp01 { - opp-hz = /bits/ 64 <599999994>; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; - opp02 { - opp-hz = /bits/ 64 <399999996>; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; - opp03 { - opp-hz = /bits/ 64 <299999997>; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; opp-microvolt = <1000000>; clock-latency-ns = <500000>; }; From c197179990124f991fca220d97fac56779a02c6d Mon Sep 17 00:00:00 2001 From: Tomas Melin Date: Tue, 25 Nov 2025 09:53:54 +0200 Subject: [PATCH 4/6] Revert "arm64: zynqmp: Add an OP-TEE node to the device tree" This reverts commit 06d22ed6b6635b17551f386b50bb5aaff9b75fbe. OP-TEE logic in U-Boot automatically injects a reserved-memory node along with optee firmware node to kernel device tree. The injection logic is dependent on that there is no manually defined optee node. Having the node in zynqmp.dtsi effectively breaks OP-TEE's insertion of the reserved-memory node, causing memory access violations during runtime. Signed-off-by: Tomas Melin Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20251125-revert-zynqmp-optee-v1-1-d2ce4c0fcaf6@vaisala.com --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 4dfcaa9927b0..29058e633fe9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -192,11 +192,6 @@ psci { }; firmware { - optee: optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - zynqmp_firmware: zynqmp-firmware { compatible = "xlnx,zynqmp-firmware"; #power-domain-cells = <1>; From e06a177d819570014ca627a062b38a032a816165 Mon Sep 17 00:00:00 2001 From: "Rob Herring (Arm)" Date: Tue, 16 Dec 2025 11:59:13 -0600 Subject: [PATCH 5/6] arm64: dts: xilinx: Drop "label" property on dlg,slg7xl45106 The "label" property is not documented for the dlg,slg7xl45106. Nor is it common to use for GPIO controllers. So drop it. Signed-off-by: Rob Herring (Arm) Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20251216175914.2791200-1-robh@kernel.org --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso | 1 - arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso | 1 - arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso | 1 - 3 files changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso index 02be5e1e8686..d0230da47068 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso @@ -75,7 +75,6 @@ u3: ina260@40 { /* u3 */ slg7xl45106: gpio@11 { /* u13 - reset logic */ compatible = "dlg,slg7xl45106"; reg = <0x11>; - label = "resetchip"; gpio-controller; #gpio-cells = <2>; gpio-line-names = "USB0_PHY_RESET_B", "", diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso index b92dcb86e87e..5d1f031bbd89 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso @@ -103,7 +103,6 @@ u14: ina260@40 { /* u14 */ slg7xl45106: gpio@11 { /* u19 - reset logic */ compatible = "dlg,slg7xl45106"; reg = <0x11>; - label = "resetchip"; gpio-controller; #gpio-cells = <2>; gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso index 99ad220d13d6..1d5c95bd6073 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso @@ -104,7 +104,6 @@ u14: ina260@40 { /* u14 */ slg7xl45106: gpio@11 { /* u19 - reset logic */ compatible = "dlg,slg7xl45106"; reg = <0x11>; - label = "resetchip"; gpio-controller; #gpio-cells = <2>; gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", From 4310a370a323901b42f0ddd119a53af723f3359b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 15 Dec 2025 09:02:05 +0100 Subject: [PATCH 6/6] arm64: zynqmp: Remove ina260 IIO description Kernel has only hwmon driver that's why there is no reason to wire iio to hwmon converter which was describing out of tree ina260 IIO. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/7e57f76deca9e73be3fcb914aed119f567c9bf8a.1765785722.git.michal.simek@amd.com --- arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso | 6 ------ arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso | 6 ------ arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso | 6 ------ arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 6 ------ arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso | 6 ------ 5 files changed, 30 deletions(-) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso index d0230da47068..23f6695d86b4 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kd-g-revA.dtso @@ -26,11 +26,6 @@ aliases { ethernet0 = "/axi/ethernet@ff0c0000"; /* &gem1 */ }; - ina260-u3 { - compatible = "iio-hwmon"; - io-channels = <&u3 0>, <&u3 1>, <&u3 2>; - }; - clk_26: clock2 { /* u17 - USB */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -67,7 +62,6 @@ &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ u3: ina260@40 { /* u3 */ compatible = "ti,ina260"; - #io-channel-cells = <1>; label = "ina260-u14"; reg = <0x40>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso index 5d1f031bbd89..b82a056be2f9 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso @@ -25,11 +25,6 @@ aliases { ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */ }; - ina260-u14 { - compatible = "iio-hwmon"; - io-channels = <&u14 0>, <&u14 1>, <&u14 2>; - }; - clk_27: clock0 { /* u86 - DP */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -95,7 +90,6 @@ &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; - #io-channel-cells = <1>; label = "ina260-u14"; reg = <0x40>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso index 1d5c95bd6073..4dcf92a2158f 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revB.dtso @@ -25,11 +25,6 @@ aliases { ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */ }; - ina260-u14 { - compatible = "iio-hwmon"; - io-channels = <&u14 0>, <&u14 1>, <&u14 2>; - }; - clk_125: clock0 { /* u87 - GEM0/1 */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -96,7 +91,6 @@ &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; - #io-channel-cells = <1>; label = "ina260-u14"; reg = <0x40>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso index d7351a17d3e8..923a70d750bf 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso @@ -32,11 +32,6 @@ aliases { ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */ }; - ina260-u14 { - compatible = "iio-hwmon"; - io-channels = <&u14 0>, <&u14 1>, <&u14 2>; - }; - si5332_0: si5332-0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -96,7 +91,6 @@ &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; - #io-channel-cells = <1>; label = "ina260-u14"; reg = <0x40>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso index a4ae37ebaccf..563e750b0e08 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso @@ -27,11 +27,6 @@ aliases { ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */ }; - ina260-u14 { - compatible = "iio-hwmon"; - io-channels = <&u14 0>, <&u14 1>, <&u14 2>; - }; - si5332_0: si5332-0 { /* u17 */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -92,7 +87,6 @@ &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ u14: ina260@40 { /* u14 */ compatible = "ti,ina260"; - #io-channel-cells = <1>; label = "ina260-u14"; reg = <0x40>; };