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octeontx2: use arch_extension to enable LSE

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Instead of using ".cpu generic+lse", use ".arch_extension lse" to
enable LSE.

The ".cpu generic+lse" directive replaces the assembler's current feature
set with generic+lse, dropping other previously enabled features. In
contrast, ".arch_extension lse" enables LSE while preserving the current
feature set.

For example, the following code is rejected with "selected processor does
not support retaa", because ".cpu generic+lse" drops PAuth even though it
was enabled by armv9-a:

 .arch armv9-a
 .text
 .cpu generic+lse
 retaa

We encountered this issue while building the kernel with GCC configured
using --with-arch=armv9-a. Since Armv9-A includes pointer authentication,
GCC can assume that PAuth instructions are available and may use retaa
when generating PAuth-protected returns.

Signed-off-by: Emanuele Rocca <emanuele.rocca@arm.com>
Link: https://patch.msgid.link/20261005162137.71397-1-emanuele.rocca@arm.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Emanuele Rocca 2026-10-05 18:21:37 +02:00 committed by Jakub Kicinski
parent 04a943067b
commit 9142c2f8f8
2 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/net/ethernet/marvell/octeontx2/nic/otx2_common.h
View File

@ -785,7 +785,7 @@ static inline u64 otx2_atomic64_add(u64 incr, void __iomem *addr)
u64 __iomem *ptr = addr;
u64 result;
__asm__ volatile(".cpu generic+lse\n"
__asm__ volatile(".arch_extension lse\n"
"ldadd %x[i], %x[r], [%[b]]"
: [r]"=r"(result), "+m"(*ptr)
: [i]"r"(incr), [b]"r"(ptr)

6
include/linux/soc/marvell/octeontx2/asm.h
View File

@ -17,7 +17,7 @@
#define otx2_lmt_flush(ioaddr) \
({ \
u64 result = 0; \
__asm__ volatile(".cpu generic+lse\n" \
__asm__ volatile(".arch_extension lse\n" \
"ldeor xzr, %x[rf], [%[rs]]" \
: [rf]"=r" (result) \
: [rs]"r" (ioaddr)); \
@ -30,7 +30,7 @@
*/
#define cn10k_lmt_flush(val, addr) \
({ \
__asm__ volatile(".cpu generic+lse\n" \
__asm__ volatile(".arch_extension lse\n" \
"steorl %x[rf],[%[rs]]" \
: [rf] "+r"(val) \
: [rs] "r"(addr)); \
@ -40,7 +40,7 @@ static inline u64 otx2_atomic64_fetch_add(u64 incr, u64 *ptr)
{
u64 result;
asm volatile (".cpu generic+lse\n"
asm volatile (".arch_extension lse\n"
"ldadda %x[i], %x[r], [%[b]]"
: [r] "=r" (result), "+m" (*ptr)
: [i] "r" (incr), [b] "r" (ptr)