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drm/amdgpu: enable separate timeout setting for every ring type V4
Every ring type can have its own timeout setting. - V2: update lockup_timeout parameter format and cosmetic fixes - V3: invalidate 0 and negative values - V4: update lockup_timeout parameter format Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -118,7 +118,6 @@ extern int amdgpu_disp_priority;
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extern int amdgpu_hw_i2c;
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extern int amdgpu_pcie_gen2;
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extern int amdgpu_msi;
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extern int amdgpu_lockup_timeout;
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extern int amdgpu_dpm;
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extern int amdgpu_fw_load_type;
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extern int amdgpu_aspm;
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@ -415,6 +414,7 @@ struct amdgpu_fpriv {
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};
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int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv);
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int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev);
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int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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unsigned size, struct amdgpu_ib *ib);
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@ -943,6 +943,11 @@ struct amdgpu_device {
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struct work_struct xgmi_reset_work;
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bool in_baco_reset;
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long gfx_timeout;
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long sdma_timeout;
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long video_timeout;
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long compute_timeout;
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};
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static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
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@ -910,8 +910,10 @@ static void amdgpu_device_check_smu_prv_buffer_size(struct amdgpu_device *adev)
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* Validates certain module parameters and updates
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* the associated values used by the driver (all asics).
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*/
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static void amdgpu_device_check_arguments(struct amdgpu_device *adev)
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static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
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{
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int ret = 0;
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if (amdgpu_sched_jobs < 4) {
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dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
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amdgpu_sched_jobs);
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@ -956,12 +958,15 @@ static void amdgpu_device_check_arguments(struct amdgpu_device *adev)
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amdgpu_vram_page_split = 1024;
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}
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if (amdgpu_lockup_timeout == 0) {
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dev_warn(adev->dev, "lockup_timeout msut be > 0, adjusting to 10000\n");
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amdgpu_lockup_timeout = 10000;
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ret = amdgpu_device_get_job_timeout_settings(adev);
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if (ret) {
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dev_err(adev->dev, "invalid lockup_timeout parameter syntax\n");
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return ret;
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}
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adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type);
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return ret;
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}
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/**
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@ -2473,7 +2478,9 @@ int amdgpu_device_init(struct amdgpu_device *adev,
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mutex_init(&adev->lock_reset);
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mutex_init(&adev->virt.dpm_mutex);
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amdgpu_device_check_arguments(adev);
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r = amdgpu_device_check_arguments(adev);
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if (r)
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return r;
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spin_lock_init(&adev->mmio_idx_lock);
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spin_lock_init(&adev->smc_idx_lock);
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@ -81,6 +81,8 @@
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#define KMS_DRIVER_MINOR 32
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#define KMS_DRIVER_PATCHLEVEL 0
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#define AMDGPU_MAX_TIMEOUT_PARAM_LENTH 256
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int amdgpu_vram_limit = 0;
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int amdgpu_vis_vram_limit = 0;
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int amdgpu_gart_size = -1; /* auto */
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@ -93,7 +95,7 @@ int amdgpu_disp_priority = 0;
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int amdgpu_hw_i2c = 0;
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int amdgpu_pcie_gen2 = -1;
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int amdgpu_msi = -1;
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int amdgpu_lockup_timeout = 10000;
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char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENTH];
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int amdgpu_dpm = -1;
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int amdgpu_fw_load_type = -1;
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int amdgpu_aspm = -1;
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@ -227,12 +229,21 @@ MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
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module_param_named(msi, amdgpu_msi, int, 0444);
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/**
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* DOC: lockup_timeout (int)
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* Set GPU scheduler timeout value in ms. Value 0 is invalidated, will be adjusted to 10000.
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* Negative values mean 'infinite timeout' (MAX_JIFFY_OFFSET). The default is 10000.
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* DOC: lockup_timeout (string)
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* Set GPU scheduler timeout value in ms.
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*
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* The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or
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* multiple values specified. 0 and negative values are invalidated. They will be adjusted
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* to default timeout.
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* - With one value specified, the setting will apply to all non-compute jobs.
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* - With multiple values specified, the first one will be for GFX. The second one is for Compute.
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* And the third and fourth ones are for SDMA and Video.
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* By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video)
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* jobs is 10000. And there is no timeout enforced on compute jobs.
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*/
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MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 10000)");
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module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
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MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: 10000 for non-compute jobs and no timeout for compute jobs), "
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"format is [Non-Compute] or [GFX,Compute,SDMA,Video]");
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module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
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/**
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* DOC: dpm (int)
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@ -1216,6 +1227,62 @@ int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
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return 0;
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}
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int amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
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{
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char *input = amdgpu_lockup_timeout;
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char *timeout_setting = NULL;
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int index = 0;
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long timeout;
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int ret = 0;
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/*
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* By default timeout for non compute jobs is 10000.
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* And there is no timeout enforced on compute jobs.
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*/
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adev->gfx_timeout = adev->sdma_timeout = adev->video_timeout = 10000;
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adev->compute_timeout = MAX_SCHEDULE_TIMEOUT;
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if (strnlen(input, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
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while ((timeout_setting = strsep(&input, ",")) &&
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strnlen(timeout_setting, AMDGPU_MAX_TIMEOUT_PARAM_LENTH)) {
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ret = kstrtol(timeout_setting, 0, &timeout);
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if (ret)
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return ret;
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/* Invalidate 0 and negative values */
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if (timeout <= 0) {
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index++;
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continue;
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}
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switch (index++) {
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case 0:
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adev->gfx_timeout = timeout;
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break;
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case 1:
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adev->compute_timeout = timeout;
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break;
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case 2:
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adev->sdma_timeout = timeout;
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break;
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case 3:
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adev->video_timeout = timeout;
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break;
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default:
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break;
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}
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}
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/*
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* There is only one value specified and
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* it should apply to all non-compute jobs.
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*/
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if (index == 1)
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adev->sdma_timeout = adev->video_timeout = adev->gfx_timeout;
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}
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return ret;
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}
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static bool
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amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe,
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bool in_vblank_irq, int *vpos, int *hpos,
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@ -427,9 +427,13 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
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int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
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unsigned num_hw_submission)
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{
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struct amdgpu_device *adev = ring->adev;
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long timeout;
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int r;
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if (!adev)
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return -EINVAL;
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/* Check that num_hw_submission is a power of two */
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if ((num_hw_submission & (num_hw_submission - 1)) != 0)
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return -EINVAL;
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@ -451,12 +455,31 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
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/* No need to setup the GPU scheduler for KIQ ring */
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if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
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/* for non-sriov case, no timeout enforce on compute ring */
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if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
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&& !amdgpu_sriov_vf(ring->adev))
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timeout = MAX_SCHEDULE_TIMEOUT;
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else
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timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
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switch (ring->funcs->type) {
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case AMDGPU_RING_TYPE_GFX:
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timeout = adev->gfx_timeout;
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break;
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case AMDGPU_RING_TYPE_COMPUTE:
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/*
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* For non-sriov case, no timeout enforce
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* on compute ring by default. Unless user
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* specifies a timeout for compute ring.
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*
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* For sriov case, always use the timeout
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* as gfx ring
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*/
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if (!amdgpu_sriov_vf(ring->adev))
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timeout = adev->compute_timeout;
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else
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timeout = adev->gfx_timeout;
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break;
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case AMDGPU_RING_TYPE_SDMA:
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timeout = adev->sdma_timeout;
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break;
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default:
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timeout = adev->video_timeout;
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break;
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}
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r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
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num_hw_submission, amdgpu_job_hang_limit,
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@ -343,7 +343,7 @@ static void xgpu_ai_mailbox_flr_work(struct work_struct *work)
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/* Trigger recovery for world switch failure if no TDR */
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if (amdgpu_device_should_recover_gpu(adev)
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&& amdgpu_lockup_timeout == MAX_SCHEDULE_TIMEOUT)
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&& adev->sdma_timeout == MAX_SCHEDULE_TIMEOUT)
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amdgpu_device_gpu_recover(adev, NULL);
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}
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