video: rockchip: edp: Solve the problem of write grf register failure

Change-Id: Ia5fa679f4cda5e0c62cf40f2079735c01d0817bc
Signed-off-by: xubilv <xbl@rock-chips.com>
This commit is contained in:
xubilv 2016-10-20 11:38:11 +08:00 committed by Huang, Tao
parent cb3e42dc8c
commit 90f3f1627e
3 changed files with 14 additions and 3 deletions

View File

@ -498,8 +498,8 @@ edp_rk_fb: edp-rk-fb@ff970000 {
reg = <0x0 0xff970000 0x0 0x8000>;
rockchip,grf = <&grf>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
clock-names = "clk_edp", "pclk_edp";
clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
clock-names = "clk_edp", "pclk_edp", "clk_grf";
resets = <&cru SRST_P_EDP_CTRL>;
reset-names = "edp_apb";
status = "disabled";

View File

@ -144,7 +144,9 @@ static int rk32_edp_init_edp(struct rk32_edp *edp)
val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
else
val = EDP_SEL_VOP_LIT << 16;
clk_prepare_enable(edp->grf_clk);
regmap_write(edp->grf, RK3399_GRF_SOC_CON20, val);
clk_disable_unprepare(edp->grf_clk);
}
rk32_edp_reset(edp);
@ -1778,6 +1780,14 @@ static int rk32_edp_probe(struct platform_device *pdev)
return PTR_ERR(edp->grf);
}
if (edp->soctype == SOC_RK3399) {
edp->grf_clk = devm_clk_get(&pdev->dev, "clk_grf");
if (IS_ERR(edp->grf_clk)) {
dev_err(&pdev->dev, "cannot get grf clk\n");
return PTR_ERR(edp->grf_clk);
}
}
edp->pd = devm_clk_get(&pdev->dev, "pd_edp");
if (IS_ERR(edp->pd)) {
dev_err(&pdev->dev, "cannot get pd\n");

View File

@ -556,6 +556,7 @@ struct rk32_edp {
void __iomem *regs;
struct regmap *grf;
unsigned int irq;
struct clk *grf_clk;
struct clk *pd;
struct clk *clk_edp; /*clk for edp controller*/
struct clk *clk_24m; /*clk for edp phy*/
@ -667,4 +668,4 @@ int rk32_edp_wait_hw_lt_done(struct rk32_edp *edp);
enum dp_irq_type rk32_edp_get_irq_type(struct rk32_edp *edp);
void rk32_edp_clear_hotplug_interrupts(struct rk32_edp *edp);
#endif
#endif