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https://github.com/torvalds/linux.git
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PM / devfreq: rockchip_dmc: add support for rk1808
Change-Id: If6a5230f84f8ea293f3d6c84f7586dbff3a02230 Signed-off-by: YouMin Chen <cym@rock-chips.com>
This commit is contained in:
YouMin Chen
Tao Huang
parent
c475623bba
commit
90cf7903d4
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@ -29,6 +29,7 @@
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#include <linux/input.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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@ -36,6 +37,7 @@
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#include <linux/pm_opp.h>
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#include <linux/pm_qos.h>
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#include <linux/reboot.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/rockchip/rockchip_sip.h>
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#include <linux/rwsem.h>
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@ -262,6 +264,310 @@ struct px30_ddr_dts_config_timing {
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unsigned int available;
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};
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static const char * const rk1808_dts_ca_timing[] = {
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"a0_ddr3a9_de-skew",
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"a1_ddr3a14_de-skew",
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"a2_ddr3a13_de-skew",
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"a3_ddr3a11_de-skew",
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"a4_ddr3a2_de-skew",
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"a5_ddr3a4_de-skew",
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"a6_ddr3a3_de-skew",
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"a7_ddr3a6_de-skew",
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"a8_ddr3a5_de-skew",
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"a9_ddr3a1_de-skew",
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"a10_ddr3a0_de-skew",
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"a11_ddr3a7_de-skew",
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"a12_ddr3casb_de-skew",
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"a13_ddr3a8_de-skew",
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"a14_ddr3odt0_de-skew",
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"a15_ddr3ba1_de-skew",
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"a16_ddr3rasb_de-skew",
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"a17_ddr3null_de-skew",
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"ba0_ddr3ba2_de-skew",
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"ba1_ddr3a12_de-skew",
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"bg0_ddr3ba0_de-skew",
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"bg1_ddr3web_de-skew",
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"cke_ddr3cke_de-skew",
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"ck_ddr3ck_de-skew",
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"ckb_ddr3ckb_de-skew",
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"csb0_ddr3a10_de-skew",
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"odt0_ddr3a15_de-skew",
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"resetn_ddr3resetn_de-skew",
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"actn_ddr3csb0_de-skew",
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"csb1_ddr3csb1_de-skew",
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"odt1_ddr3odt1_de-skew",
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};
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static const char * const rk1808_dts_cs0_a_timing[] = {
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"cs0_dm0_rx_de-skew",
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"cs0_dm0_tx_de-skew",
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"cs0_dq0_rx_de-skew",
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"cs0_dq0_tx_de-skew",
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"cs0_dq1_rx_de-skew",
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"cs0_dq1_tx_de-skew",
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"cs0_dq2_rx_de-skew",
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"cs0_dq2_tx_de-skew",
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"cs0_dq3_rx_de-skew",
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"cs0_dq3_tx_de-skew",
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"cs0_dq4_rx_de-skew",
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"cs0_dq4_tx_de-skew",
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"cs0_dq5_rx_de-skew",
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"cs0_dq5_tx_de-skew",
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"cs0_dq6_rx_de-skew",
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"cs0_dq6_tx_de-skew",
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"cs0_dq7_rx_de-skew",
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"cs0_dq7_tx_de-skew",
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"cs0_dqs0p_rx_de-skew",
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"cs0_dqs0p_tx_de-skew",
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"cs0_dqs0n_tx_de-skew",
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"cs0_dm1_rx_de-skew",
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"cs0_dm1_tx_de-skew",
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"cs0_dq8_rx_de-skew",
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"cs0_dq8_tx_de-skew",
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"cs0_dq9_rx_de-skew",
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"cs0_dq9_tx_de-skew",
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"cs0_dq10_rx_de-skew",
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"cs0_dq10_tx_de-skew",
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"cs0_dq11_rx_de-skew",
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"cs0_dq11_tx_de-skew",
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"cs0_dq12_rx_de-skew",
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"cs0_dq12_tx_de-skew",
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"cs0_dq13_rx_de-skew",
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"cs0_dq13_tx_de-skew",
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"cs0_dq14_rx_de-skew",
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"cs0_dq14_tx_de-skew",
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"cs0_dq15_rx_de-skew",
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"cs0_dq15_tx_de-skew",
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"cs0_dqs1p_rx_de-skew",
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"cs0_dqs1p_tx_de-skew",
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"cs0_dqs1n_tx_de-skew",
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"cs0_dqs0n_rx_de-skew",
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"cs0_dqs1n_rx_de-skew",
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};
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static const char * const rk1808_dts_cs0_b_timing[] = {
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"cs0_dm2_rx_de-skew",
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"cs0_dm2_tx_de-skew",
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"cs0_dq16_rx_de-skew",
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"cs0_dq16_tx_de-skew",
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"cs0_dq17_rx_de-skew",
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"cs0_dq17_tx_de-skew",
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"cs0_dq18_rx_de-skew",
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"cs0_dq18_tx_de-skew",
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"cs0_dq19_rx_de-skew",
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"cs0_dq19_tx_de-skew",
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"cs0_dq20_rx_de-skew",
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"cs0_dq20_tx_de-skew",
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"cs0_dq21_rx_de-skew",
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"cs0_dq21_tx_de-skew",
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"cs0_dq22_rx_de-skew",
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"cs0_dq22_tx_de-skew",
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"cs0_dq23_rx_de-skew",
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"cs0_dq23_tx_de-skew",
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"cs0_dqs2p_rx_de-skew",
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"cs0_dqs2p_tx_de-skew",
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"cs0_dqs2n_tx_de-skew",
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"cs0_dm3_rx_de-skew",
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"cs0_dm3_tx_de-skew",
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"cs0_dq24_rx_de-skew",
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"cs0_dq24_tx_de-skew",
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"cs0_dq25_rx_de-skew",
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"cs0_dq25_tx_de-skew",
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"cs0_dq26_rx_de-skew",
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"cs0_dq26_tx_de-skew",
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"cs0_dq27_rx_de-skew",
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"cs0_dq27_tx_de-skew",
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"cs0_dq28_rx_de-skew",
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"cs0_dq28_tx_de-skew",
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"cs0_dq29_rx_de-skew",
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"cs0_dq29_tx_de-skew",
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"cs0_dq30_rx_de-skew",
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"cs0_dq30_tx_de-skew",
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"cs0_dq31_rx_de-skew",
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"cs0_dq31_tx_de-skew",
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"cs0_dqs3p_rx_de-skew",
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"cs0_dqs3p_tx_de-skew",
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"cs0_dqs3n_tx_de-skew",
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"cs0_dqs2n_rx_de-skew",
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"cs0_dqs3n_rx_de-skew",
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};
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static const char * const rk1808_dts_cs1_a_timing[] = {
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"cs1_dm0_rx_de-skew",
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"cs1_dm0_tx_de-skew",
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"cs1_dq0_rx_de-skew",
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"cs1_dq0_tx_de-skew",
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"cs1_dq1_rx_de-skew",
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"cs1_dq1_tx_de-skew",
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"cs1_dq2_rx_de-skew",
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"cs1_dq2_tx_de-skew",
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"cs1_dq3_rx_de-skew",
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"cs1_dq3_tx_de-skew",
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"cs1_dq4_rx_de-skew",
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"cs1_dq4_tx_de-skew",
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"cs1_dq5_rx_de-skew",
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"cs1_dq5_tx_de-skew",
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"cs1_dq6_rx_de-skew",
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"cs1_dq6_tx_de-skew",
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"cs1_dq7_rx_de-skew",
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"cs1_dq7_tx_de-skew",
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"cs1_dqs0p_rx_de-skew",
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"cs1_dqs0p_tx_de-skew",
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"cs1_dqs0n_tx_de-skew",
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"cs1_dm1_rx_de-skew",
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"cs1_dm1_tx_de-skew",
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"cs1_dq8_rx_de-skew",
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"cs1_dq8_tx_de-skew",
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"cs1_dq9_rx_de-skew",
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"cs1_dq9_tx_de-skew",
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"cs1_dq10_rx_de-skew",
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"cs1_dq10_tx_de-skew",
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"cs1_dq11_rx_de-skew",
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"cs1_dq11_tx_de-skew",
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"cs1_dq12_rx_de-skew",
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"cs1_dq12_tx_de-skew",
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"cs1_dq13_rx_de-skew",
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"cs1_dq13_tx_de-skew",
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"cs1_dq14_rx_de-skew",
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"cs1_dq14_tx_de-skew",
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"cs1_dq15_rx_de-skew",
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"cs1_dq15_tx_de-skew",
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"cs1_dqs1p_rx_de-skew",
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"cs1_dqs1p_tx_de-skew",
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"cs1_dqs1n_tx_de-skew",
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"cs1_dqs0n_rx_de-skew",
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"cs1_dqs1n_rx_de-skew",
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};
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static const char * const rk1808_dts_cs1_b_timing[] = {
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"cs1_dm2_rx_de-skew",
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"cs1_dm2_tx_de-skew",
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"cs1_dq16_rx_de-skew",
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"cs1_dq16_tx_de-skew",
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"cs1_dq17_rx_de-skew",
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"cs1_dq17_tx_de-skew",
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"cs1_dq18_rx_de-skew",
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"cs1_dq18_tx_de-skew",
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"cs1_dq19_rx_de-skew",
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"cs1_dq19_tx_de-skew",
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"cs1_dq20_rx_de-skew",
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"cs1_dq20_tx_de-skew",
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"cs1_dq21_rx_de-skew",
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"cs1_dq21_tx_de-skew",
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"cs1_dq22_rx_de-skew",
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"cs1_dq22_tx_de-skew",
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"cs1_dq23_rx_de-skew",
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"cs1_dq23_tx_de-skew",
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"cs1_dqs2p_rx_de-skew",
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"cs1_dqs2p_tx_de-skew",
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"cs1_dqs2n_tx_de-skew",
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"cs1_dm3_rx_de-skew",
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"cs1_dm3_tx_de-skew",
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"cs1_dq24_rx_de-skew",
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"cs1_dq24_tx_de-skew",
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"cs1_dq25_rx_de-skew",
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"cs1_dq25_tx_de-skew",
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"cs1_dq26_rx_de-skew",
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"cs1_dq26_tx_de-skew",
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"cs1_dq27_rx_de-skew",
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"cs1_dq27_tx_de-skew",
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"cs1_dq28_rx_de-skew",
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"cs1_dq28_tx_de-skew",
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"cs1_dq29_rx_de-skew",
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"cs1_dq29_tx_de-skew",
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"cs1_dq30_rx_de-skew",
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"cs1_dq30_tx_de-skew",
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"cs1_dq31_rx_de-skew",
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"cs1_dq31_tx_de-skew",
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"cs1_dqs3p_rx_de-skew",
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"cs1_dqs3p_tx_de-skew",
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"cs1_dqs3n_tx_de-skew",
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"cs1_dqs2n_rx_de-skew",
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"cs1_dqs3n_rx_de-skew",
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};
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struct rk1808_ddr_dts_config_timing {
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unsigned int ddr2_speed_bin;
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unsigned int ddr3_speed_bin;
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unsigned int ddr4_speed_bin;
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unsigned int pd_idle;
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unsigned int sr_idle;
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unsigned int sr_mc_gate_idle;
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unsigned int srpd_lite_idle;
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unsigned int standby_idle;
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unsigned int auto_pd_dis_freq;
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unsigned int auto_sr_dis_freq;
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/* for ddr2 only */
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unsigned int ddr2_dll_dis_freq;
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/* for ddr3 only */
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unsigned int ddr3_dll_dis_freq;
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/* for ddr4 only */
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unsigned int ddr4_dll_dis_freq;
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unsigned int phy_dll_dis_freq;
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unsigned int ddr2_odt_dis_freq;
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unsigned int phy_ddr2_odt_dis_freq;
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unsigned int ddr2_drv;
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unsigned int ddr2_odt;
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unsigned int phy_ddr2_ca_drv;
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unsigned int phy_ddr2_ck_drv;
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unsigned int phy_ddr2_dq_drv;
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unsigned int phy_ddr2_odt;
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unsigned int ddr3_odt_dis_freq;
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unsigned int phy_ddr3_odt_dis_freq;
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unsigned int ddr3_drv;
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unsigned int ddr3_odt;
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unsigned int phy_ddr3_ca_drv;
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unsigned int phy_ddr3_ck_drv;
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unsigned int phy_ddr3_dq_drv;
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unsigned int phy_ddr3_odt;
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unsigned int phy_lpddr2_odt_dis_freq;
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unsigned int lpddr2_drv;
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unsigned int phy_lpddr2_ca_drv;
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unsigned int phy_lpddr2_ck_drv;
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unsigned int phy_lpddr2_dq_drv;
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unsigned int phy_lpddr2_odt;
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unsigned int lpddr3_odt_dis_freq;
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unsigned int phy_lpddr3_odt_dis_freq;
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unsigned int lpddr3_drv;
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unsigned int lpddr3_odt;
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unsigned int phy_lpddr3_ca_drv;
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unsigned int phy_lpddr3_ck_drv;
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unsigned int phy_lpddr3_dq_drv;
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unsigned int phy_lpddr3_odt;
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unsigned int lpddr4_odt_dis_freq;
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unsigned int phy_lpddr4_odt_dis_freq;
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unsigned int lpddr4_drv;
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unsigned int lpddr4_dq_odt;
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unsigned int lpddr4_ca_odt;
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unsigned int phy_lpddr4_ca_drv;
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unsigned int phy_lpddr4_ck_cs_drv;
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unsigned int phy_lpddr4_dq_drv;
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unsigned int phy_lpddr4_odt;
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unsigned int ddr4_odt_dis_freq;
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unsigned int phy_ddr4_odt_dis_freq;
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unsigned int ddr4_drv;
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unsigned int ddr4_odt;
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unsigned int phy_ddr4_ca_drv;
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unsigned int phy_ddr4_ck_drv;
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unsigned int phy_ddr4_dq_drv;
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unsigned int phy_ddr4_odt;
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unsigned int ca_de_skew[31];
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unsigned int cs0_a_de_skew[44];
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unsigned int cs0_b_de_skew[44];
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unsigned int cs1_a_de_skew[44];
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unsigned int cs1_b_de_skew[44];
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unsigned int available;
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};
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static const char * const rk3128_dts_timing[] = {
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"ddr3_speed_bin",
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"pd_idle",
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@ -1300,6 +1606,67 @@ static void of_get_px30_timings(struct device *dev,
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of_node_put(np_tim);
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}
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static void of_get_rk1808_timings(struct device *dev,
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struct device_node *np, uint32_t *timing)
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{
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struct device_node *np_tim;
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u32 *p;
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struct rk1808_ddr_dts_config_timing *dts_timing;
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int ret = 0;
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u32 i;
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dts_timing =
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(struct rk1808_ddr_dts_config_timing *)(timing +
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DTS_PAR_OFFSET / 4);
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np_tim = of_parse_phandle(np, "ddr_timing", 0);
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if (!np_tim) {
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ret = -EINVAL;
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goto end;
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}
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p = (u32 *)dts_timing;
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for (i = 0; i < ARRAY_SIZE(px30_dts_timing); i++) {
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ret |= of_property_read_u32(np_tim, px30_dts_timing[i],
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p + i);
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}
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p = (u32 *)dts_timing->ca_de_skew;
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for (i = 0; i < ARRAY_SIZE(rk1808_dts_ca_timing); i++) {
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ret |= of_property_read_u32(np_tim, rk1808_dts_ca_timing[i],
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p + i);
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}
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p = (u32 *)dts_timing->cs0_a_de_skew;
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for (i = 0; i < ARRAY_SIZE(rk1808_dts_cs0_a_timing); i++) {
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ret |= of_property_read_u32(np_tim, rk1808_dts_cs0_a_timing[i],
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p + i);
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}
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p = (u32 *)dts_timing->cs0_b_de_skew;
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for (i = 0; i < ARRAY_SIZE(rk1808_dts_cs0_b_timing); i++) {
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ret |= of_property_read_u32(np_tim, rk1808_dts_cs0_b_timing[i],
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p + i);
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}
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p = (u32 *)dts_timing->cs1_a_de_skew;
|
||||
for (i = 0; i < ARRAY_SIZE(rk1808_dts_cs1_a_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk1808_dts_cs1_a_timing[i],
|
||||
p + i);
|
||||
}
|
||||
p = (u32 *)dts_timing->cs1_b_de_skew;
|
||||
for (i = 0; i < ARRAY_SIZE(rk1808_dts_cs1_b_timing); i++) {
|
||||
ret |= of_property_read_u32(np_tim, rk1808_dts_cs1_b_timing[i],
|
||||
p + i);
|
||||
}
|
||||
|
||||
end:
|
||||
if (!ret) {
|
||||
dts_timing->available = 1;
|
||||
} else {
|
||||
dts_timing->available = 0;
|
||||
dev_err(dev, "of_get_ddr_timings: fail\n");
|
||||
}
|
||||
|
||||
of_node_put(np_tim);
|
||||
}
|
||||
|
||||
static void of_get_rk3128_timings(struct device *dev,
|
||||
struct device_node *np, uint32_t *timing)
|
||||
{
|
||||
|
|
@ -1675,6 +2042,8 @@ struct dmcfreq_wait_ctrl_t {
|
|||
int wait_flag;
|
||||
int wait_en;
|
||||
int wait_time_out_ms;
|
||||
int dcf_en;
|
||||
struct regmap *regmap_dcf;
|
||||
};
|
||||
|
||||
static struct dmcfreq_wait_ctrl_t wait_ctrl;
|
||||
|
|
@ -1688,6 +2057,21 @@ static irqreturn_t wait_complete_irq(int irqno, void *dev_id)
|
|||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static irqreturn_t wait_dcf_complete_irq(int irqno, void *dev_id)
|
||||
{
|
||||
struct arm_smccc_res res;
|
||||
struct dmcfreq_wait_ctrl_t *ctrl = dev_id;
|
||||
|
||||
res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
|
||||
ROCKCHIP_SIP_CONFIG_DRAM_POST_SET_RATE);
|
||||
if (res.a0)
|
||||
pr_err("%s: dram post set rate error:%lx\n", __func__, res.a0);
|
||||
|
||||
ctrl->wait_flag = 0;
|
||||
wake_up(&ctrl->wait_wq);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
int rockchip_dmcfreq_wait_complete(void)
|
||||
{
|
||||
if (!wait_ctrl.wait_en) {
|
||||
|
|
@ -1702,6 +2086,11 @@ int rockchip_dmcfreq_wait_complete(void)
|
|||
*/
|
||||
pm_qos_update_request(&pm_qos, 0);
|
||||
|
||||
if (wait_ctrl.dcf_en == 1) {
|
||||
/* start dcf */
|
||||
regmap_update_bits(wait_ctrl.regmap_dcf, 0x0, 0x1, 0x1);
|
||||
}
|
||||
|
||||
wait_event_timeout(wait_ctrl.wait_wq, (wait_ctrl.wait_flag == 0),
|
||||
msecs_to_jiffies(wait_ctrl.wait_time_out_ms));
|
||||
|
||||
|
|
@ -1781,6 +2170,77 @@ static __maybe_unused int px30_dmc_init(struct platform_device *pdev,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static __maybe_unused int rk1808_dmc_init(struct platform_device *pdev,
|
||||
struct rockchip_dmcfreq *dmcfreq)
|
||||
{
|
||||
struct arm_smccc_res res;
|
||||
u32 size;
|
||||
int ret;
|
||||
int complt_irq;
|
||||
struct device_node *node;
|
||||
|
||||
res = sip_smc_dram(0, 0,
|
||||
ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION);
|
||||
dev_notice(&pdev->dev, "current ATF version 0x%lx!\n", res.a1);
|
||||
if (res.a0 || res.a1 < 0x101) {
|
||||
dev_err(&pdev->dev,
|
||||
"trusted firmware need to update or is invalid!\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
/*
|
||||
* first 4KB is used for interface parameters
|
||||
* after 4KB * N is dts parameters
|
||||
*/
|
||||
size = sizeof(struct rk1808_ddr_dts_config_timing);
|
||||
res = sip_smc_request_share_mem(DIV_ROUND_UP(size, 4096) + 1,
|
||||
SHARE_PAGE_TYPE_DDR);
|
||||
if (res.a0 != 0) {
|
||||
dev_err(&pdev->dev, "no ATF memory for init\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
ddr_psci_param = (struct share_params *)res.a1;
|
||||
of_get_rk1808_timings(&pdev->dev, pdev->dev.of_node,
|
||||
(uint32_t *)ddr_psci_param);
|
||||
|
||||
/* enable start dcf in kernel after dcf ready */
|
||||
node = of_parse_phandle(pdev->dev.of_node, "dcf_reg", 0);
|
||||
wait_ctrl.regmap_dcf = syscon_node_to_regmap(node);
|
||||
if (IS_ERR(wait_ctrl.regmap_dcf))
|
||||
return PTR_ERR(wait_ctrl.regmap_dcf);
|
||||
wait_ctrl.dcf_en = 1;
|
||||
|
||||
init_waitqueue_head(&wait_ctrl.wait_wq);
|
||||
wait_ctrl.wait_en = 1;
|
||||
wait_ctrl.wait_time_out_ms = 17 * 5;
|
||||
|
||||
complt_irq = platform_get_irq_byname(pdev, "complete_irq");
|
||||
if (complt_irq < 0) {
|
||||
dev_err(&pdev->dev, "no IRQ for complete_irq: %d\n",
|
||||
complt_irq);
|
||||
return complt_irq;
|
||||
}
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, complt_irq, wait_dcf_complete_irq,
|
||||
0, dev_name(&pdev->dev), &wait_ctrl);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "cannot request complete_irq\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
|
||||
ROCKCHIP_SIP_CONFIG_DRAM_INIT);
|
||||
if (res.a0) {
|
||||
dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n",
|
||||
res.a0);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __maybe_unused int rk3128_dmc_init(struct platform_device *pdev,
|
||||
struct rockchip_dmcfreq *dmcfreq)
|
||||
{
|
||||
|
|
@ -2114,6 +2574,9 @@ static const struct of_device_id rockchip_dmcfreq_of_match[] = {
|
|||
#ifdef CONFIG_CPU_PX30
|
||||
{ .compatible = "rockchip,px30-dmc", .data = px30_dmc_init },
|
||||
#endif
|
||||
#ifdef CONFIG_CPU_RK1808
|
||||
{ .compatible = "rockchip,rk1808-dmc", .data = rk1808_dmc_init },
|
||||
#endif
|
||||
#ifdef CONFIG_CPU_RK312X
|
||||
{ .compatible = "rockchip,rk3128-dmc", .data = rk3128_dmc_init },
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -24,5 +24,6 @@
|
|||
#define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06
|
||||
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07
|
||||
#define ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION 0x08
|
||||
#define ROCKCHIP_SIP_CONFIG_DRAM_POST_SET_RATE 0x09
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user