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arm64: dts: arm/corstone1000: Move cpu nodes

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In preparation to add a new Corstone-1000 variation with different CPUs,
move the CPU nodes into the specific platforms and out of the common
corstone1000.dtsi.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Message-Id: <20260320-dt-corstone1000-a320-v1-3-a549dfcfe8da@kernel.org>
Signed-off-by: Sudeep Holla <sudeep.holla@kernel.org>
This commit is contained in:
Rob Herring (Arm) 2026-03-20 11:47:16 -05:00 committed by Sudeep Holla
parent 55de145c8e
commit 903528ac23
3 changed files with 45 additions and 35 deletions
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54
arch/arm64/boot/dts/arm/corstone1000-fvp.dts
View File

@ -48,30 +48,40 @@ sdmmc1: mmc@50000000 {
clocks = <&smbclk>, <&refclk100mhz>;
clock-names = "smclk", "apb_pclk";
};
};
cpus: cpus {
#address-cells = <2>;
#size-cells = <0>;
&cpus {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0 0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x2>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0 0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x3>;
enable-method = "psci";
next-level-cache = <&L2_0>;
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0 0x2>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0 0x3>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
};
};

13
arch/arm64/boot/dts/arm/corstone1000-mps3.dts
View File

@ -13,6 +13,19 @@ / {
model = "ARM Corstone1000 FPGA MPS3 board";
compatible = "arm,corstone1000-mps3";
cpus: cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0 0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
};
smsc: ethernet@4010000 {
compatible = "smsc,lan9220", "smsc,lan9115";
reg = <0x40100000 0x10000>;

13
arch/arm64/boot/dts/arm/corstone1000.dtsi
View File

@ -21,19 +21,6 @@ chosen {
stdout-path = "serial0:115200n8";
};
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
};
memory@88200000 {
device_type = "memory";
reg = <0x88200000 0x77e00000>;