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This pull request contains Broadcom ARM64-SoC Device Tree fixes for

Browse Source 
6.19, please pull the following:
 
 - Andrea fixes the RP1 DeviceTree hierarchy and drop overlay support,
   this resolves a number of DTC warnings and other issues
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Merge tag 'arm-soc/for-6.19/devicetree-arm64-fixes' of https://github.com/Broadcom/stblinux into arm/fixes

This pull request contains Broadcom ARM64-SoC Device Tree fixes for
6.19, please pull the following:

- Andrea fixes the RP1 DeviceTree hierarchy and drop overlay support,
  this resolves a number of DTC warnings and other issues

* tag 'arm-soc/for-6.19/devicetree-arm64-fixes' of https://github.com/Broadcom/stblinux:
  arm64: dts: broadcom: rp1: drop RP1 overlay
  arm64: dts: broadcom: bcm2712: fix RP1 endpoint PCI topology
  misc: rp1: drop overlay support
  dt-bindings: misc: pci1de4,1: add required reg property for endpoint

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2026-01-07 17:45:03 +01:00
commit 902300d332
11 changed files with 40 additions and 108 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
Documentation/devicetree/bindings/misc/pci1de4,1.yaml
View File

@ -25,6 +25,10 @@ properties:
items:
- const: pci1de4,1
reg:
maxItems: 1
description: The PCI Bus-Device-Function address.
'#interrupt-cells':
const: 2
description: |
@ -101,6 +105,7 @@ unevaluatedProperties: false
required:
- compatible
- reg
- '#interrupt-cells'
- interrupt-controller
- pci-ep-bus@1
@ -111,8 +116,9 @@ examples:
#address-cells = <3>;
#size-cells = <2>;
rp1@0,0 {
dev@0,0 {
compatible = "pci1de4,1";
reg = <0x10000 0x0 0x0 0x0 0x0>;
ranges = <0x01 0x00 0x00000000 0x82010000 0x00 0x00 0x00 0x400000>;
#address-cells = <3>;
#size-cells = <2>;

4
arch/arm64/boot/dts/broadcom/Makefile
View File

@ -7,15 +7,13 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \
bcm2711-rpi-4-b.dtb \
bcm2711-rpi-cm4-io.dtb \
bcm2712-rpi-5-b.dtb \
bcm2712-rpi-5-b-ovl-rp1.dtb \
bcm2712-d-rpi-5-b.dtb \
bcm2837-rpi-2-b.dtb \
bcm2837-rpi-3-a-plus.dtb \
bcm2837-rpi-3-b.dtb \
bcm2837-rpi-3-b-plus.dtb \
bcm2837-rpi-cm3-io3.dtb \
bcm2837-rpi-zero-2-w.dtb \
rp1.dtbo
bcm2837-rpi-zero-2-w.dtb
subdir-y += bcmbca
subdir-y += northstar2

0
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-ovl-rp1.dts → arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi
View File

39
arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
View File

@ -1,22 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* bcm2712-rpi-5-b-ovl-rp1.dts is the overlay-ready DT which will make
* the RP1 driver to load the RP1 dtb overlay at runtime, while
* bcm2712-rpi-5-b.dts (this file) is the fully defined one (i.e. it
* already contains RP1 node, so no overlay is loaded nor needed).
* This file is intended to host the override nodes for the RP1 peripherals,
* e.g. to declare the phy of the ethernet interface or the custom pin setup
* for several RP1 peripherals.
* This in turn is due to the fact that there's no current generic
* infrastructure to reference nodes (i.e. the nodes in rp1-common.dtsi) that
* are not yet defined in the DT since they are loaded at runtime via overlay.
* As a loose attempt to separate RP1 customizations from SoC peripherals
* definitioni, this file is intended to host the override nodes for the RP1
* peripherals, e.g. to declare the phy of the ethernet interface or custom
* pin setup.
* All other nodes that do not have anything to do with RP1 should be added
* to the included bcm2712-rpi-5-b-ovl-rp1.dts instead.
* to the included bcm2712-rpi-5-b-base.dtsi instead.
*/
/dts-v1/;
#include "bcm2712-rpi-5-b-ovl-rp1.dts"
#include "bcm2712-rpi-5-b-base.dtsi"
/ {
aliases {
@ -25,7 +19,26 @@ aliases {
};
&pcie2 {
#include "rp1-nexus.dtsi"
pci@0,0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
ranges;
bus-range = <0 1>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
dev@0,0 {
compatible = "pci1de4,1";
reg = <0x10000 0x0 0x0 0x0 0x0>;
ranges = <0x1 0x0 0x0 0x82010000 0x0 0x0 0x0 0x400000>;
interrupt-controller;
#interrupt-cells = <2>;
#address-cells = <3>;
#size-cells = <2>;
#include "rp1-common.dtsi"
};
};
};
&rp1_eth {

14
arch/arm64/boot/dts/broadcom/rp1-nexus.dtsi
View File

@ -1,14 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
rp1_nexus {
compatible = "pci1de4,1";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01 0x00 0x00000000
0x02000000 0x00 0x00000000
0x0 0x400000>;
interrupt-controller;
#interrupt-cells = <2>;
#include "rp1-common.dtsi"
};

11
arch/arm64/boot/dts/broadcom/rp1.dtso
View File

@ -1,11 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/dts-v1/;
/plugin/;
&pcie2 {
#address-cells = <3>;
#size-cells = <2>;
#include "rp1-nexus.dtsi"
};

6
drivers/misc/rp1/Kconfig
View File

@ -5,8 +5,7 @@
config MISC_RP1
tristate "RaspberryPi RP1 misc device"
depends on OF_IRQ && OF_OVERLAY && PCI_MSI && PCI_QUIRKS
select PCI_DYNAMIC_OF_NODES
depends on OF_IRQ && PCI_MSI
help
Support the RP1 peripheral chip found on Raspberry Pi 5 board.
@ -15,6 +14,3 @@ config MISC_RP1
The driver is responsible for enabling the DT node once the PCIe
endpoint has been configured, and handling interrupts.
This driver uses an overlay to load other drivers to support for
RP1 internal sub-devices.

3
drivers/misc/rp1/Makefile
View File

@ -1,3 +1,2 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_MISC_RP1) += rp1-pci.o
rp1-pci-objs := rp1_pci.o rp1-pci.dtbo.o
obj-$(CONFIG_MISC_RP1) += rp1_pci.o

25
drivers/misc/rp1/rp1-pci.dtso
View File

@ -1,25 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* The dts overlay is included from the dts directory so
* it can be possible to check it with CHECK_DTBS while
* also compile it from the driver source directory.
*/
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target-path="";
__overlay__ {
compatible = "pci1de4,1";
#address-cells = <3>;
#size-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
#include "arm64/broadcom/rp1-common.dtsi"
};
};
};

37
drivers/misc/rp1/rp1_pci.c
View File

@ -34,16 +34,11 @@
/* Interrupts */
#define RP1_INT_END 61
/* Embedded dtbo symbols created by cmd_wrap_S_dtb in scripts/Makefile.lib */
extern char __dtbo_rp1_pci_begin[];
extern char __dtbo_rp1_pci_end[];
struct rp1_dev {
struct pci_dev *pdev;
struct irq_domain *domain;
struct irq_data *pcie_irqds[64];
void __iomem *bar1;
int ovcs_id; /* overlay changeset id */
bool level_triggered_irq[RP1_INT_END];
};
@ -184,24 +179,13 @@ static void rp1_unregister_interrupts(struct pci_dev *pdev)
static int rp1_probe(struct pci_dev *pdev, const struct pci_device_id *id)
{
u32 dtbo_size = __dtbo_rp1_pci_end - __dtbo_rp1_pci_begin;
void *dtbo_start = __dtbo_rp1_pci_begin;
struct device *dev = &pdev->dev;
struct device_node *rp1_node;
bool skip_ovl = true;
struct rp1_dev *rp1;
int err = 0;
int i;
/*
* Either use rp1_nexus node if already present in DT, or
* set a flag to load it from overlay at runtime
*/
rp1_node = of_find_node_by_name(NULL, "rp1_nexus");
if (!rp1_node) {
rp1_node = dev_of_node(dev);
skip_ovl = false;
}
rp1_node = dev_of_node(dev);
if (!rp1_node) {
dev_err(dev, "Missing of_node for device\n");
@ -276,42 +260,29 @@ static int rp1_probe(struct pci_dev *pdev, const struct pci_device_id *id)
rp1_chained_handle_irq, rp1);
}
if (!skip_ovl) {
err = of_overlay_fdt_apply(dtbo_start, dtbo_size, &rp1->ovcs_id,
rp1_node);
if (err)
goto err_unregister_interrupts;
}
err = of_platform_default_populate(rp1_node, NULL, dev);
if (err) {
dev_err_probe(&pdev->dev, err, "Error populating devicetree\n");
goto err_unload_overlay;
goto err_unregister_interrupts;
}
if (skip_ovl)
of_node_put(rp1_node);
of_node_put(rp1_node);
return 0;
err_unload_overlay:
of_overlay_remove(&rp1->ovcs_id);
err_unregister_interrupts:
rp1_unregister_interrupts(pdev);
err_put_node:
if (skip_ovl)
of_node_put(rp1_node);
of_node_put(rp1_node);
return err;
}
static void rp1_remove(struct pci_dev *pdev)
{
struct rp1_dev *rp1 = pci_get_drvdata(pdev);
struct device *dev = &pdev->dev;
of_platform_depopulate(dev);
of_overlay_remove(&rp1->ovcs_id);
rp1_unregister_interrupts(pdev);
}

1
drivers/pci/quirks.c
View File

@ -6308,7 +6308,6 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node);
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RPI, PCI_DEVICE_ID_RPI_RP1_C0, of_pci_make_dev_node);
/*
* Devices known to require a longer delay before first config space access