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drm/amd/pm: Treat zero vblank time as too short in si_dpm (v3)
Some parts of the code base expect that MCLK switching is turned
off when the vblank time is set to zero.
According to pp_pm_compute_clocks the non-DC code has issues
with MCLK switching with refresh rates over 120 Hz.
v3:
Add code comment to explain this better.
Add an if statement instead of changing the switch_limit.
Fixes: 841686df9f ("drm/amdgpu: add SI DPM support (v4)")
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -3085,7 +3085,13 @@ static bool si_dpm_vblank_too_short(void *handle)
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/* we never hit the non-gddr5 limit so disable it */
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/* we never hit the non-gddr5 limit so disable it */
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u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
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u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
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if (vblank_time < switch_limit)
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/* Consider zero vblank time too short and disable MCLK switching.
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* Note that the vblank time is set to maximum when no displays are attached,
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* so we'll still enable MCLK switching in that case.
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*/
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if (vblank_time == 0)
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return true;
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else if (vblank_time < switch_limit)
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return true;
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return true;
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else
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else
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return false;
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return false;
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