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mt76: mt7615: introduce mt7615_mac_update_rate_desc routine
Move register configuration out of mt7615_mac_set_rates since usb driver can't access device register in interrupt context. Introduce mt7615_mac_update_rate_desc routine to report rate info to mt7615_mac_set_rates Co-developed-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Sean Wang <sean.wang@mediatek.com> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org> Signed-off-by: Felix Fietkau <nbd@nbd.name>
This commit is contained in:
Lorenzo Bianconi
Felix Fietkau
parent
d4bf77bd74
commit
8f93af9cac
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@ -813,26 +813,19 @@ void mt7615_mac_sta_poll(struct mt7615_dev *dev)
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rcu_read_unlock();
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}
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void mt7615_mac_set_rates(struct mt7615_phy *phy, struct mt7615_sta *sta,
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struct ieee80211_tx_rate *probe_rate,
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struct ieee80211_tx_rate *rates)
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static void
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mt7615_mac_update_rate_desc(struct mt7615_phy *phy, struct mt7615_sta *sta,
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struct ieee80211_tx_rate *probe_rate,
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struct ieee80211_tx_rate *rates,
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struct mt7615_rate_desc *rd)
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{
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struct mt7615_dev *dev = phy->dev;
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struct mt76_phy *mphy = phy->mt76;
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struct ieee80211_tx_rate *ref;
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int wcid = sta->wcid.idx;
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u32 addr = mt7615_mac_wtbl_addr(dev, wcid);
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bool stbc = false;
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bool rateset, stbc = false;
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int n_rates = sta->n_rates;
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u8 bw, bw_prev, bw_idx = 0;
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u16 val[4];
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u16 probe_val;
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u32 w5, w27;
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bool rateset;
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int i, k;
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if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
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return;
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u8 bw, bw_prev;
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int i, j;
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for (i = n_rates; i < 4; i++)
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rates[i] = rates[n_rates - 1];
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@ -860,10 +853,10 @@ void mt7615_mac_set_rates(struct mt7615_phy *phy, struct mt7615_sta *sta,
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if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI)
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rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI;
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for (k = 0; k < i; k++) {
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if (rates[i].idx != rates[k].idx)
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for (j = 0; j < i; j++) {
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if (rates[i].idx != rates[j].idx)
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continue;
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if ((rates[i].flags ^ rates[k].flags) &
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if ((rates[i].flags ^ rates[j].flags) &
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(IEEE80211_TX_RC_40_MHZ_WIDTH |
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IEEE80211_TX_RC_80_MHZ_WIDTH |
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IEEE80211_TX_RC_160_MHZ_WIDTH))
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@ -876,65 +869,87 @@ void mt7615_mac_set_rates(struct mt7615_phy *phy, struct mt7615_sta *sta,
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}
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}
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val[0] = mt7615_mac_tx_rate_val(dev, mphy, &rates[0], stbc, &bw);
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rd->val[0] = mt7615_mac_tx_rate_val(dev, mphy, &rates[0], stbc, &bw);
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bw_prev = bw;
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if (probe_rate) {
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probe_val = mt7615_mac_tx_rate_val(dev, mphy, probe_rate,
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stbc, &bw);
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rd->probe_val = mt7615_mac_tx_rate_val(dev, mphy, probe_rate,
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stbc, &bw);
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if (bw)
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bw_idx = 1;
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rd->bw_idx = 1;
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else
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bw_prev = 0;
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} else {
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probe_val = val[0];
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rd->probe_val = rd->val[0];
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}
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val[1] = mt7615_mac_tx_rate_val(dev, mphy, &rates[1], stbc, &bw);
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rd->val[1] = mt7615_mac_tx_rate_val(dev, mphy, &rates[1], stbc, &bw);
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if (bw_prev) {
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bw_idx = 3;
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rd->bw_idx = 3;
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bw_prev = bw;
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}
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val[2] = mt7615_mac_tx_rate_val(dev, mphy, &rates[2], stbc, &bw);
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rd->val[2] = mt7615_mac_tx_rate_val(dev, mphy, &rates[2], stbc, &bw);
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if (bw_prev) {
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bw_idx = 5;
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rd->bw_idx = 5;
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bw_prev = bw;
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}
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val[3] = mt7615_mac_tx_rate_val(dev, mphy, &rates[3], stbc, &bw);
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rd->val[3] = mt7615_mac_tx_rate_val(dev, mphy, &rates[3], stbc, &bw);
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if (bw_prev)
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bw_idx = 7;
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rd->bw_idx = 7;
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rd->rateset = rateset;
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rd->sta = sta;
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rd->bw = bw;
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}
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void mt7615_mac_set_rates(struct mt7615_phy *phy, struct mt7615_sta *sta,
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struct ieee80211_tx_rate *probe_rate,
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struct ieee80211_tx_rate *rates)
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{
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int wcid = sta->wcid.idx, n_rates = sta->n_rates;
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struct mt7615_dev *dev = phy->dev;
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struct mt7615_rate_desc rd;
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u32 w5, w27, addr;
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if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
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return;
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memset(&rd, 0, sizeof(struct mt7615_rate_desc));
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mt7615_mac_update_rate_desc(phy, sta, probe_rate, rates, &rd);
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addr = mt7615_mac_wtbl_addr(dev, wcid);
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w27 = mt76_rr(dev, addr + 27 * 4);
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w27 &= ~MT_WTBL_W27_CC_BW_SEL;
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w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, bw);
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w27 |= FIELD_PREP(MT_WTBL_W27_CC_BW_SEL, rd.bw);
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w5 = mt76_rr(dev, addr + 5 * 4);
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w5 &= ~(MT_WTBL_W5_BW_CAP | MT_WTBL_W5_CHANGE_BW_RATE |
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MT_WTBL_W5_MPDU_OK_COUNT |
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MT_WTBL_W5_MPDU_FAIL_COUNT |
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MT_WTBL_W5_RATE_IDX);
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w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, bw) |
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FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE, bw_idx ? bw_idx - 1 : 7);
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w5 |= FIELD_PREP(MT_WTBL_W5_BW_CAP, rd.bw) |
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FIELD_PREP(MT_WTBL_W5_CHANGE_BW_RATE,
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rd.bw_idx ? rd.bw_idx - 1 : 7);
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mt76_wr(dev, MT_WTBL_RIUCR0, w5);
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mt76_wr(dev, MT_WTBL_RIUCR1,
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FIELD_PREP(MT_WTBL_RIUCR1_RATE0, probe_val) |
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FIELD_PREP(MT_WTBL_RIUCR1_RATE1, val[0]) |
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FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, val[1]));
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FIELD_PREP(MT_WTBL_RIUCR1_RATE0, rd.probe_val) |
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FIELD_PREP(MT_WTBL_RIUCR1_RATE1, rd.val[0]) |
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FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, rd.val[1]));
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mt76_wr(dev, MT_WTBL_RIUCR2,
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FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, val[1] >> 8) |
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FIELD_PREP(MT_WTBL_RIUCR2_RATE3, val[1]) |
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FIELD_PREP(MT_WTBL_RIUCR2_RATE4, val[2]) |
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FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, val[2]));
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FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, rd.val[1] >> 8) |
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FIELD_PREP(MT_WTBL_RIUCR2_RATE3, rd.val[1]) |
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FIELD_PREP(MT_WTBL_RIUCR2_RATE4, rd.val[2]) |
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FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, rd.val[2]));
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mt76_wr(dev, MT_WTBL_RIUCR3,
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FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, val[2] >> 4) |
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FIELD_PREP(MT_WTBL_RIUCR3_RATE6, val[3]) |
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FIELD_PREP(MT_WTBL_RIUCR3_RATE7, val[3]));
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FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, rd.val[2] >> 4) |
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FIELD_PREP(MT_WTBL_RIUCR3_RATE6, rd.val[3]) |
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FIELD_PREP(MT_WTBL_RIUCR3_RATE7, rd.val[3]));
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mt76_wr(dev, MT_WTBL_UPDATE,
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FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
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@ -944,7 +959,8 @@ void mt7615_mac_set_rates(struct mt7615_phy *phy, struct mt7615_sta *sta,
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mt76_wr(dev, addr + 27 * 4, w27);
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mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */
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sta->rate_set_tsf = (mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0)) | rateset;
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sta->rate_set_tsf = mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0);
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sta->rate_set_tsf |= rd.rateset;
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if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET))
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mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
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@ -90,6 +90,18 @@ struct mt7615_rate_set {
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struct ieee80211_tx_rate rates[4];
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};
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struct mt7615_rate_desc {
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struct list_head node;
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struct mt7615_sta *sta;
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bool rateset;
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u16 probe_val;
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u16 val[4];
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u8 bw_idx;
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u8 bw;
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};
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struct mt7615_sta {
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struct mt76_wcid wcid; /* must be first */
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