From 03ea8676919af21b99bea01f18ef1a271d19f92f Mon Sep 17 00:00:00 2001 From: "Anton D. Stavinskii" Date: Wed, 26 Nov 2025 21:21:16 +0400 Subject: [PATCH 1/5] riscv: dts: sophgo: cv180x: fix USB dwc2 FIFO sizes I've tested the current dwc2 FIFO configuration and found that USB device mode breaks in ECM mode when transmitting frames larger than 128 bytes. For example, large ICMP packets or iperf3 traffic cause the USB link to hang and eventually disconnect without any messages in dmesg. After switching to more conservative FIFO sizes, ECM becomes stable and no longer drops the connection. iperf3 now shows ~130 Mbit/s RX and ~100 Mbit/s TX on SG2002 (MilkV Duo 256M). Fix the FIFO sizes accordingly. Signed-off-by: Anton D. Stavinskii Reviewed-by: Inochi Amaoto Fixes: e307248a3c2d ("riscv: dts: sophgo: Add USB support for cv18xx") Link: https://lore.kernel.org/r/20251126172115.1894190-2-stavinsky@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv180x.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi index 1b2b1969a648..06b0ce5a2db7 100644 --- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi @@ -438,8 +438,8 @@ usb: usb@4340000 { clocks = <&clk CLK_AXI4_USB>, <&clk CLK_APB_USB>; clock-names = "otg", "utmi"; g-np-tx-fifo-size = <32>; - g-rx-fifo-size = <536>; - g-tx-fifo-size = <768 512 512 384 128 128>; + g-rx-fifo-size = <1536>; + g-tx-fifo-size = <128 128 64 64 64 64 32 32>; interrupts = ; phys = <&usbphy>; phy-names = "usb2-phy"; From 9e81c522680db5998c872fb91ff7877cf3d8ff42 Mon Sep 17 00:00:00 2001 From: Michael Orlitzky Date: Wed, 7 Jan 2026 06:29:22 -0500 Subject: [PATCH 2/5] riscv: dts: sophgo: enable hardware clock (RTC) on the Milk-V Pioneer These boards have a working hardware clock if you put a CR-1220 battery in them. We enable it using information from a 6.1.x vendor kernel. Reviewed-by: Chen Wang Signed-off-by: Michael Orlitzky Link: https://lore.kernel.org/r/20260107112922.20013-2-michael@orlitzky.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index 54d8386bf9c0..ecf8c1e29079 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -52,6 +52,17 @@ &emmc { status = "okay"; }; +&i2c0 { + pinctrl-0 = <&i2c0_cfg>; + pinctrl-names = "default"; + status = "okay"; + + rtc: rtc@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + }; +}; + &i2c1 { pinctrl-0 = <&i2c1_cfg>; pinctrl-names = "default"; @@ -89,6 +100,16 @@ sdhci-emmc-rst-pwr-pins { }; }; + i2c0_cfg: i2c0-cfg { + i2c0-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <26800>; + input-schmitt-enable; + }; + }; + i2c1_cfg: i2c1-cfg { i2c1-pins { pinmux = , From 5e6836e735f9c9c5e8e1d1dce02dfed5fe566e8f Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 13 Jan 2026 10:38:26 +0800 Subject: [PATCH 3/5] riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi As we have a separate CPU dtsi file, move the PLIC and CLINT node to the CPU dtsi file. This will make the sg2042.dtsi focus on peripheral devices, and make the CPU dtsi force CPU related devices. Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/20260113023828.790136-1-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 305 ++++++++++++++++++++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 303 ------------------- 2 files changed, 305 insertions(+), 303 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi index 94a4b71acad3..509488eee432 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi @@ -2189,4 +2189,309 @@ l2_cache15: cache-controller-15 { cache-unified; }; }; + + soc { + intc: interrupt-controller@7090000000 { + compatible = "sophgo,sg2042-plic", "thead,c900-plic"; + #address-cells = <0>; + #interrupt-cells = <2>; + reg = <0x00000070 0x90000000 0x00000000 0x04000000>; + interrupt-controller; + interrupts-extended = + <&cpu0_intc 11>, <&cpu0_intc 9>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>, + <&cpu5_intc 11>, <&cpu5_intc 9>, + <&cpu6_intc 11>, <&cpu6_intc 9>, + <&cpu7_intc 11>, <&cpu7_intc 9>, + <&cpu8_intc 11>, <&cpu8_intc 9>, + <&cpu9_intc 11>, <&cpu9_intc 9>, + <&cpu10_intc 11>, <&cpu10_intc 9>, + <&cpu11_intc 11>, <&cpu11_intc 9>, + <&cpu12_intc 11>, <&cpu12_intc 9>, + <&cpu13_intc 11>, <&cpu13_intc 9>, + <&cpu14_intc 11>, <&cpu14_intc 9>, + <&cpu15_intc 11>, <&cpu15_intc 9>, + <&cpu16_intc 11>, <&cpu16_intc 9>, + <&cpu17_intc 11>, <&cpu17_intc 9>, + <&cpu18_intc 11>, <&cpu18_intc 9>, + <&cpu19_intc 11>, <&cpu19_intc 9>, + <&cpu20_intc 11>, <&cpu20_intc 9>, + <&cpu21_intc 11>, <&cpu21_intc 9>, + <&cpu22_intc 11>, <&cpu22_intc 9>, + <&cpu23_intc 11>, <&cpu23_intc 9>, + <&cpu24_intc 11>, <&cpu24_intc 9>, + <&cpu25_intc 11>, <&cpu25_intc 9>, + <&cpu26_intc 11>, <&cpu26_intc 9>, + <&cpu27_intc 11>, <&cpu27_intc 9>, + <&cpu28_intc 11>, <&cpu28_intc 9>, + <&cpu29_intc 11>, <&cpu29_intc 9>, + <&cpu30_intc 11>, <&cpu30_intc 9>, + <&cpu31_intc 11>, <&cpu31_intc 9>, + <&cpu32_intc 11>, <&cpu32_intc 9>, + <&cpu33_intc 11>, <&cpu33_intc 9>, + <&cpu34_intc 11>, <&cpu34_intc 9>, + <&cpu35_intc 11>, <&cpu35_intc 9>, + <&cpu36_intc 11>, <&cpu36_intc 9>, + <&cpu37_intc 11>, <&cpu37_intc 9>, + <&cpu38_intc 11>, <&cpu38_intc 9>, + <&cpu39_intc 11>, <&cpu39_intc 9>, + <&cpu40_intc 11>, <&cpu40_intc 9>, + <&cpu41_intc 11>, <&cpu41_intc 9>, + <&cpu42_intc 11>, <&cpu42_intc 9>, + <&cpu43_intc 11>, <&cpu43_intc 9>, + <&cpu44_intc 11>, <&cpu44_intc 9>, + <&cpu45_intc 11>, <&cpu45_intc 9>, + <&cpu46_intc 11>, <&cpu46_intc 9>, + <&cpu47_intc 11>, <&cpu47_intc 9>, + <&cpu48_intc 11>, <&cpu48_intc 9>, + <&cpu49_intc 11>, <&cpu49_intc 9>, + <&cpu50_intc 11>, <&cpu50_intc 9>, + <&cpu51_intc 11>, <&cpu51_intc 9>, + <&cpu52_intc 11>, <&cpu52_intc 9>, + <&cpu53_intc 11>, <&cpu53_intc 9>, + <&cpu54_intc 11>, <&cpu54_intc 9>, + <&cpu55_intc 11>, <&cpu55_intc 9>, + <&cpu56_intc 11>, <&cpu56_intc 9>, + <&cpu57_intc 11>, <&cpu57_intc 9>, + <&cpu58_intc 11>, <&cpu58_intc 9>, + <&cpu59_intc 11>, <&cpu59_intc 9>, + <&cpu60_intc 11>, <&cpu60_intc 9>, + <&cpu61_intc 11>, <&cpu61_intc 9>, + <&cpu62_intc 11>, <&cpu62_intc 9>, + <&cpu63_intc 11>, <&cpu63_intc 9>; + riscv,ndev = <224>; + }; + + clint_mswi: interrupt-controller@7094000000 { + compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; + reg = <0x00000070 0x94000000 0x00000000 0x00004000>; + interrupts-extended = <&cpu0_intc 3>, + <&cpu1_intc 3>, + <&cpu2_intc 3>, + <&cpu3_intc 3>, + <&cpu4_intc 3>, + <&cpu5_intc 3>, + <&cpu6_intc 3>, + <&cpu7_intc 3>, + <&cpu8_intc 3>, + <&cpu9_intc 3>, + <&cpu10_intc 3>, + <&cpu11_intc 3>, + <&cpu12_intc 3>, + <&cpu13_intc 3>, + <&cpu14_intc 3>, + <&cpu15_intc 3>, + <&cpu16_intc 3>, + <&cpu17_intc 3>, + <&cpu18_intc 3>, + <&cpu19_intc 3>, + <&cpu20_intc 3>, + <&cpu21_intc 3>, + <&cpu22_intc 3>, + <&cpu23_intc 3>, + <&cpu24_intc 3>, + <&cpu25_intc 3>, + <&cpu26_intc 3>, + <&cpu27_intc 3>, + <&cpu28_intc 3>, + <&cpu29_intc 3>, + <&cpu30_intc 3>, + <&cpu31_intc 3>, + <&cpu32_intc 3>, + <&cpu33_intc 3>, + <&cpu34_intc 3>, + <&cpu35_intc 3>, + <&cpu36_intc 3>, + <&cpu37_intc 3>, + <&cpu38_intc 3>, + <&cpu39_intc 3>, + <&cpu40_intc 3>, + <&cpu41_intc 3>, + <&cpu42_intc 3>, + <&cpu43_intc 3>, + <&cpu44_intc 3>, + <&cpu45_intc 3>, + <&cpu46_intc 3>, + <&cpu47_intc 3>, + <&cpu48_intc 3>, + <&cpu49_intc 3>, + <&cpu50_intc 3>, + <&cpu51_intc 3>, + <&cpu52_intc 3>, + <&cpu53_intc 3>, + <&cpu54_intc 3>, + <&cpu55_intc 3>, + <&cpu56_intc 3>, + <&cpu57_intc 3>, + <&cpu58_intc 3>, + <&cpu59_intc 3>, + <&cpu60_intc 3>, + <&cpu61_intc 3>, + <&cpu62_intc 3>, + <&cpu63_intc 3>; + }; + + clint_mtimer0: timer@70ac004000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu0_intc 7>, + <&cpu1_intc 7>, + <&cpu2_intc 7>, + <&cpu3_intc 7>; + }; + + clint_mtimer1: timer@70ac014000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu4_intc 7>, + <&cpu5_intc 7>, + <&cpu6_intc 7>, + <&cpu7_intc 7>; + }; + + clint_mtimer2: timer@70ac024000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu8_intc 7>, + <&cpu9_intc 7>, + <&cpu10_intc 7>, + <&cpu11_intc 7>; + }; + + clint_mtimer3: timer@70ac034000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu12_intc 7>, + <&cpu13_intc 7>, + <&cpu14_intc 7>, + <&cpu15_intc 7>; + }; + + clint_mtimer4: timer@70ac044000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu16_intc 7>, + <&cpu17_intc 7>, + <&cpu18_intc 7>, + <&cpu19_intc 7>; + }; + + clint_mtimer5: timer@70ac054000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu20_intc 7>, + <&cpu21_intc 7>, + <&cpu22_intc 7>, + <&cpu23_intc 7>; + }; + + clint_mtimer6: timer@70ac064000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu24_intc 7>, + <&cpu25_intc 7>, + <&cpu26_intc 7>, + <&cpu27_intc 7>; + }; + + clint_mtimer7: timer@70ac074000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu28_intc 7>, + <&cpu29_intc 7>, + <&cpu30_intc 7>, + <&cpu31_intc 7>; + }; + + clint_mtimer8: timer@70ac084000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu32_intc 7>, + <&cpu33_intc 7>, + <&cpu34_intc 7>, + <&cpu35_intc 7>; + }; + + clint_mtimer9: timer@70ac094000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu36_intc 7>, + <&cpu37_intc 7>, + <&cpu38_intc 7>, + <&cpu39_intc 7>; + }; + + clint_mtimer10: timer@70ac0a4000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu40_intc 7>, + <&cpu41_intc 7>, + <&cpu42_intc 7>, + <&cpu43_intc 7>; + }; + + clint_mtimer11: timer@70ac0b4000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu44_intc 7>, + <&cpu45_intc 7>, + <&cpu46_intc 7>, + <&cpu47_intc 7>; + }; + + clint_mtimer12: timer@70ac0c4000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu48_intc 7>, + <&cpu49_intc 7>, + <&cpu50_intc 7>, + <&cpu51_intc 7>; + }; + + clint_mtimer13: timer@70ac0d4000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu52_intc 7>, + <&cpu53_intc 7>, + <&cpu54_intc 7>, + <&cpu55_intc 7>; + }; + + clint_mtimer14: timer@70ac0e4000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu56_intc 7>, + <&cpu57_intc 7>, + <&cpu58_intc 7>, + <&cpu59_intc 7>; + }; + + clint_mtimer15: timer@70ac0f4000 { + compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; + reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; + reg-names = "mtimecmp"; + interrupts-extended = <&cpu60_intc 7>, + <&cpu61_intc 7>, + <&cpu62_intc 7>, + <&cpu63_intc 7>; + }; + }; }; diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index ec99da39150f..e6891f95d479 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -352,309 +352,6 @@ pcie_rc3: pcie@7062800000 { status = "disabled"; }; - clint_mswi: interrupt-controller@7094000000 { - compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; - reg = <0x00000070 0x94000000 0x00000000 0x00004000>; - interrupts-extended = <&cpu0_intc 3>, - <&cpu1_intc 3>, - <&cpu2_intc 3>, - <&cpu3_intc 3>, - <&cpu4_intc 3>, - <&cpu5_intc 3>, - <&cpu6_intc 3>, - <&cpu7_intc 3>, - <&cpu8_intc 3>, - <&cpu9_intc 3>, - <&cpu10_intc 3>, - <&cpu11_intc 3>, - <&cpu12_intc 3>, - <&cpu13_intc 3>, - <&cpu14_intc 3>, - <&cpu15_intc 3>, - <&cpu16_intc 3>, - <&cpu17_intc 3>, - <&cpu18_intc 3>, - <&cpu19_intc 3>, - <&cpu20_intc 3>, - <&cpu21_intc 3>, - <&cpu22_intc 3>, - <&cpu23_intc 3>, - <&cpu24_intc 3>, - <&cpu25_intc 3>, - <&cpu26_intc 3>, - <&cpu27_intc 3>, - <&cpu28_intc 3>, - <&cpu29_intc 3>, - <&cpu30_intc 3>, - <&cpu31_intc 3>, - <&cpu32_intc 3>, - <&cpu33_intc 3>, - <&cpu34_intc 3>, - <&cpu35_intc 3>, - <&cpu36_intc 3>, - <&cpu37_intc 3>, - <&cpu38_intc 3>, - <&cpu39_intc 3>, - <&cpu40_intc 3>, - <&cpu41_intc 3>, - <&cpu42_intc 3>, - <&cpu43_intc 3>, - <&cpu44_intc 3>, - <&cpu45_intc 3>, - <&cpu46_intc 3>, - <&cpu47_intc 3>, - <&cpu48_intc 3>, - <&cpu49_intc 3>, - <&cpu50_intc 3>, - <&cpu51_intc 3>, - <&cpu52_intc 3>, - <&cpu53_intc 3>, - <&cpu54_intc 3>, - <&cpu55_intc 3>, - <&cpu56_intc 3>, - <&cpu57_intc 3>, - <&cpu58_intc 3>, - <&cpu59_intc 3>, - <&cpu60_intc 3>, - <&cpu61_intc 3>, - <&cpu62_intc 3>, - <&cpu63_intc 3>; - }; - - clint_mtimer0: timer@70ac004000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu0_intc 7>, - <&cpu1_intc 7>, - <&cpu2_intc 7>, - <&cpu3_intc 7>; - }; - - clint_mtimer1: timer@70ac014000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu4_intc 7>, - <&cpu5_intc 7>, - <&cpu6_intc 7>, - <&cpu7_intc 7>; - }; - - clint_mtimer2: timer@70ac024000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu8_intc 7>, - <&cpu9_intc 7>, - <&cpu10_intc 7>, - <&cpu11_intc 7>; - }; - - clint_mtimer3: timer@70ac034000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu12_intc 7>, - <&cpu13_intc 7>, - <&cpu14_intc 7>, - <&cpu15_intc 7>; - }; - - clint_mtimer4: timer@70ac044000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu16_intc 7>, - <&cpu17_intc 7>, - <&cpu18_intc 7>, - <&cpu19_intc 7>; - }; - - clint_mtimer5: timer@70ac054000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu20_intc 7>, - <&cpu21_intc 7>, - <&cpu22_intc 7>, - <&cpu23_intc 7>; - }; - - clint_mtimer6: timer@70ac064000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu24_intc 7>, - <&cpu25_intc 7>, - <&cpu26_intc 7>, - <&cpu27_intc 7>; - }; - - clint_mtimer7: timer@70ac074000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu28_intc 7>, - <&cpu29_intc 7>, - <&cpu30_intc 7>, - <&cpu31_intc 7>; - }; - - clint_mtimer8: timer@70ac084000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu32_intc 7>, - <&cpu33_intc 7>, - <&cpu34_intc 7>, - <&cpu35_intc 7>; - }; - - clint_mtimer9: timer@70ac094000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu36_intc 7>, - <&cpu37_intc 7>, - <&cpu38_intc 7>, - <&cpu39_intc 7>; - }; - - clint_mtimer10: timer@70ac0a4000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu40_intc 7>, - <&cpu41_intc 7>, - <&cpu42_intc 7>, - <&cpu43_intc 7>; - }; - - clint_mtimer11: timer@70ac0b4000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu44_intc 7>, - <&cpu45_intc 7>, - <&cpu46_intc 7>, - <&cpu47_intc 7>; - }; - - clint_mtimer12: timer@70ac0c4000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu48_intc 7>, - <&cpu49_intc 7>, - <&cpu50_intc 7>, - <&cpu51_intc 7>; - }; - - clint_mtimer13: timer@70ac0d4000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu52_intc 7>, - <&cpu53_intc 7>, - <&cpu54_intc 7>, - <&cpu55_intc 7>; - }; - - clint_mtimer14: timer@70ac0e4000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu56_intc 7>, - <&cpu57_intc 7>, - <&cpu58_intc 7>, - <&cpu59_intc 7>; - }; - - clint_mtimer15: timer@70ac0f4000 { - compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; - reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; - reg-names = "mtimecmp"; - interrupts-extended = <&cpu60_intc 7>, - <&cpu61_intc 7>, - <&cpu62_intc 7>, - <&cpu63_intc 7>; - }; - - intc: interrupt-controller@7090000000 { - compatible = "sophgo,sg2042-plic", "thead,c900-plic"; - #address-cells = <0>; - #interrupt-cells = <2>; - reg = <0x00000070 0x90000000 0x00000000 0x04000000>; - interrupt-controller; - interrupts-extended = - <&cpu0_intc 11>, <&cpu0_intc 9>, - <&cpu1_intc 11>, <&cpu1_intc 9>, - <&cpu2_intc 11>, <&cpu2_intc 9>, - <&cpu3_intc 11>, <&cpu3_intc 9>, - <&cpu4_intc 11>, <&cpu4_intc 9>, - <&cpu5_intc 11>, <&cpu5_intc 9>, - <&cpu6_intc 11>, <&cpu6_intc 9>, - <&cpu7_intc 11>, <&cpu7_intc 9>, - <&cpu8_intc 11>, <&cpu8_intc 9>, - <&cpu9_intc 11>, <&cpu9_intc 9>, - <&cpu10_intc 11>, <&cpu10_intc 9>, - <&cpu11_intc 11>, <&cpu11_intc 9>, - <&cpu12_intc 11>, <&cpu12_intc 9>, - <&cpu13_intc 11>, <&cpu13_intc 9>, - <&cpu14_intc 11>, <&cpu14_intc 9>, - <&cpu15_intc 11>, <&cpu15_intc 9>, - <&cpu16_intc 11>, <&cpu16_intc 9>, - <&cpu17_intc 11>, <&cpu17_intc 9>, - <&cpu18_intc 11>, <&cpu18_intc 9>, - <&cpu19_intc 11>, <&cpu19_intc 9>, - <&cpu20_intc 11>, <&cpu20_intc 9>, - <&cpu21_intc 11>, <&cpu21_intc 9>, - <&cpu22_intc 11>, <&cpu22_intc 9>, - <&cpu23_intc 11>, <&cpu23_intc 9>, - <&cpu24_intc 11>, <&cpu24_intc 9>, - <&cpu25_intc 11>, <&cpu25_intc 9>, - <&cpu26_intc 11>, <&cpu26_intc 9>, - <&cpu27_intc 11>, <&cpu27_intc 9>, - <&cpu28_intc 11>, <&cpu28_intc 9>, - <&cpu29_intc 11>, <&cpu29_intc 9>, - <&cpu30_intc 11>, <&cpu30_intc 9>, - <&cpu31_intc 11>, <&cpu31_intc 9>, - <&cpu32_intc 11>, <&cpu32_intc 9>, - <&cpu33_intc 11>, <&cpu33_intc 9>, - <&cpu34_intc 11>, <&cpu34_intc 9>, - <&cpu35_intc 11>, <&cpu35_intc 9>, - <&cpu36_intc 11>, <&cpu36_intc 9>, - <&cpu37_intc 11>, <&cpu37_intc 9>, - <&cpu38_intc 11>, <&cpu38_intc 9>, - <&cpu39_intc 11>, <&cpu39_intc 9>, - <&cpu40_intc 11>, <&cpu40_intc 9>, - <&cpu41_intc 11>, <&cpu41_intc 9>, - <&cpu42_intc 11>, <&cpu42_intc 9>, - <&cpu43_intc 11>, <&cpu43_intc 9>, - <&cpu44_intc 11>, <&cpu44_intc 9>, - <&cpu45_intc 11>, <&cpu45_intc 9>, - <&cpu46_intc 11>, <&cpu46_intc 9>, - <&cpu47_intc 11>, <&cpu47_intc 9>, - <&cpu48_intc 11>, <&cpu48_intc 9>, - <&cpu49_intc 11>, <&cpu49_intc 9>, - <&cpu50_intc 11>, <&cpu50_intc 9>, - <&cpu51_intc 11>, <&cpu51_intc 9>, - <&cpu52_intc 11>, <&cpu52_intc 9>, - <&cpu53_intc 11>, <&cpu53_intc 9>, - <&cpu54_intc 11>, <&cpu54_intc 9>, - <&cpu55_intc 11>, <&cpu55_intc 9>, - <&cpu56_intc 11>, <&cpu56_intc 9>, - <&cpu57_intc 11>, <&cpu57_intc 9>, - <&cpu58_intc 11>, <&cpu58_intc 9>, - <&cpu59_intc 11>, <&cpu59_intc 9>, - <&cpu60_intc 11>, <&cpu60_intc 9>, - <&cpu61_intc 11>, <&cpu61_intc 9>, - <&cpu62_intc 11>, <&cpu62_intc 9>, - <&cpu63_intc 11>, <&cpu63_intc 9>; - riscv,ndev = <224>; - }; - rstgen: reset-controller@7030013000 { compatible = "sophgo,sg2042-reset"; reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; From ebb87dd74c34a76e1e93041e9329cf9269be35ed Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 13 Jan 2026 10:38:27 +0800 Subject: [PATCH 4/5] riscv: dts: sophgo: fix the node order of SG2042 peripheral In sg2042.dtsi, some peripheral device node does not follow the address order. Reorder them in ascending order by address. Reviewed-by: Chen Wang Link: https://lore.kernel.org/r/20260113023828.790136-2-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2042.dtsi | 176 ++++++++++++------------- 1 file changed, 88 insertions(+), 88 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi index e6891f95d479..9fddf3f0b3b9 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi @@ -264,94 +264,6 @@ clkgen: clock-controller@7030012000 { #clock-cells = <1>; }; - pcie_rc0: pcie@7060000000 { - compatible = "sophgo,sg2042-pcie-host"; - device_type = "pci"; - reg = <0x70 0x60000000 0x0 0x00800000>, - <0x40 0x00000000 0x0 0x00001000>; - reg-names = "reg", "cfg"; - linux,pci-domain = <0>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>, - <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, - <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, - <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, - <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; - bus-range = <0x0 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; - msi-parent = <&msi>; - status = "disabled"; - }; - - pcie_rc1: pcie@7060800000 { - compatible = "sophgo,sg2042-pcie-host"; - device_type = "pci"; - reg = <0x70 0x60800000 0x0 0x00800000>, - <0x44 0x00000000 0x0 0x00001000>; - reg-names = "reg", "cfg"; - linux,pci-domain = <1>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>, - <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, - <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, - <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, - <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; - bus-range = <0x0 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; - msi-parent = <&msi>; - status = "disabled"; - }; - - pcie_rc2: pcie@7062000000 { - compatible = "sophgo,sg2042-pcie-host"; - device_type = "pci"; - reg = <0x70 0x62000000 0x0 0x00800000>, - <0x48 0x00000000 0x0 0x00001000>; - reg-names = "reg", "cfg"; - linux,pci-domain = <2>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>, - <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, - <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, - <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, - <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; - bus-range = <0x0 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; - msi-parent = <&msi>; - status = "disabled"; - }; - - pcie_rc3: pcie@7062800000 { - compatible = "sophgo,sg2042-pcie-host"; - device_type = "pci"; - reg = <0x70 0x62800000 0x0 0x00800000>, - <0x4c 0x00000000 0x0 0x00001000>; - reg-names = "reg", "cfg"; - linux,pci-domain = <3>; - #address-cells = <3>; - #size-cells = <2>; - ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>, - <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, - <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, - <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, - <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; - bus-range = <0x0 0xff>; - vendor-id = <0x1f1c>; - device-id = <0x2042>; - cdns,no-bar-match-nbits = <48>; - msi-parent = <&msi>; - status = "disabled"; - }; - rstgen: reset-controller@7030013000 { compatible = "sophgo,sg2042-reset"; reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; @@ -486,5 +398,93 @@ sd: mmc@704002b000 { "timer"; status = "disabled"; }; + + pcie_rc0: pcie@7060000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x60000000 0x0 0x00800000>, + <0x40 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc1: pcie@7060800000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x60800000 0x0 0x00800000>, + <0x44 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, + <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, + <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc2: pcie@7062000000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x62000000 0x0 0x00800000>, + <0x48 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <2>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>, + <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; + + pcie_rc3: pcie@7062800000 { + compatible = "sophgo,sg2042-pcie-host"; + device_type = "pci"; + reg = <0x70 0x62800000 0x0 0x00800000>, + <0x4c 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; + linux,pci-domain = <3>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>, + <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, + <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, + <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, + <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; + bus-range = <0x0 0xff>; + vendor-id = <0x1f1c>; + device-id = <0x2042>; + cdns,no-bar-match-nbits = <48>; + msi-parent = <&msi>; + status = "disabled"; + }; }; }; From f16ae81b80ca4e721f4c4ed1f28390115f7721eb Mon Sep 17 00:00:00 2001 From: Guodong Xu Date: Thu, 15 Jan 2026 07:18:59 +0800 Subject: [PATCH 5/5] riscv: dts: sophgo: sg2044: Add "b" ISA extension "b" is ratified (Apr/2024) much later than its components zba/zbb/zbs (Jun/2021). With "b" added into riscv/extensions.yaml, a dependency checking rule is now enforced, which requires that when zba, zbb, and zbs are all specified, "b" must be added as well. Failing to do this will cause dtbs_check schema check warnings. According to uabi.rst, as a single-letter extension, "b" should be added after "c" in canonical order. Update sg2044-cpus.dtsi to conform to this rule. Signed-off-by: Guodong Xu Reviewed-by: Inochi Amaoto Link: https://lore.kernel.org/r/20260115-adding-b-dtsi-v2-3-254dd61cf947@riscstar.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi | 256 ++++++++++---------- 1 file changed, 128 insertions(+), 128 deletions(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi index 523799a1a8b8..3135409c2149 100644 --- a/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi @@ -24,10 +24,10 @@ cpu0: cpu@0 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache0>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -60,10 +60,10 @@ cpu1: cpu@1 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache0>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -96,10 +96,10 @@ cpu2: cpu@2 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache0>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -132,10 +132,10 @@ cpu3: cpu@3 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache0>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -168,10 +168,10 @@ cpu4: cpu@4 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache1>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -204,10 +204,10 @@ cpu5: cpu@5 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache1>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -240,10 +240,10 @@ cpu6: cpu@6 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache1>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -276,10 +276,10 @@ cpu7: cpu@7 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache1>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -312,10 +312,10 @@ cpu8: cpu@8 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache2>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -348,10 +348,10 @@ cpu9: cpu@9 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache2>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -384,10 +384,10 @@ cpu10: cpu@10 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache2>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -420,10 +420,10 @@ cpu11: cpu@11 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache2>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -456,10 +456,10 @@ cpu12: cpu@12 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache3>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -492,10 +492,10 @@ cpu13: cpu@13 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache3>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -528,10 +528,10 @@ cpu14: cpu@14 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache3>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -564,10 +564,10 @@ cpu15: cpu@15 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache3>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -600,10 +600,10 @@ cpu16: cpu@16 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache4>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -636,10 +636,10 @@ cpu17: cpu@17 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache4>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -672,10 +672,10 @@ cpu18: cpu@18 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache4>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -708,10 +708,10 @@ cpu19: cpu@19 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache4>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -744,10 +744,10 @@ cpu20: cpu@20 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache5>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -780,10 +780,10 @@ cpu21: cpu@21 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache5>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -816,10 +816,10 @@ cpu22: cpu@22 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache5>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -852,10 +852,10 @@ cpu23: cpu@23 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache5>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -888,10 +888,10 @@ cpu24: cpu@24 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache6>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -924,10 +924,10 @@ cpu25: cpu@25 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache6>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -960,10 +960,10 @@ cpu26: cpu@26 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache6>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -996,10 +996,10 @@ cpu27: cpu@27 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache6>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1032,10 +1032,10 @@ cpu28: cpu@28 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache7>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1068,10 +1068,10 @@ cpu29: cpu@29 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache7>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1104,10 +1104,10 @@ cpu30: cpu@30 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache7>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1140,10 +1140,10 @@ cpu31: cpu@31 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache7>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1176,10 +1176,10 @@ cpu32: cpu@32 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache8>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1212,10 +1212,10 @@ cpu33: cpu@33 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache8>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1248,10 +1248,10 @@ cpu34: cpu@34 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache8>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1284,10 +1284,10 @@ cpu35: cpu@35 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache8>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1320,10 +1320,10 @@ cpu36: cpu@36 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache9>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1356,10 +1356,10 @@ cpu37: cpu@37 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache9>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1392,10 +1392,10 @@ cpu38: cpu@38 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache9>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1428,10 +1428,10 @@ cpu39: cpu@39 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache9>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1464,10 +1464,10 @@ cpu40: cpu@40 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache10>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1500,10 +1500,10 @@ cpu41: cpu@41 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache10>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1536,10 +1536,10 @@ cpu42: cpu@42 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache10>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1572,10 +1572,10 @@ cpu43: cpu@43 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache10>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1608,10 +1608,10 @@ cpu44: cpu@44 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache11>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1644,10 +1644,10 @@ cpu45: cpu@45 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache11>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1680,10 +1680,10 @@ cpu46: cpu@46 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache11>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1716,10 +1716,10 @@ cpu47: cpu@47 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache11>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1752,10 +1752,10 @@ cpu48: cpu@48 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache12>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1788,10 +1788,10 @@ cpu49: cpu@49 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache12>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1824,10 +1824,10 @@ cpu50: cpu@50 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache12>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1860,10 +1860,10 @@ cpu51: cpu@51 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache12>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1896,10 +1896,10 @@ cpu52: cpu@52 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache13>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1932,10 +1932,10 @@ cpu53: cpu@53 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache13>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -1968,10 +1968,10 @@ cpu54: cpu@54 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache13>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2004,10 +2004,10 @@ cpu55: cpu@55 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache13>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2040,10 +2040,10 @@ cpu56: cpu@56 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache14>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2076,10 +2076,10 @@ cpu57: cpu@57 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache14>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2112,10 +2112,10 @@ cpu58: cpu@58 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache14>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2148,10 +2148,10 @@ cpu59: cpu@59 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache14>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2184,10 +2184,10 @@ cpu60: cpu@60 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache15>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2220,10 +2220,10 @@ cpu61: cpu@61 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache15>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2256,10 +2256,10 @@ cpu62: cpu@62 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache15>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", @@ -2292,10 +2292,10 @@ cpu63: cpu@63 { device_type = "cpu"; mmu-type = "riscv,sv48"; next-level-cache = <&l2_cache15>; - riscv,isa = "rv64imafdcv"; + riscv,isa = "rv64imafdcbv"; riscv,isa-base = "rv64i"; riscv,isa-extensions = "i", "m", "a", "f", "d", "c", - "v", "sscofpmf", "sstc", + "b", "v", "sscofpmf", "sstc", "svinval", "svnapot", "svpbmt", "zawrs", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd",