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RISC-V Devicetrees for v6.20

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Sophgo:
 
 For CV18xx serials:
 Update RX/TX FIFO size to fix the USB transfer issue.
 
 For SG2042:
 Optimize the DTS file format, including moving PLIC/CLINT
 nodes into cpu dtsi and sorting peripheral nodes by address.
 In addition, we also enable RTC for Pioneerbox.
 
 For SG2044:
 Add "b" ISA extension to fix dtbs_check warnings.
 
 Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
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Merge tag 'riscv-sophgo-dt-for-v6.20' of https://github.com/sophgo/linux into soc/dt

RISC-V/Sophgo Devicetrees for v6.20

Sophgo:

For CV18xx serials:
Update RX/TX FIFO size to fix the USB transfer issue.

For SG2042:
Optimize the DTS file format, including moving PLIC/CLINT
nodes into cpu dtsi and sorting peripheral nodes by address.
In addition, we also enable RTC for Pioneerbox.

For SG2044:
Add "b" ISA extension to fix dtbs_check warnings.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

* tag 'riscv-sophgo-dt-for-v6.20' of https://github.com/sophgo/linux:
  riscv: dts: sophgo: sg2044: Add "b" ISA extension
  riscv: dts: sophgo: fix the node order of SG2042 peripheral
  riscv: dts: sophgo: Move PLIC and CLINT node into CPU dtsi
  riscv: dts: sophgo: enable hardware clock (RTC) on the Milk-V Pioneer
  riscv: dts: sophgo: cv180x: fix USB dwc2 FIFO sizes

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2026-01-28 17:11:37 +01:00
commit 8f8f7bccda
5 changed files with 544 additions and 521 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/riscv/boot/dts/sophgo/cv180x.dtsi
View File

@ -438,8 +438,8 @@ usb: usb@4340000 {
clocks = <&clk CLK_AXI4_USB>, <&clk CLK_APB_USB>;
clock-names = "otg", "utmi";
g-np-tx-fifo-size = <32>;
g-rx-fifo-size = <536>;
g-tx-fifo-size = <768 512 512 384 128 128>;
g-rx-fifo-size = <1536>;
g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
interrupts = <SOC_PERIPHERAL_IRQ(14) IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbphy>;
phy-names = "usb2-phy";

305
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
View File

@ -2189,4 +2189,309 @@ l2_cache15: cache-controller-15 {
cache-unified;
};
};
soc {
intc: interrupt-controller@7090000000 {
compatible = "sophgo,sg2042-plic", "thead,c900-plic";
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
interrupt-controller;
interrupts-extended =
<&cpu0_intc 11>, <&cpu0_intc 9>,
<&cpu1_intc 11>, <&cpu1_intc 9>,
<&cpu2_intc 11>, <&cpu2_intc 9>,
<&cpu3_intc 11>, <&cpu3_intc 9>,
<&cpu4_intc 11>, <&cpu4_intc 9>,
<&cpu5_intc 11>, <&cpu5_intc 9>,
<&cpu6_intc 11>, <&cpu6_intc 9>,
<&cpu7_intc 11>, <&cpu7_intc 9>,
<&cpu8_intc 11>, <&cpu8_intc 9>,
<&cpu9_intc 11>, <&cpu9_intc 9>,
<&cpu10_intc 11>, <&cpu10_intc 9>,
<&cpu11_intc 11>, <&cpu11_intc 9>,
<&cpu12_intc 11>, <&cpu12_intc 9>,
<&cpu13_intc 11>, <&cpu13_intc 9>,
<&cpu14_intc 11>, <&cpu14_intc 9>,
<&cpu15_intc 11>, <&cpu15_intc 9>,
<&cpu16_intc 11>, <&cpu16_intc 9>,
<&cpu17_intc 11>, <&cpu17_intc 9>,
<&cpu18_intc 11>, <&cpu18_intc 9>,
<&cpu19_intc 11>, <&cpu19_intc 9>,
<&cpu20_intc 11>, <&cpu20_intc 9>,
<&cpu21_intc 11>, <&cpu21_intc 9>,
<&cpu22_intc 11>, <&cpu22_intc 9>,
<&cpu23_intc 11>, <&cpu23_intc 9>,
<&cpu24_intc 11>, <&cpu24_intc 9>,
<&cpu25_intc 11>, <&cpu25_intc 9>,
<&cpu26_intc 11>, <&cpu26_intc 9>,
<&cpu27_intc 11>, <&cpu27_intc 9>,
<&cpu28_intc 11>, <&cpu28_intc 9>,
<&cpu29_intc 11>, <&cpu29_intc 9>,
<&cpu30_intc 11>, <&cpu30_intc 9>,
<&cpu31_intc 11>, <&cpu31_intc 9>,
<&cpu32_intc 11>, <&cpu32_intc 9>,
<&cpu33_intc 11>, <&cpu33_intc 9>,
<&cpu34_intc 11>, <&cpu34_intc 9>,
<&cpu35_intc 11>, <&cpu35_intc 9>,
<&cpu36_intc 11>, <&cpu36_intc 9>,
<&cpu37_intc 11>, <&cpu37_intc 9>,
<&cpu38_intc 11>, <&cpu38_intc 9>,
<&cpu39_intc 11>, <&cpu39_intc 9>,
<&cpu40_intc 11>, <&cpu40_intc 9>,
<&cpu41_intc 11>, <&cpu41_intc 9>,
<&cpu42_intc 11>, <&cpu42_intc 9>,
<&cpu43_intc 11>, <&cpu43_intc 9>,
<&cpu44_intc 11>, <&cpu44_intc 9>,
<&cpu45_intc 11>, <&cpu45_intc 9>,
<&cpu46_intc 11>, <&cpu46_intc 9>,
<&cpu47_intc 11>, <&cpu47_intc 9>,
<&cpu48_intc 11>, <&cpu48_intc 9>,
<&cpu49_intc 11>, <&cpu49_intc 9>,
<&cpu50_intc 11>, <&cpu50_intc 9>,
<&cpu51_intc 11>, <&cpu51_intc 9>,
<&cpu52_intc 11>, <&cpu52_intc 9>,
<&cpu53_intc 11>, <&cpu53_intc 9>,
<&cpu54_intc 11>, <&cpu54_intc 9>,
<&cpu55_intc 11>, <&cpu55_intc 9>,
<&cpu56_intc 11>, <&cpu56_intc 9>,
<&cpu57_intc 11>, <&cpu57_intc 9>,
<&cpu58_intc 11>, <&cpu58_intc 9>,
<&cpu59_intc 11>, <&cpu59_intc 9>,
<&cpu60_intc 11>, <&cpu60_intc 9>,
<&cpu61_intc 11>, <&cpu61_intc 9>,
<&cpu62_intc 11>, <&cpu62_intc 9>,
<&cpu63_intc 11>, <&cpu63_intc 9>;
riscv,ndev = <224>;
};
clint_mswi: interrupt-controller@7094000000 {
compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
interrupts-extended = <&cpu0_intc 3>,
<&cpu1_intc 3>,
<&cpu2_intc 3>,
<&cpu3_intc 3>,
<&cpu4_intc 3>,
<&cpu5_intc 3>,
<&cpu6_intc 3>,
<&cpu7_intc 3>,
<&cpu8_intc 3>,
<&cpu9_intc 3>,
<&cpu10_intc 3>,
<&cpu11_intc 3>,
<&cpu12_intc 3>,
<&cpu13_intc 3>,
<&cpu14_intc 3>,
<&cpu15_intc 3>,
<&cpu16_intc 3>,
<&cpu17_intc 3>,
<&cpu18_intc 3>,
<&cpu19_intc 3>,
<&cpu20_intc 3>,
<&cpu21_intc 3>,
<&cpu22_intc 3>,
<&cpu23_intc 3>,
<&cpu24_intc 3>,
<&cpu25_intc 3>,
<&cpu26_intc 3>,
<&cpu27_intc 3>,
<&cpu28_intc 3>,
<&cpu29_intc 3>,
<&cpu30_intc 3>,
<&cpu31_intc 3>,
<&cpu32_intc 3>,
<&cpu33_intc 3>,
<&cpu34_intc 3>,
<&cpu35_intc 3>,
<&cpu36_intc 3>,
<&cpu37_intc 3>,
<&cpu38_intc 3>,
<&cpu39_intc 3>,
<&cpu40_intc 3>,
<&cpu41_intc 3>,
<&cpu42_intc 3>,
<&cpu43_intc 3>,
<&cpu44_intc 3>,
<&cpu45_intc 3>,
<&cpu46_intc 3>,
<&cpu47_intc 3>,
<&cpu48_intc 3>,
<&cpu49_intc 3>,
<&cpu50_intc 3>,
<&cpu51_intc 3>,
<&cpu52_intc 3>,
<&cpu53_intc 3>,
<&cpu54_intc 3>,
<&cpu55_intc 3>,
<&cpu56_intc 3>,
<&cpu57_intc 3>,
<&cpu58_intc 3>,
<&cpu59_intc 3>,
<&cpu60_intc 3>,
<&cpu61_intc 3>,
<&cpu62_intc 3>,
<&cpu63_intc 3>;
};
clint_mtimer0: timer@70ac004000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu0_intc 7>,
<&cpu1_intc 7>,
<&cpu2_intc 7>,
<&cpu3_intc 7>;
};
clint_mtimer1: timer@70ac014000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu4_intc 7>,
<&cpu5_intc 7>,
<&cpu6_intc 7>,
<&cpu7_intc 7>;
};
clint_mtimer2: timer@70ac024000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu8_intc 7>,
<&cpu9_intc 7>,
<&cpu10_intc 7>,
<&cpu11_intc 7>;
};
clint_mtimer3: timer@70ac034000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu12_intc 7>,
<&cpu13_intc 7>,
<&cpu14_intc 7>,
<&cpu15_intc 7>;
};
clint_mtimer4: timer@70ac044000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu16_intc 7>,
<&cpu17_intc 7>,
<&cpu18_intc 7>,
<&cpu19_intc 7>;
};
clint_mtimer5: timer@70ac054000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu20_intc 7>,
<&cpu21_intc 7>,
<&cpu22_intc 7>,
<&cpu23_intc 7>;
};
clint_mtimer6: timer@70ac064000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu24_intc 7>,
<&cpu25_intc 7>,
<&cpu26_intc 7>,
<&cpu27_intc 7>;
};
clint_mtimer7: timer@70ac074000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu28_intc 7>,
<&cpu29_intc 7>,
<&cpu30_intc 7>,
<&cpu31_intc 7>;
};
clint_mtimer8: timer@70ac084000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu32_intc 7>,
<&cpu33_intc 7>,
<&cpu34_intc 7>,
<&cpu35_intc 7>;
};
clint_mtimer9: timer@70ac094000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu36_intc 7>,
<&cpu37_intc 7>,
<&cpu38_intc 7>,
<&cpu39_intc 7>;
};
clint_mtimer10: timer@70ac0a4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu40_intc 7>,
<&cpu41_intc 7>,
<&cpu42_intc 7>,
<&cpu43_intc 7>;
};
clint_mtimer11: timer@70ac0b4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu44_intc 7>,
<&cpu45_intc 7>,
<&cpu46_intc 7>,
<&cpu47_intc 7>;
};
clint_mtimer12: timer@70ac0c4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu48_intc 7>,
<&cpu49_intc 7>,
<&cpu50_intc 7>,
<&cpu51_intc 7>;
};
clint_mtimer13: timer@70ac0d4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu52_intc 7>,
<&cpu53_intc 7>,
<&cpu54_intc 7>,
<&cpu55_intc 7>;
};
clint_mtimer14: timer@70ac0e4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu56_intc 7>,
<&cpu57_intc 7>,
<&cpu58_intc 7>,
<&cpu59_intc 7>;
};
clint_mtimer15: timer@70ac0f4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu60_intc 7>,
<&cpu61_intc 7>,
<&cpu62_intc 7>,
<&cpu63_intc 7>;
};
};
};

21
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
View File

@ -52,6 +52,17 @@ &emmc {
status = "okay";
};
&i2c0 {
pinctrl-0 = <&i2c0_cfg>;
pinctrl-names = "default";
status = "okay";
rtc: rtc@68 {
compatible = "dallas,ds1307";
reg = <0x68>;
};
};
&i2c1 {
pinctrl-0 = <&i2c1_cfg>;
pinctrl-names = "default";
@ -89,6 +100,16 @@ sdhci-emmc-rst-pwr-pins {
};
};
i2c0_cfg: i2c0-cfg {
i2c0-pins {
pinmux = <PINMUX(PIN_IIC0_SDA, 0)>,
<PINMUX(PIN_IIC0_SCL, 0)>;
bias-pull-up;
drive-strength-microamp = <26800>;
input-schmitt-enable;
};
};
i2c1_cfg: i2c1-cfg {
i2c1-pins {
pinmux = <PINMUX(PIN_IIC1_SDA, 0)>,

479
arch/riscv/boot/dts/sophgo/sg2042.dtsi
View File

@ -264,397 +264,6 @@ clkgen: clock-controller@7030012000 {
#clock-cells = <1>;
};
pcie_rc0: pcie@7060000000 {
compatible = "sophgo,sg2042-pcie-host";
device_type = "pci";
reg = <0x70 0x60000000 0x0 0x00800000>,
<0x40 0x00000000 0x0 0x00001000>;
reg-names = "reg", "cfg";
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>,
<0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>,
<0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>,
<0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
<0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
bus-range = <0x0 0xff>;
vendor-id = <0x1f1c>;
device-id = <0x2042>;
cdns,no-bar-match-nbits = <48>;
msi-parent = <&msi>;
status = "disabled";
};
pcie_rc1: pcie@7060800000 {
compatible = "sophgo,sg2042-pcie-host";
device_type = "pci";
reg = <0x70 0x60800000 0x0 0x00800000>,
<0x44 0x00000000 0x0 0x00001000>;
reg-names = "reg", "cfg";
linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>,
<0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>,
<0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>,
<0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>,
<0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>;
bus-range = <0x0 0xff>;
vendor-id = <0x1f1c>;
device-id = <0x2042>;
cdns,no-bar-match-nbits = <48>;
msi-parent = <&msi>;
status = "disabled";
};
pcie_rc2: pcie@7062000000 {
compatible = "sophgo,sg2042-pcie-host";
device_type = "pci";
reg = <0x70 0x62000000 0x0 0x00800000>,
<0x48 0x00000000 0x0 0x00001000>;
reg-names = "reg", "cfg";
linux,pci-domain = <2>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>,
<0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>,
<0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>,
<0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>,
<0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>;
bus-range = <0x0 0xff>;
vendor-id = <0x1f1c>;
device-id = <0x2042>;
cdns,no-bar-match-nbits = <48>;
msi-parent = <&msi>;
status = "disabled";
};
pcie_rc3: pcie@7062800000 {
compatible = "sophgo,sg2042-pcie-host";
device_type = "pci";
reg = <0x70 0x62800000 0x0 0x00800000>,
<0x4c 0x00000000 0x0 0x00001000>;
reg-names = "reg", "cfg";
linux,pci-domain = <3>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>,
<0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>,
<0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>,
<0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>,
<0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>;
bus-range = <0x0 0xff>;
vendor-id = <0x1f1c>;
device-id = <0x2042>;
cdns,no-bar-match-nbits = <48>;
msi-parent = <&msi>;
status = "disabled";
};
clint_mswi: interrupt-controller@7094000000 {
compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
interrupts-extended = <&cpu0_intc 3>,
<&cpu1_intc 3>,
<&cpu2_intc 3>,
<&cpu3_intc 3>,
<&cpu4_intc 3>,
<&cpu5_intc 3>,
<&cpu6_intc 3>,
<&cpu7_intc 3>,
<&cpu8_intc 3>,
<&cpu9_intc 3>,
<&cpu10_intc 3>,
<&cpu11_intc 3>,
<&cpu12_intc 3>,
<&cpu13_intc 3>,
<&cpu14_intc 3>,
<&cpu15_intc 3>,
<&cpu16_intc 3>,
<&cpu17_intc 3>,
<&cpu18_intc 3>,
<&cpu19_intc 3>,
<&cpu20_intc 3>,
<&cpu21_intc 3>,
<&cpu22_intc 3>,
<&cpu23_intc 3>,
<&cpu24_intc 3>,
<&cpu25_intc 3>,
<&cpu26_intc 3>,
<&cpu27_intc 3>,
<&cpu28_intc 3>,
<&cpu29_intc 3>,
<&cpu30_intc 3>,
<&cpu31_intc 3>,
<&cpu32_intc 3>,
<&cpu33_intc 3>,
<&cpu34_intc 3>,
<&cpu35_intc 3>,
<&cpu36_intc 3>,
<&cpu37_intc 3>,
<&cpu38_intc 3>,
<&cpu39_intc 3>,
<&cpu40_intc 3>,
<&cpu41_intc 3>,
<&cpu42_intc 3>,
<&cpu43_intc 3>,
<&cpu44_intc 3>,
<&cpu45_intc 3>,
<&cpu46_intc 3>,
<&cpu47_intc 3>,
<&cpu48_intc 3>,
<&cpu49_intc 3>,
<&cpu50_intc 3>,
<&cpu51_intc 3>,
<&cpu52_intc 3>,
<&cpu53_intc 3>,
<&cpu54_intc 3>,
<&cpu55_intc 3>,
<&cpu56_intc 3>,
<&cpu57_intc 3>,
<&cpu58_intc 3>,
<&cpu59_intc 3>,
<&cpu60_intc 3>,
<&cpu61_intc 3>,
<&cpu62_intc 3>,
<&cpu63_intc 3>;
};
clint_mtimer0: timer@70ac004000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu0_intc 7>,
<&cpu1_intc 7>,
<&cpu2_intc 7>,
<&cpu3_intc 7>;
};
clint_mtimer1: timer@70ac014000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu4_intc 7>,
<&cpu5_intc 7>,
<&cpu6_intc 7>,
<&cpu7_intc 7>;
};
clint_mtimer2: timer@70ac024000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu8_intc 7>,
<&cpu9_intc 7>,
<&cpu10_intc 7>,
<&cpu11_intc 7>;
};
clint_mtimer3: timer@70ac034000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu12_intc 7>,
<&cpu13_intc 7>,
<&cpu14_intc 7>,
<&cpu15_intc 7>;
};
clint_mtimer4: timer@70ac044000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu16_intc 7>,
<&cpu17_intc 7>,
<&cpu18_intc 7>,
<&cpu19_intc 7>;
};
clint_mtimer5: timer@70ac054000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu20_intc 7>,
<&cpu21_intc 7>,
<&cpu22_intc 7>,
<&cpu23_intc 7>;
};
clint_mtimer6: timer@70ac064000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu24_intc 7>,
<&cpu25_intc 7>,
<&cpu26_intc 7>,
<&cpu27_intc 7>;
};
clint_mtimer7: timer@70ac074000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu28_intc 7>,
<&cpu29_intc 7>,
<&cpu30_intc 7>,
<&cpu31_intc 7>;
};
clint_mtimer8: timer@70ac084000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu32_intc 7>,
<&cpu33_intc 7>,
<&cpu34_intc 7>,
<&cpu35_intc 7>;
};
clint_mtimer9: timer@70ac094000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu36_intc 7>,
<&cpu37_intc 7>,
<&cpu38_intc 7>,
<&cpu39_intc 7>;
};
clint_mtimer10: timer@70ac0a4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu40_intc 7>,
<&cpu41_intc 7>,
<&cpu42_intc 7>,
<&cpu43_intc 7>;
};
clint_mtimer11: timer@70ac0b4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu44_intc 7>,
<&cpu45_intc 7>,
<&cpu46_intc 7>,
<&cpu47_intc 7>;
};
clint_mtimer12: timer@70ac0c4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu48_intc 7>,
<&cpu49_intc 7>,
<&cpu50_intc 7>,
<&cpu51_intc 7>;
};
clint_mtimer13: timer@70ac0d4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu52_intc 7>,
<&cpu53_intc 7>,
<&cpu54_intc 7>,
<&cpu55_intc 7>;
};
clint_mtimer14: timer@70ac0e4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu56_intc 7>,
<&cpu57_intc 7>,
<&cpu58_intc 7>,
<&cpu59_intc 7>;
};
clint_mtimer15: timer@70ac0f4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
reg-names = "mtimecmp";
interrupts-extended = <&cpu60_intc 7>,
<&cpu61_intc 7>,
<&cpu62_intc 7>,
<&cpu63_intc 7>;
};
intc: interrupt-controller@7090000000 {
compatible = "sophgo,sg2042-plic", "thead,c900-plic";
#address-cells = <0>;
#interrupt-cells = <2>;
reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
interrupt-controller;
interrupts-extended =
<&cpu0_intc 11>, <&cpu0_intc 9>,
<&cpu1_intc 11>, <&cpu1_intc 9>,
<&cpu2_intc 11>, <&cpu2_intc 9>,
<&cpu3_intc 11>, <&cpu3_intc 9>,
<&cpu4_intc 11>, <&cpu4_intc 9>,
<&cpu5_intc 11>, <&cpu5_intc 9>,
<&cpu6_intc 11>, <&cpu6_intc 9>,
<&cpu7_intc 11>, <&cpu7_intc 9>,
<&cpu8_intc 11>, <&cpu8_intc 9>,
<&cpu9_intc 11>, <&cpu9_intc 9>,
<&cpu10_intc 11>, <&cpu10_intc 9>,
<&cpu11_intc 11>, <&cpu11_intc 9>,
<&cpu12_intc 11>, <&cpu12_intc 9>,
<&cpu13_intc 11>, <&cpu13_intc 9>,
<&cpu14_intc 11>, <&cpu14_intc 9>,
<&cpu15_intc 11>, <&cpu15_intc 9>,
<&cpu16_intc 11>, <&cpu16_intc 9>,
<&cpu17_intc 11>, <&cpu17_intc 9>,
<&cpu18_intc 11>, <&cpu18_intc 9>,
<&cpu19_intc 11>, <&cpu19_intc 9>,
<&cpu20_intc 11>, <&cpu20_intc 9>,
<&cpu21_intc 11>, <&cpu21_intc 9>,
<&cpu22_intc 11>, <&cpu22_intc 9>,
<&cpu23_intc 11>, <&cpu23_intc 9>,
<&cpu24_intc 11>, <&cpu24_intc 9>,
<&cpu25_intc 11>, <&cpu25_intc 9>,
<&cpu26_intc 11>, <&cpu26_intc 9>,
<&cpu27_intc 11>, <&cpu27_intc 9>,
<&cpu28_intc 11>, <&cpu28_intc 9>,
<&cpu29_intc 11>, <&cpu29_intc 9>,
<&cpu30_intc 11>, <&cpu30_intc 9>,
<&cpu31_intc 11>, <&cpu31_intc 9>,
<&cpu32_intc 11>, <&cpu32_intc 9>,
<&cpu33_intc 11>, <&cpu33_intc 9>,
<&cpu34_intc 11>, <&cpu34_intc 9>,
<&cpu35_intc 11>, <&cpu35_intc 9>,
<&cpu36_intc 11>, <&cpu36_intc 9>,
<&cpu37_intc 11>, <&cpu37_intc 9>,
<&cpu38_intc 11>, <&cpu38_intc 9>,
<&cpu39_intc 11>, <&cpu39_intc 9>,
<&cpu40_intc 11>, <&cpu40_intc 9>,
<&cpu41_intc 11>, <&cpu41_intc 9>,
<&cpu42_intc 11>, <&cpu42_intc 9>,
<&cpu43_intc 11>, <&cpu43_intc 9>,
<&cpu44_intc 11>, <&cpu44_intc 9>,
<&cpu45_intc 11>, <&cpu45_intc 9>,
<&cpu46_intc 11>, <&cpu46_intc 9>,
<&cpu47_intc 11>, <&cpu47_intc 9>,
<&cpu48_intc 11>, <&cpu48_intc 9>,
<&cpu49_intc 11>, <&cpu49_intc 9>,
<&cpu50_intc 11>, <&cpu50_intc 9>,
<&cpu51_intc 11>, <&cpu51_intc 9>,
<&cpu52_intc 11>, <&cpu52_intc 9>,
<&cpu53_intc 11>, <&cpu53_intc 9>,
<&cpu54_intc 11>, <&cpu54_intc 9>,
<&cpu55_intc 11>, <&cpu55_intc 9>,
<&cpu56_intc 11>, <&cpu56_intc 9>,
<&cpu57_intc 11>, <&cpu57_intc 9>,
<&cpu58_intc 11>, <&cpu58_intc 9>,
<&cpu59_intc 11>, <&cpu59_intc 9>,
<&cpu60_intc 11>, <&cpu60_intc 9>,
<&cpu61_intc 11>, <&cpu61_intc 9>,
<&cpu62_intc 11>, <&cpu62_intc 9>,
<&cpu63_intc 11>, <&cpu63_intc 9>;
riscv,ndev = <224>;
};
rstgen: reset-controller@7030013000 {
compatible = "sophgo,sg2042-reset";
reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
@ -789,5 +398,93 @@ sd: mmc@704002b000 {
"timer";
status = "disabled";
};
pcie_rc0: pcie@7060000000 {
compatible = "sophgo,sg2042-pcie-host";
device_type = "pci";
reg = <0x70 0x60000000 0x0 0x00800000>,
<0x40 0x00000000 0x0 0x00001000>;
reg-names = "reg", "cfg";
linux,pci-domain = <0>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x40 0xc0000000 0x0 0x00400000>,
<0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>,
<0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>,
<0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
<0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
bus-range = <0x0 0xff>;
vendor-id = <0x1f1c>;
device-id = <0x2042>;
cdns,no-bar-match-nbits = <48>;
msi-parent = <&msi>;
status = "disabled";
};
pcie_rc1: pcie@7060800000 {
compatible = "sophgo,sg2042-pcie-host";
device_type = "pci";
reg = <0x70 0x60800000 0x0 0x00800000>,
<0x44 0x00000000 0x0 0x00001000>;
reg-names = "reg", "cfg";
linux,pci-domain = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x44 0xc0400000 0x0 0x00400000>,
<0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>,
<0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>,
<0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>,
<0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>;
bus-range = <0x0 0xff>;
vendor-id = <0x1f1c>;
device-id = <0x2042>;
cdns,no-bar-match-nbits = <48>;
msi-parent = <&msi>;
status = "disabled";
};
pcie_rc2: pcie@7062000000 {
compatible = "sophgo,sg2042-pcie-host";
device_type = "pci";
reg = <0x70 0x62000000 0x0 0x00800000>,
<0x48 0x00000000 0x0 0x00001000>;
reg-names = "reg", "cfg";
linux,pci-domain = <2>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x48 0xc0800000 0x0 0x00400000>,
<0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>,
<0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>,
<0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>,
<0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>;
bus-range = <0x0 0xff>;
vendor-id = <0x1f1c>;
device-id = <0x2042>;
cdns,no-bar-match-nbits = <48>;
msi-parent = <&msi>;
status = "disabled";
};
pcie_rc3: pcie@7062800000 {
compatible = "sophgo,sg2042-pcie-host";
device_type = "pci";
reg = <0x70 0x62800000 0x0 0x00800000>,
<0x4c 0x00000000 0x0 0x00001000>;
reg-names = "reg", "cfg";
linux,pci-domain = <3>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x00000000 0x4c 0xc0c00000 0x0 0x00400000>,
<0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>,
<0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>,
<0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>,
<0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>;
bus-range = <0x0 0xff>;
vendor-id = <0x1f1c>;
device-id = <0x2042>;
cdns,no-bar-match-nbits = <48>;
msi-parent = <&msi>;
status = "disabled";
};
};
};

256
arch/riscv/boot/dts/sophgo/sg2044-cpus.dtsi
View File

@ -24,10 +24,10 @@ cpu0: cpu@0 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache0>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -60,10 +60,10 @@ cpu1: cpu@1 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache0>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -96,10 +96,10 @@ cpu2: cpu@2 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache0>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -132,10 +132,10 @@ cpu3: cpu@3 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache0>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -168,10 +168,10 @@ cpu4: cpu@4 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache1>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -204,10 +204,10 @@ cpu5: cpu@5 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache1>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -240,10 +240,10 @@ cpu6: cpu@6 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache1>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -276,10 +276,10 @@ cpu7: cpu@7 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache1>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -312,10 +312,10 @@ cpu8: cpu@8 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache2>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -348,10 +348,10 @@ cpu9: cpu@9 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache2>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -384,10 +384,10 @@ cpu10: cpu@10 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache2>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -420,10 +420,10 @@ cpu11: cpu@11 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache2>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -456,10 +456,10 @@ cpu12: cpu@12 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache3>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -492,10 +492,10 @@ cpu13: cpu@13 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache3>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -528,10 +528,10 @@ cpu14: cpu@14 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache3>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -564,10 +564,10 @@ cpu15: cpu@15 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache3>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -600,10 +600,10 @@ cpu16: cpu@16 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache4>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -636,10 +636,10 @@ cpu17: cpu@17 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache4>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -672,10 +672,10 @@ cpu18: cpu@18 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache4>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -708,10 +708,10 @@ cpu19: cpu@19 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache4>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -744,10 +744,10 @@ cpu20: cpu@20 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache5>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -780,10 +780,10 @@ cpu21: cpu@21 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache5>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -816,10 +816,10 @@ cpu22: cpu@22 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache5>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -852,10 +852,10 @@ cpu23: cpu@23 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache5>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -888,10 +888,10 @@ cpu24: cpu@24 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache6>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -924,10 +924,10 @@ cpu25: cpu@25 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache6>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -960,10 +960,10 @@ cpu26: cpu@26 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache6>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -996,10 +996,10 @@ cpu27: cpu@27 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache6>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1032,10 +1032,10 @@ cpu28: cpu@28 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache7>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1068,10 +1068,10 @@ cpu29: cpu@29 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache7>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1104,10 +1104,10 @@ cpu30: cpu@30 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache7>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1140,10 +1140,10 @@ cpu31: cpu@31 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache7>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1176,10 +1176,10 @@ cpu32: cpu@32 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache8>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1212,10 +1212,10 @@ cpu33: cpu@33 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache8>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1248,10 +1248,10 @@ cpu34: cpu@34 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache8>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1284,10 +1284,10 @@ cpu35: cpu@35 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache8>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1320,10 +1320,10 @@ cpu36: cpu@36 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache9>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1356,10 +1356,10 @@ cpu37: cpu@37 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache9>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1392,10 +1392,10 @@ cpu38: cpu@38 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache9>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1428,10 +1428,10 @@ cpu39: cpu@39 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache9>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1464,10 +1464,10 @@ cpu40: cpu@40 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache10>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1500,10 +1500,10 @@ cpu41: cpu@41 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache10>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1536,10 +1536,10 @@ cpu42: cpu@42 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache10>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1572,10 +1572,10 @@ cpu43: cpu@43 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache10>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1608,10 +1608,10 @@ cpu44: cpu@44 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache11>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1644,10 +1644,10 @@ cpu45: cpu@45 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache11>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1680,10 +1680,10 @@ cpu46: cpu@46 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache11>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1716,10 +1716,10 @@ cpu47: cpu@47 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache11>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1752,10 +1752,10 @@ cpu48: cpu@48 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache12>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1788,10 +1788,10 @@ cpu49: cpu@49 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache12>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1824,10 +1824,10 @@ cpu50: cpu@50 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache12>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1860,10 +1860,10 @@ cpu51: cpu@51 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache12>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1896,10 +1896,10 @@ cpu52: cpu@52 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache13>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1932,10 +1932,10 @@ cpu53: cpu@53 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache13>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -1968,10 +1968,10 @@ cpu54: cpu@54 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache13>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -2004,10 +2004,10 @@ cpu55: cpu@55 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache13>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -2040,10 +2040,10 @@ cpu56: cpu@56 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache14>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -2076,10 +2076,10 @@ cpu57: cpu@57 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache14>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -2112,10 +2112,10 @@ cpu58: cpu@58 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache14>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -2148,10 +2148,10 @@ cpu59: cpu@59 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache14>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -2184,10 +2184,10 @@ cpu60: cpu@60 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache15>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -2220,10 +2220,10 @@ cpu61: cpu@61 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache15>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -2256,10 +2256,10 @@ cpu62: cpu@62 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache15>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",
@ -2292,10 +2292,10 @@ cpu63: cpu@63 {
device_type = "cpu";
mmu-type = "riscv,sv48";
next-level-cache = <&l2_cache15>;
riscv,isa = "rv64imafdcv";
riscv,isa = "rv64imafdcbv";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"v", "sscofpmf", "sstc",
"b", "v", "sscofpmf", "sstc",
"svinval", "svnapot", "svpbmt",
"zawrs", "zba", "zbb", "zbc",
"zbs", "zca", "zcb", "zcd",