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drm/xe: Define CACHE_MODE_1 as MCR register

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CACHE_MODE_1 is a MCR register for all platforms that currently use it
in the Xe driver.  Use XE_REG_MCR() when defining it.

Fixes: 8cd7e97597 ("drm/xe: Add missing DG2 lrc workarounds")
Fixes: ff063430ca ("drm/xe/mtl: Add some initial MTL workarounds")
Bspec: 66534, 67788
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20260514-rtp-mcr-check-v3-1-30dd47855fee@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
This commit is contained in:
Gustavo Sousa 2026-05-14 18:44:44 -03:00
parent ff1d386a83
commit 8f765f0c05
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/xe/regs/xe_gt_regs.h
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@ -152,7 +152,7 @@
#define XEHPG_INSTDONE_GEOM_SVGUNIT XE_REG_MCR(0x666c)
#define CACHE_MODE_1 XE_REG(0x7004, XE_REG_OPTION_MASKED)
#define CACHE_MODE_1 XE_REG_MCR(0x7004, XE_REG_OPTION_MASKED)
#define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11)
#define COMMON_SLICE_CHICKEN1 XE_REG(0x7010, XE_REG_OPTION_MASKED)