From 8f5453b4c59c8c258ecfa1eb51784695627466f9 Mon Sep 17 00:00:00 2001 From: Madhuri Medasani Date: Tue, 31 Aug 2021 09:30:48 +0530 Subject: [PATCH] clk: qcom: clk-regmap: Update type for rate in clk prepare On 32 bit the PLL frequency can be beyond the range of the `int` leads to improper assignment, so update rate type to 'unsigned long'. Change-Id: I50f03ea95b3d934c4936087998f832373e620e46 Signed-off-by: Madhuri Medasani --- drivers/clk/qcom/clk-regmap.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/clk-regmap.c b/drivers/clk/qcom/clk-regmap.c index 4c0261cbcb18..a6c2e4b4bce6 100644 --- a/drivers/clk/qcom/clk-regmap.c +++ b/drivers/clk/qcom/clk-regmap.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (c) 2014, 2019-2020 The Linux Foundation. All rights reserved. + * Copyright (c) 2014, 2019-2021 The Linux Foundation. All rights reserved. */ #include @@ -195,7 +195,7 @@ EXPORT_SYMBOL(clk_post_change_regmap); int clk_prepare_regmap(struct clk_hw *hw) { struct clk_regmap *rclk = to_clk_regmap(hw); - int rate = clk_hw_get_rate(hw); + unsigned long rate = clk_hw_get_rate(hw); int vdd_level; if (!rclk->vdd_data.rate_max)