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drm/amdgpu: Use correct SRIOV macro for gmc_v9_0_vm_fault_interrupt_state

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Under SRIOV, programming to VM_CONTEXT*_CNTL regs failed because the
current macro does not pass through the correct xcc instance.
Use the *REG32_XCC macro in this case.

The behaviour without SRIOV is the same without this patch.

Signed-off-by: Victor Lu <victorchengchi.lu@amd.com>
Reviewed-by: Zhigang Luo <Zhigang.Luo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Victor Lu 2023-12-19 10:22:19 -05:00 committed by Alex Deucher
parent bea07b215d
commit 8f4de8f72e
1 changed files with 4 additions and 4 deletions
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8
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
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@ -496,14 +496,14 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
if (j >= AMDGPU_MMHUB0(0))
tmp = RREG32_SOC15_IP(MMHUB, reg);
else
tmp = RREG32_SOC15_IP(GC, reg);
tmp = RREG32_XCC(reg, j);
tmp &= ~bits;
if (j >= AMDGPU_MMHUB0(0))
WREG32_SOC15_IP(MMHUB, reg, tmp);
else
WREG32_SOC15_IP(GC, reg, tmp);
WREG32_XCC(reg, tmp, j);
}
}
break;
@ -524,14 +524,14 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
if (j >= AMDGPU_MMHUB0(0))
tmp = RREG32_SOC15_IP(MMHUB, reg);
else
tmp = RREG32_SOC15_IP(GC, reg);
tmp = RREG32_XCC(reg, j);
tmp |= bits;
if (j >= AMDGPU_MMHUB0(0))
WREG32_SOC15_IP(MMHUB, reg, tmp);
else
WREG32_SOC15_IP(GC, reg, tmp);
WREG32_XCC(reg, tmp, j);
}
}
break;