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drm/msm/a6xx: Simplify min_acc_len calculation

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It's only necessary for some lower end parts.
Also rename it to min_acc_len_64b to denote that if set, the minimum
access length is 64 bits, 32b otherwise.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/660977/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
This commit is contained in:
Konrad Dybcio 2025-06-26 11:02:37 +02:00 committed by Rob Clark
parent b6ce504c71
commit 8f18e87957
1 changed files with 9 additions and 9 deletions
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18
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
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@ -611,14 +611,12 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
if (IS_ERR(gpu->common_ubwc_cfg))
return PTR_ERR(gpu->common_ubwc_cfg);
gpu->ubwc_config.min_acc_len = 0;
gpu->ubwc_config.ubwc_swizzle = 0x6;
gpu->ubwc_config.macrotile_mode = 0;
gpu->ubwc_config.highest_bank_bit = 15;
if (adreno_is_a610(gpu)) {
gpu->ubwc_config.highest_bank_bit = 13;
gpu->ubwc_config.min_acc_len = 1;
gpu->ubwc_config.ubwc_swizzle = 0x7;
}
@ -664,10 +662,8 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
gpu->ubwc_config.macrotile_mode = 1;
}
if (adreno_is_a702(gpu)) {
if (adreno_is_a702(gpu))
gpu->ubwc_config.highest_bank_bit = 14;
gpu->ubwc_config.min_acc_len = 1;
}
return 0;
}
@ -687,6 +683,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
u32 level2_swizzling_dis = !(cfg->ubwc_swizzle & BIT(1));
bool ubwc_mode = qcom_ubwc_get_ubwc_mode(cfg);
bool amsbc = cfg->ubwc_enc_version >= UBWC_3_0;
bool min_acc_len_64b = false;
u8 uavflagprd_inv = 0;
u32 hbb_hi = hbb >> 2;
u32 hbb_lo = hbb & 3;
@ -694,22 +691,25 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
if (adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu))
uavflagprd_inv = 2;
if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu))
min_acc_len_64b = true;
gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
level2_swizzling_dis << 12 |
rgb565_predicator << 11 |
hbb_hi << 10 | amsbc << 4 |
adreno_gpu->ubwc_config.min_acc_len << 3 |
min_acc_len_64b << 3 |
hbb_lo << 1 | ubwc_mode);
gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL,
level2_swizzling_dis << 6 | hbb_hi << 4 |
adreno_gpu->ubwc_config.min_acc_len << 3 |
min_acc_len_64b << 3 |
hbb_lo << 1 | ubwc_mode);
gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
level2_swizzling_dis << 12 | hbb_hi << 10 |
uavflagprd_inv << 4 |
adreno_gpu->ubwc_config.min_acc_len << 3 |
min_acc_len_64b << 3 |
hbb_lo << 1 | ubwc_mode);
if (adreno_is_a7xx(adreno_gpu))
@ -717,7 +717,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
FIELD_PREP(GENMASK(8, 5), hbb_lo));
gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL,
adreno_gpu->ubwc_config.min_acc_len << 23 | hbb_lo << 21);
min_acc_len_64b << 23 | hbb_lo << 21);
gpu_write(gpu, REG_A6XX_RBBM_NC_MODE_CNTL,
adreno_gpu->ubwc_config.macrotile_mode);