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drm/imagination: Move FWCORE_* macros to register defines

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Move FWCORE_* macros to pvr_rogue_cr_defs.h where they should have been
from the beginning.

Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
Reviewed-by: Alessio Belle <alessio.belle@imgtec.com>
Link: https://patch.msgid.link/20260810-b4-unify-repeated-reg-defs-and-move-fwcore-macros-v2-2-991ae813fd88@imgtec.com
Signed-off-by: Alessio Belle <alessio.belle@imgtec.com>
This commit is contained in:
Matt Coster 2026-08-10 11:35:20 +03:00 committed by Alessio Belle
parent cf43f918de
commit 8f07803fcf
3 changed files with 5 additions and 11 deletions
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5
drivers/gpu/drm/imagination/pvr_fw_riscv.c
View File

@ -23,10 +23,11 @@ static int
pvr_riscv_wrapper_init(struct pvr_device *pvr_dev)
{
const u64 common_opts =
((u64)(ROGUE_FW_HEAP_RISCV_SIZE >> FWCORE_ADDR_REMAP_CONFIGx_SIZE_ALIGNSHIFT)
((u64)(ROGUE_FW_HEAP_RISCV_SIZE
>> ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_SIZE_ALIGNSHIFT)
<< ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_SIZE_SHIFT) |
((u64)MMU_CONTEXT_MAPPING_FWPRIV
<< FWCORE_ADDR_REMAP_CONFIGx_MMU_CONTEXT_SHIFT);
<< ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_CBASE_SHIFT);
u64 code_addr = pvr_fw_obj_get_gpu_addr(pvr_dev->fw_dev.mem.code_obj);
u64 data_addr = pvr_fw_obj_get_gpu_addr(pvr_dev->fw_dev.mem.data_obj);

2
drivers/gpu/drm/imagination/pvr_rogue_cr_defs.h
View File

@ -3029,6 +3029,8 @@
#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_FETCH_EN_EN 0x1000000000000000ULL
#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_SIZE_SHIFT 44U
#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_SIZE_CLRMSK 0xF0000FFFFFFFFFFFULL
#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_SIZE_ALIGNSHIFT 12U
#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_SIZE_ALIGNSIZE 4096U
#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_CBASE_SHIFT 40U
#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_CBASE_CLRMSK 0xFFFFF8FFFFFFFFFFULL
#define ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_DEVVADDR_SHIFT 12U

9
drivers/gpu/drm/imagination/pvr_rogue_defs.h
View File

@ -96,15 +96,6 @@
/* Utility macro for accessing instances of repeated registers */
#define PVR_CR_REPEAT_X(REG, N) ((REG##_REPEAT_BASE) + (N) * (REG##_REPEAT_OFFSET))
/*
* FWCORE wrapper register defines
*/
#define FWCORE_ADDR_REMAP_CONFIGx_MMU_CONTEXT_SHIFT \
ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_CBASE_SHIFT
#define FWCORE_ADDR_REMAP_CONFIGx_MMU_CONTEXT_CLRMSK \
ROGUE_CR_FWCORE_ADDR_REMAP_CONFIGx_CBASE_CLRMSK
#define FWCORE_ADDR_REMAP_CONFIGx_SIZE_ALIGNSHIFT (12U)
#define ROGUE_MAX_COMPUTE_SHARED_REGISTERS (2 * 1024)
#define ROGUE_MAX_VERTEX_SHARED_REGISTERS 1024
#define ROGUE_MAX_PIXEL_SHARED_REGISTERS 1024