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RISC-V Fixes for 6.2-rc8
* A fix to avoid partial TLB fences for huge pages, which are disallowed
by the ISA.
* A fix to to avoid missing a frame when dumping stacks.
* A fix to avoid misaligned accesses (and possibly overflows) in
kprobes.
* A fix for a race condition in tracking page dirtiness.
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Merge tag 'riscv-for-linus-6.2-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V fixes from Palmer Dabbelt:
"This is a little bigger that I'd hope for this late in the cycle, but
they're all pretty concrete fixes and the only one that's bigger than
a few lines is pmdp_collapse_flush() (which is almost all
boilerplate/comment). It's also all bug fixes for issues that have
been around for a while.
So I think it's not all that scary, just bad timing.
- avoid partial TLB fences for huge pages, which are disallowed by
the ISA
- avoid missing a frame when dumping stacks
- avoid misaligned accesses (and possibly overflows) in kprobes
- fix a race condition in tracking page dirtiness"
* tag 'riscv-for-linus-6.2-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
riscv: Fixup race condition on PG_dcache_clean in flush_icache_pte
riscv: kprobe: Fixup misaligned load text
riscv: stacktrace: Fix missing the first frame
riscv: mm: Implement pmdp_collapse_flush for THP
This commit is contained in:
commit
8e9a8427a1
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@ -721,6 +721,10 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
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page_table_check_pmd_set(vma->vm_mm, address, pmdp, pmd);
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return __pmd(atomic_long_xchg((atomic_long_t *)pmdp, pmd_val(pmd)));
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}
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#define pmdp_collapse_flush pmdp_collapse_flush
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extern pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
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unsigned long address, pmd_t *pmdp);
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#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
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/*
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@ -65,16 +65,18 @@ static bool __kprobes arch_check_kprobe(struct kprobe *p)
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int __kprobes arch_prepare_kprobe(struct kprobe *p)
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{
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unsigned long probe_addr = (unsigned long)p->addr;
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u16 *insn = (u16 *)p->addr;
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if (probe_addr & 0x1)
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if ((unsigned long)insn & 0x1)
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return -EILSEQ;
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if (!arch_check_kprobe(p))
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return -EILSEQ;
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/* copy instruction */
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p->opcode = *p->addr;
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p->opcode = (kprobe_opcode_t)(*insn++);
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if (GET_INSN_LENGTH(p->opcode) == 4)
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p->opcode |= (kprobe_opcode_t)(*insn) << 16;
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/* decode instruction */
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switch (riscv_probe_decode_insn(p->addr, &p->ainsn.api)) {
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@ -32,6 +32,7 @@ void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs,
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fp = (unsigned long)__builtin_frame_address(0);
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sp = current_stack_pointer;
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pc = (unsigned long)walk_stackframe;
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level = -1;
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} else {
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/* task blocked in __switch_to */
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fp = task->thread.s[0];
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@ -43,7 +44,7 @@ void notrace walk_stackframe(struct task_struct *task, struct pt_regs *regs,
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unsigned long low, high;
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struct stackframe *frame;
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if (unlikely(!__kernel_text_address(pc) || (level++ >= 1 && !fn(arg, pc))))
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if (unlikely(!__kernel_text_address(pc) || (level++ >= 0 && !fn(arg, pc))))
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break;
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/* Validate frame pointer */
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@ -90,8 +90,10 @@ void flush_icache_pte(pte_t pte)
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if (PageHuge(page))
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page = compound_head(page);
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if (!test_and_set_bit(PG_dcache_clean, &page->flags))
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if (!test_bit(PG_dcache_clean, &page->flags)) {
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flush_icache_all();
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set_bit(PG_dcache_clean, &page->flags);
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}
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}
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#endif /* CONFIG_MMU */
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@ -81,3 +81,23 @@ int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
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}
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#endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
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unsigned long address, pmd_t *pmdp)
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{
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pmd_t pmd = pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp);
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VM_BUG_ON(address & ~HPAGE_PMD_MASK);
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VM_BUG_ON(pmd_trans_huge(*pmdp));
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/*
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* When leaf PTE entries (regular pages) are collapsed into a leaf
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* PMD entry (huge page), a valid non-leaf PTE is converted into a
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* valid leaf PTE at the level 1 page table. Since the sfence.vma
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* forms that specify an address only apply to leaf PTEs, we need a
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* global flush here. collapse_huge_page() assumes these flushes are
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* eager, so just do the fence here.
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*/
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flush_tlb_mm(vma->vm_mm);
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return pmd;
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}
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#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
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