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drm/i915/cdclk: Introduce HAS_2PPC()

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We'll need to check for the "does the platform do 2 pixels per clock?"
thing in a few places. Add a feature macro for it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20260715120926.10786-3-ville.syrjala@linux.intel.com
Reviewed-by: Nemesa Garg <nemesa.garg@intel.com>
This commit is contained in:
Ville Syrjälä 2026-07-15 15:09:24 +03:00
parent 04e1c59b34
commit 8e4c3b38ac
2 changed files with 2 additions and 1 deletions
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2
drivers/gpu/drm/i915/display/intel_cdclk.c
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@ -2910,7 +2910,7 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
/* pixels per CDCLK */
int intel_cdclk_ppc(struct intel_display *display, bool double_wide)
{
return DISPLAY_VER(display) >= 10 || double_wide ? 2 : 1;
return HAS_2PPC(display) || double_wide ? 2 : 1;
}
/* max pixel rate as % of CDCLK (not accounting for PPC) */

1
drivers/gpu/drm/i915/display/intel_display_device.h
View File

@ -146,6 +146,7 @@ struct intel_display_platforms {
func(supports_tv);
#define HAS_128B_Y_TILING(__display) (!(__display)->platform.i915g && !(__display)->platform.i915gm)
#define HAS_2PPC(__display) (DISPLAY_VER(__display) >= 10)
#define HAS_4TILE(__display) ((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
#define HAS_ASYNC_FLIPS(__display) (DISPLAY_VER(__display) >= 5)
#define HAS_AS_SDP(__display) (DISPLAY_VER(__display) >= 13)