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arm64: dts: renesas: r9a08g046: Add wdt device node

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The RZ/G3L SOC has 3 watchdog timer channels:
  - channel0 (wdt0) for Cortex-A55-CPU Non-Secure,
  - channel1 (wdt1) for Cortex-A55 CPU Secure,
  - channel2 (wdt2) for Cortex-M33 CPU.

Add wdt0 node to RZ/G3L ("R9A08G046") SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260505125921.149682-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2026-05-05 13:59:16 +01:00 committed by Geert Uytterhoeven
parent 89b67a16a5
commit 8e46bc6370
1 changed files with 14 additions and 0 deletions
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14
arch/arm64/boot/dts/renesas/r9a08g046.dtsi
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@ -577,6 +577,20 @@ gic: interrupt-controller@12400000 {
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
wdt0: watchdog@12800800 {
compatible = "renesas,r9a08g046-wdt", "renesas,rzg2l-wdt";
reg = <0 0x12800800 0 0x400>;
clocks = <&cpg CPG_MOD R9A08G046_WDT0_PCLK>,
<&cpg CPG_MOD R9A08G046_WDT0_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A08G046_WDT0_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
};
stmmac_axi_setup: stmmac-axi-config {