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x86/apic: Read and write LVT* APIC registers from HV for SAVIC guests

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The Hypervisor needs information about the current state of the LVT registers
for device emulation and NMIs. So, forward reads and write of these registers
to the hypervisor for Secure AVIC enabled guests.

Signed-off-by: Neeraj Upadhyay <Neeraj.Upadhyay@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Tianyu Lan <tiala@microsoft.com>
Link: https://lore.kernel.org/20250828111356.208972-1-Neeraj.Upadhyay@amd.com
This commit is contained in:
Neeraj Upadhyay 2025-08-28 16:43:56 +05:30 committed by Borislav Petkov (AMD)
parent 28bbfad229
commit 8e3714305a
1 changed files with 10 additions and 10 deletions
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20
arch/x86/kernel/apic/x2apic_savic.c
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@ -67,6 +67,11 @@ static u32 savic_read(u32 reg)
case APIC_TMICT:
case APIC_TMCCT:
case APIC_TDCR:
case APIC_LVTTHMR:
case APIC_LVTPC:
case APIC_LVT0:
case APIC_LVT1:
case APIC_LVTERR:
return savic_ghcb_msr_read(reg);
case APIC_ID:
case APIC_LVR:
@ -76,11 +81,6 @@ static u32 savic_read(u32 reg)
case APIC_LDR:
case APIC_SPIV:
case APIC_ESR:
case APIC_LVTTHMR:
case APIC_LVTPC:
case APIC_LVT0:
case APIC_LVT1:
case APIC_LVTERR:
case APIC_EFEAT:
case APIC_ECTRL:
case APIC_SEOI:
@ -205,18 +205,18 @@ static void savic_write(u32 reg, u32 data)
case APIC_LVTT:
case APIC_TMICT:
case APIC_TDCR:
savic_ghcb_msr_write(reg, data);
break;
case APIC_LVT0:
case APIC_LVT1:
case APIC_LVTTHMR:
case APIC_LVTPC:
case APIC_LVTERR:
savic_ghcb_msr_write(reg, data);
break;
case APIC_TASKPRI:
case APIC_EOI:
case APIC_SPIV:
case SAVIC_NMI_REQ:
case APIC_ESR:
case APIC_LVTTHMR:
case APIC_LVTPC:
case APIC_LVTERR:
case APIC_ECTRL:
case APIC_SEOI:
case APIC_IER: