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drm/xe/mocs: update MOCS table for xe2
Looks like there were some changes at some point here for preferring L4 uncached for some of the indexes. Triple checked the PAT settings also, but that looks all correct as per current BSpec. BSpec: 71582 Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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parent
975e4a3795
commit
8e35780233
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@ -366,9 +366,9 @@ static const struct xe_mocs_entry mtl_mocs_desc[] = {
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static const struct xe_mocs_entry xe2_mocs_table[] = {
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/* Defer to PAT */
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MOCS_ENTRY(0, XE2_L3_0_WB | L4_0_WB, 0),
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/* Cached L3 + L4 */
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MOCS_ENTRY(1, IG_PAT | XE2_L3_0_WB | L4_0_WB, 0),
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MOCS_ENTRY(0, XE2_L3_0_WB | L4_3_UC, 0),
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/* Cached L3, Uncached L4 */
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MOCS_ENTRY(1, IG_PAT | XE2_L3_0_WB | L4_3_UC, 0),
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/* Uncached L3, Cached L4 */
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MOCS_ENTRY(2, IG_PAT | XE2_L3_3_UC | L4_0_WB, 0),
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/* Uncached L3 + L4 */
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@ -390,8 +390,8 @@ static unsigned int get_mocs_settings(struct xe_device *xe,
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info->table = xe2_mocs_table;
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info->n_entries = XE2_NUM_MOCS_ENTRIES;
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info->uc_index = 3;
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info->wb_index = 1;
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info->unused_entries_index = 1;
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info->wb_index = 4;
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info->unused_entries_index = 4;
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break;
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case XE_PVC:
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info->size = ARRAY_SIZE(pvc_mocs_desc);
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