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Add support for "Fast CPPC" which allows some CPUs to operate a tighter
loop for passive mode. -----BEGIN PGP SIGNATURE----- iQJOBAABCgA4FiEECwtuSU6dXvs5GA2aLRkspiR3AnYFAmZowfYaHG1hcmlvLmxp bW9uY2llbGxvQGFtZC5jb20ACgkQLRkspiR3AnaBgg//Y5NstlTa50RmjY3j0xRl h4lBj/cQQ2mEz/CDnAGMuE+EJQecKL3SgqKKoF/vihG/ODtcRb0wl+fQ4AUbnkpP qKmVMKBvmAVfTv5kRtbPOXx3YfQCe9pZOFZaEC2TF/gKYc4Se316gZo9hkQ2lJAw 9jjURUUwCkfHw9TAqBpu4w9GOVrcFhzshib8iKpPcjNFkjpuRa3nDovHfTFAxyzx 6WRVR9Y8mQNU4zZuOeOktg6+G/nquy0Zfdd3Z3OR3OA1FwI+bPFYTiXFvnTPeXus jFVZNwBGEbPS95aBCj3Ka2urDeEJZNJu09khh/DViMDk/IteD7Ddo1DsF7YyVC7t AU9OmvECVKhaVk5oGAB3SKkRCeKKYMY6R0bFmhUZX2CFg3oxOfNMp0HCl1w67iVG TgjJT8aTYjcW15KVn/QDF94q1QdOGxclAJXKvP3hO2Sod19dj8Y8QPAOj7RKGdGS yjg7isPG82BCI9upnXxQq9uBqDpAfnqpuAbHMXyFkGyF2f9yfmLTo+PUIxTLLBIo 7VHNSUVQpXdi2dOCP4KQITs/W9geXniVVrqK3VJ1u4MzmRGIds5a1w0Xk7DvL7FO 258rLTmdnGaSAN4Sz9RgdC4fHqKlJXo7XkCWUzbNCtuPl0SzizBHXOQ6xqRT9kDD SHfZKXNFoLfHDrdy00Nk1PM= =6763 -----END PGP SIGNATURE----- Merge tag 'amd-pstate-v6.11-2024-06-11' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/superm1/linux Merge amd-pstate driver updates for v6.11 from Mario Mario Limonciello: "Add support for "Fast CPPC" which allows some CPUs to operate a tighter loop for passive mode." * tag 'amd-pstate-v6.11-2024-06-11' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/superm1/linux: cpufreq: amd-pstate: change cpu freq transition delay for some models x86/cpufeatures: Add AMD FAST CPPC feature flag
This commit is contained in:
commit
8e184ac079
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@ -470,6 +470,7 @@
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#define X86_FEATURE_BHI_CTRL (21*32+ 2) /* "" BHI_DIS_S HW control available */
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#define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* "" BHI_DIS_S HW control enabled */
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#define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* "" Clear branch history at vmexit using SW loop */
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#define X86_FEATURE_FAST_CPPC (21*32 + 5) /* "" AMD Fast CPPC */
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/*
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* BUG word(s)
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@ -45,6 +45,7 @@ static const struct cpuid_bit cpuid_bits[] = {
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{ X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 },
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{ X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 },
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{ X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
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{ X86_FEATURE_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 },
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{ X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 },
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{ X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 },
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{ X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 },
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@ -51,6 +51,7 @@
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#define AMD_PSTATE_TRANSITION_LATENCY 20000
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#define AMD_PSTATE_TRANSITION_DELAY 1000
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#define AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY 600
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#define CPPC_HIGHEST_PERF_PERFORMANCE 196
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#define CPPC_HIGHEST_PERF_DEFAULT 166
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@ -849,8 +850,12 @@ static u32 amd_pstate_get_transition_delay_us(unsigned int cpu)
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u32 transition_delay_ns;
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transition_delay_ns = cppc_get_transition_latency(cpu);
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if (transition_delay_ns == CPUFREQ_ETERNAL)
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return AMD_PSTATE_TRANSITION_DELAY;
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if (transition_delay_ns == CPUFREQ_ETERNAL) {
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if (cpu_feature_enabled(X86_FEATURE_FAST_CPPC))
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return AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY;
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else
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return AMD_PSTATE_TRANSITION_DELAY;
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}
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return transition_delay_ns / NSEC_PER_USEC;
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}
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