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iwlwifi: pcie: remove TR/CR tail allocations
The TR/CR tail data are meant to be per-queue-arrays, however, we allocate them completely wrong (we have a separate allocation per queue). Looking at this more closely, it turns out that the hardware never uses these - we have a separate free list per RX queue and maintain a write pointer for that in a register, and the RX itself is indicated in the RB status (rb_stts) DMA region. Despite nothing using the tail pointers, the hardware will unconditionally access them to write updates, even when we aren't using CRs/TRs. Give it dummy values that we never use/update so it can do that without causing trouble. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Luca Coelho <luciano.coelho@intel.com> Link: https://lore.kernel.org/r/iwlwifi.20210617110647.5f5764e04c46.I4d5de1929be048085767f1234a1e07b517ab6a2d@changeid Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
This commit is contained in:
parent
bef99c7d91
commit
8e08e191fc
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@ -138,8 +138,15 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
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/* Allocate prph information
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* currently we don't assign to the prph info anything, but it would get
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* assigned later */
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prph_info = dma_alloc_coherent(trans->dev, sizeof(*prph_info),
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* assigned later
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*
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* We also use the second half of this page to give the device some
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* dummy TR/CR tail pointers - which shouldn't be necessary as we don't
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* use this, but the hardware still reads/writes there and we can't let
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* it go do that with a NULL pointer.
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*/
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BUILD_BUG_ON(sizeof(*prph_info) > PAGE_SIZE / 2);
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prph_info = dma_alloc_coherent(trans->dev, PAGE_SIZE,
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&trans_pcie->prph_info_dma_addr,
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GFP_KERNEL);
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if (!prph_info) {
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@ -166,13 +173,9 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
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ctxt_info_gen3->cr_head_idx_arr_base_addr =
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cpu_to_le64(trans_pcie->rxq->rb_stts_dma);
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ctxt_info_gen3->tr_tail_idx_arr_base_addr =
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cpu_to_le64(trans_pcie->rxq->tr_tail_dma);
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cpu_to_le64(trans_pcie->prph_info_dma_addr + PAGE_SIZE / 2);
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ctxt_info_gen3->cr_tail_idx_arr_base_addr =
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cpu_to_le64(trans_pcie->rxq->cr_tail_dma);
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ctxt_info_gen3->cr_idx_arr_size =
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cpu_to_le16(IWL_NUM_OF_COMPLETION_RINGS);
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ctxt_info_gen3->tr_idx_arr_size =
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cpu_to_le16(IWL_NUM_OF_TRANSFER_RINGS);
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cpu_to_le64(trans_pcie->prph_info_dma_addr + 3 * PAGE_SIZE / 4);
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ctxt_info_gen3->mtr_base_addr =
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cpu_to_le64(trans->txqs.txq[trans->txqs.cmd.q_id]->dma_addr);
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ctxt_info_gen3->mcr_base_addr =
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@ -216,10 +219,8 @@ int iwl_pcie_ctxt_info_gen3_init(struct iwl_trans *trans,
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trans_pcie->ctxt_info_dma_addr);
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trans_pcie->ctxt_info_gen3 = NULL;
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err_free_prph_info:
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dma_free_coherent(trans->dev,
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sizeof(*prph_info),
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prph_info,
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trans_pcie->prph_info_dma_addr);
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dma_free_coherent(trans->dev, PAGE_SIZE, prph_info,
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trans_pcie->prph_info_dma_addr);
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err_free_prph_scratch:
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dma_free_coherent(trans->dev,
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@ -251,8 +252,7 @@ void iwl_pcie_ctxt_info_gen3_free(struct iwl_trans *trans)
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trans_pcie->prph_scratch_dma_addr = 0;
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trans_pcie->prph_scratch = NULL;
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dma_free_coherent(trans->dev, sizeof(*trans_pcie->prph_info),
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trans_pcie->prph_info,
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dma_free_coherent(trans->dev, PAGE_SIZE, trans_pcie->prph_info,
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trans_pcie->prph_info_dma_addr);
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trans_pcie->prph_info_dma_addr = 0;
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trans_pcie->prph_info = NULL;
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@ -111,10 +111,6 @@ struct iwl_rx_completion_desc {
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* @bd_dma: bus address of buffer of receive buffer descriptors (rbd)
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* @used_bd: driver's pointer to buffer of used receive buffer descriptors (rbd)
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* @used_bd_dma: physical address of buffer of used receive buffer descriptors (rbd)
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* @tr_tail: driver's pointer to the transmission ring tail buffer
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* @tr_tail_dma: physical address of the buffer for the transmission ring tail
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* @cr_tail: driver's pointer to the completion ring tail buffer
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* @cr_tail_dma: physical address of the buffer for the completion ring tail
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* @read: Shared index to newest available Rx buffer
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* @write: Shared index to oldest written Rx packet
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* @free_count: Number of pre-allocated buffers in rx_free
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@ -142,10 +138,6 @@ struct iwl_rxq {
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struct iwl_rx_completion_desc *cd;
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};
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dma_addr_t used_bd_dma;
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__le16 *tr_tail;
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dma_addr_t tr_tail_dma;
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__le16 *cr_tail;
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dma_addr_t cr_tail_dma;
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u32 read;
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u32 write;
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u32 free_count;
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@ -533,9 +525,6 @@ static inline void _iwl_disable_interrupts(struct iwl_trans *trans)
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IWL_DEBUG_ISR(trans, "Disabled interrupts\n");
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}
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#define IWL_NUM_OF_COMPLETION_RINGS 31
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#define IWL_NUM_OF_TRANSFER_RINGS 527
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static inline int iwl_pcie_get_num_sections(const struct fw_img *fw,
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int start)
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{
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@ -663,7 +663,6 @@ static int iwl_pcie_free_bd_size(struct iwl_trans *trans, bool use_rx_td)
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static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans,
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struct iwl_rxq *rxq)
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{
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struct device *dev = trans->dev;
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bool use_rx_td = (trans->trans_cfg->device_family >=
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IWL_DEVICE_FAMILY_AX210);
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int free_size = iwl_pcie_free_bd_size(trans, use_rx_td);
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@ -685,21 +684,6 @@ static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans,
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rxq->used_bd, rxq->used_bd_dma);
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rxq->used_bd_dma = 0;
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rxq->used_bd = NULL;
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if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210)
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return;
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if (rxq->tr_tail)
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dma_free_coherent(dev, sizeof(__le16),
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rxq->tr_tail, rxq->tr_tail_dma);
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rxq->tr_tail_dma = 0;
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rxq->tr_tail = NULL;
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if (rxq->cr_tail)
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dma_free_coherent(dev, sizeof(__le16),
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rxq->cr_tail, rxq->cr_tail_dma);
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rxq->cr_tail_dma = 0;
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rxq->cr_tail = NULL;
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}
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static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans,
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@ -744,21 +728,6 @@ static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans,
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rxq->rb_stts_dma =
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trans_pcie->base_rb_stts_dma + rxq->id * rb_stts_size;
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if (!use_rx_td)
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return 0;
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/* Allocate the driver's pointer to TR tail */
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rxq->tr_tail = dma_alloc_coherent(dev, sizeof(__le16),
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&rxq->tr_tail_dma, GFP_KERNEL);
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if (!rxq->tr_tail)
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goto err;
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/* Allocate the driver's pointer to CR tail */
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rxq->cr_tail = dma_alloc_coherent(dev, sizeof(__le16),
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&rxq->cr_tail_dma, GFP_KERNEL);
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if (!rxq->cr_tail)
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goto err;
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return 0;
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err:
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@ -1590,9 +1559,6 @@ static int iwl_pcie_rx_handle(struct iwl_trans *trans, int queue, int budget)
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out:
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/* Backtrack one entry */
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rxq->read = i;
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/* update cr tail with the rxq read pointer */
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if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210)
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*rxq->cr_tail = cpu_to_le16(r);
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spin_unlock(&rxq->lock);
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/*
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