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Merge patch series "RISC-V: clarify what some RISCV_ISA* config options do & redo Zbb toolchain dependency"
Conor Dooley <conor@kernel.org> says: Since one depends on the other, albeit trivially, here's a v4 of the Zbb toolchain dep removal alongside the rewording of Kconfig options I'd sent out before the merge window. I think I like this implementation better than v1, but I couldn't think of a good name for a "public" version of __ALTERNATIVE(), so I used it here directly. Unfortunately "ALTERNATIVE_2_CFG" already exists and I couldn't think of a good way to name an alternative macro that allows for several config options that didn't make the distinction sufficiently clear.. Yell if you have better suggestions than I did. I am a wee bit "worried" that this makes the Kconfig option confusing as it isn't immediately obvious if someone is or is not going to get the toolchain based optimisations. Cheers, Conor. * patches from https://lore.kernel.org/r/20241024-aspire-rectify-9982da6943e5@spud: RISC-V: separate Zbb optimisations requiring and not requiring toolchain support RISC-V: clarify what some RISCV_ISA* config options do Link: https://lore.kernel.org/r/20241024-aspire-rectify-9982da6943e5@spud Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
This commit is contained in:
Alexandre Ghiti
commit
8df0cdcc21
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@ -566,7 +566,8 @@ config RISCV_ISA_C
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help
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Adds "C" to the ISA subsets that the toolchain is allowed to emit
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when building Linux, which results in compressed instructions in the
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Linux binary.
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Linux binary. This option produces a kernel that will not run on
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systems that do not support compressed instructions.
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If you don't know what to do here, say Y.
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@ -587,8 +588,8 @@ config RISCV_ISA_SVNAPOT
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depends on RISCV_ALTERNATIVE
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default y
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help
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Allow kernel to detect the Svnapot ISA-extension dynamically at boot
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time and enable its usage.
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Enable support for the Svnapot ISA-extension when it is detected
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at boot.
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The Svnapot extension is used to mark contiguous PTEs as a range
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of contiguous virtual-to-physical translations for a naturally
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@ -606,9 +607,8 @@ config RISCV_ISA_SVPBMT
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depends on RISCV_ALTERNATIVE
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default y
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help
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Adds support to dynamically detect the presence of the Svpbmt
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ISA-extension (Supervisor-mode: page-based memory types) and
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enable its usage.
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Add support for the Svpbmt ISA-extension (Supervisor-mode:
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page-based memory types) in the kernel when it is detected at boot.
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The memory type for a page contains a combination of attributes
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that indicate the cacheability, idempotency, and ordering
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@ -627,14 +627,15 @@ config TOOLCHAIN_HAS_V
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depends on AS_HAS_OPTION_ARCH
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config RISCV_ISA_V
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bool "VECTOR extension support"
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bool "Vector extension support"
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depends on TOOLCHAIN_HAS_V
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depends on FPU
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select DYNAMIC_SIGFRAME
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default y
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help
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Say N here if you want to disable all vector related procedure
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in the kernel.
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Add support for the Vector extension when it is detected at boot.
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When this option is disabled, neither the kernel nor userspace may
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use vector procedures.
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If you don't know what to do here, say Y.
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@ -747,12 +748,12 @@ config RISCV_ISA_ZBA
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config RISCV_ISA_ZBB
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bool "Zbb extension support for bit manipulation instructions"
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depends on TOOLCHAIN_HAS_ZBB
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depends on RISCV_ALTERNATIVE
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default y
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help
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Adds support to dynamically detect the presence of the ZBB
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extension (basic bit manipulation) and enable its usage.
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Add support for enabling optimisations in the kernel when the
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Zbb extension is detected at boot. Some optimisations may
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additionally depend on toolchain support for Zbb.
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The Zbb extension provides instructions to accelerate a number
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of bit-specific operations (count bit population, sign extending,
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@ -791,9 +792,9 @@ config RISCV_ISA_ZICBOM
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select RISCV_DMA_NONCOHERENT
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select DMA_DIRECT_REMAP
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help
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Adds support to dynamically detect the presence of the ZICBOM
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extension (Cache Block Management Operations) and enable its
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usage.
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Add support for the Zicbom extension (Cache Block Management
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Operations) and enable its use in the kernel when it is detected
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at boot.
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The Zicbom extension can be used to handle for example
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non-coherent DMA support on devices that need it.
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@ -806,7 +807,7 @@ config RISCV_ISA_ZICBOZ
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default y
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help
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Enable the use of the Zicboz extension (cbo.zero instruction)
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when available.
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in the kernel when it is detected at boot.
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The Zicboz extension is used for faster zeroing of memory.
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@ -844,8 +845,9 @@ config FPU
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bool "FPU support"
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default y
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help
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Say N here if you want to disable all floating-point related procedure
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in the kernel.
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Add support for floating point operations when an FPU is detected at
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boot. When this option is disabled, neither the kernel nor userspace
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may use the floating point unit.
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If you don't know what to do here, say Y.
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@ -19,7 +19,7 @@
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static __always_inline unsigned int __arch_hweight32(unsigned int w)
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{
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#ifdef CONFIG_RISCV_ISA_ZBB
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#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)
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asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
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RISCV_ISA_EXT_ZBB, 1)
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: : : : legacy);
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@ -50,7 +50,7 @@ static inline unsigned int __arch_hweight8(unsigned int w)
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#if BITS_PER_LONG == 64
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static __always_inline unsigned long __arch_hweight64(__u64 w)
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{
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# ifdef CONFIG_RISCV_ISA_ZBB
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#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)
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asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0,
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RISCV_ISA_EXT_ZBB, 1)
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: : : : legacy);
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@ -64,7 +64,7 @@ static __always_inline unsigned long __arch_hweight64(__u64 w)
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return w;
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legacy:
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# endif
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#endif
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return __sw_hweight64(w);
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}
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#else /* BITS_PER_LONG == 64 */
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@ -15,7 +15,7 @@
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#include <asm/barrier.h>
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#include <asm/bitsperlong.h>
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#if !defined(CONFIG_RISCV_ISA_ZBB) || defined(NO_ALTERNATIVE)
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#if !(defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)) || defined(NO_ALTERNATIVE)
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#include <asm-generic/bitops/__ffs.h>
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#include <asm-generic/bitops/__fls.h>
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#include <asm-generic/bitops/ffs.h>
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@ -175,7 +175,7 @@ static __always_inline int variable_fls(unsigned int x)
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variable_fls(x_); \
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})
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#endif /* !defined(CONFIG_RISCV_ISA_ZBB) || defined(NO_ALTERNATIVE) */
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#endif /* !(defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)) || defined(NO_ALTERNATIVE) */
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#include <asm-generic/bitops/ffz.h>
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#include <asm-generic/bitops/fls64.h>
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@ -49,8 +49,7 @@ static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
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* ZBB only saves three instructions on 32-bit and five on 64-bit so not
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* worth checking if supported without Alternatives.
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*/
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if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&
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IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
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if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) {
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unsigned long fold_temp;
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asm goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0,
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@ -40,12 +40,7 @@ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
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uproto = (__force unsigned int)htonl(proto);
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sum += uproto;
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/*
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* Zbb support saves 4 instructions, so not worth checking without
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* alternatives if supported
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*/
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if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&
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IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
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if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) {
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unsigned long fold_temp;
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/*
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@ -157,12 +152,7 @@ do_csum_with_alignment(const unsigned char *buff, int len)
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csum = do_csum_common(ptr, end, data);
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#ifdef CC_HAS_ASM_GOTO_TIED_OUTPUT
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/*
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* Zbb support saves 6 instructions, so not worth checking without
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* alternatives if supported
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*/
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if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&
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IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
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if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) {
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unsigned long fold_temp;
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/*
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@ -244,12 +234,7 @@ do_csum_no_alignment(const unsigned char *buff, int len)
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end = (const unsigned long *)(buff + len);
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csum = do_csum_common(ptr, end, data);
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/*
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* Zbb support saves 6 instructions, so not worth checking without
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* alternatives if supported
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*/
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if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) &&
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IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
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if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB)) {
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unsigned long fold_temp;
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/*
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@ -8,7 +8,8 @@
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/* int strcmp(const char *cs, const char *ct) */
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SYM_FUNC_START(strcmp)
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ALTERNATIVE("nop", "j strcmp_zbb", 0, RISCV_ISA_EXT_ZBB, CONFIG_RISCV_ISA_ZBB)
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__ALTERNATIVE_CFG("nop", "j strcmp_zbb", 0, RISCV_ISA_EXT_ZBB,
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IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB))
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/*
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* Returns
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@ -43,7 +44,7 @@ SYM_FUNC_START(strcmp)
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* The code was published as part of the bitmanip manual
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* in Appendix A.
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*/
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#ifdef CONFIG_RISCV_ISA_ZBB
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#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)
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strcmp_zbb:
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.option push
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@ -8,7 +8,8 @@
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/* int strlen(const char *s) */
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SYM_FUNC_START(strlen)
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ALTERNATIVE("nop", "j strlen_zbb", 0, RISCV_ISA_EXT_ZBB, CONFIG_RISCV_ISA_ZBB)
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__ALTERNATIVE_CFG("nop", "j strlen_zbb", 0, RISCV_ISA_EXT_ZBB,
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IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB))
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/*
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* Returns
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@ -33,7 +34,7 @@ SYM_FUNC_START(strlen)
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/*
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* Variant of strlen using the ZBB extension if available
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*/
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#ifdef CONFIG_RISCV_ISA_ZBB
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#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)
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strlen_zbb:
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#ifdef CONFIG_CPU_BIG_ENDIAN
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@ -8,7 +8,8 @@
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/* int strncmp(const char *cs, const char *ct, size_t count) */
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SYM_FUNC_START(strncmp)
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ALTERNATIVE("nop", "j strncmp_zbb", 0, RISCV_ISA_EXT_ZBB, CONFIG_RISCV_ISA_ZBB)
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__ALTERNATIVE_CFG("nop", "j strncmp_zbb", 0, RISCV_ISA_EXT_ZBB,
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IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB))
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/*
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* Returns
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@ -46,7 +47,7 @@ SYM_FUNC_START(strncmp)
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/*
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* Variant of strncmp using the ZBB extension if available
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*/
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#ifdef CONFIG_RISCV_ISA_ZBB
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#if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB)
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strncmp_zbb:
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.option push
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