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arm64: dts: qcom: sm8650: Sort nodes by unit address
Qualcomm DTS uses sorting of MMIO nodes by the unit address, so move few nodes in SM8650 DTSI to fix that. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250727193652.4029-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Krzysztof Kozlowski
Bjorn Andersson
parent
1a67f85c69
commit
8def31f8c1
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@ -3490,6 +3490,11 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
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};
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};
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rng: rng@10c3000 {
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compatible = "qcom,sm8650-trng", "qcom,trng";
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reg = <0 0x010c3000 0 0x1000>;
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};
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cnoc_main: interconnect@1500000 {
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compatible = "qcom,sm8650-cnoc-main";
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reg = <0 0x01500000 0 0x14080>;
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@ -3561,11 +3566,6 @@ mmss_noc: interconnect@1780000 {
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#interconnect-cells = <2>;
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};
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rng: rng@10c3000 {
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compatible = "qcom,sm8650-trng", "qcom,trng";
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reg = <0 0x010c3000 0 0x1000>;
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};
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pcie0: pcie@1c00000 {
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device_type = "pci";
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compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550";
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@ -3926,38 +3926,6 @@ pcie1_phy: phy@1c0e000 {
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status = "disabled";
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};
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cryptobam: dma-controller@1dc4000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0 0x01dc4000 0 0x28000>;
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interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>;
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#dma-cells = <1>;
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iommus = <&apps_smmu 0x480 0>,
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<&apps_smmu 0x481 0>;
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qcom,ee = <0>;
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qcom,num-ees = <4>;
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num-channels = <20>;
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qcom,controlled-remotely;
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};
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crypto: crypto@1dfa000 {
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compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce";
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reg = <0 0x01dfa000 0 0x6000>;
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interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "memory";
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dmas = <&cryptobam 4>, <&cryptobam 5>;
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dma-names = "rx", "tx";
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iommus = <&apps_smmu 0x480 0>,
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<&apps_smmu 0x481 0>;
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};
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ufs_mem_phy: phy@1d80000 {
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compatible = "qcom,sm8650-qmp-ufs-phy";
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reg = <0 0x01d80000 0 0x2000>;
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@ -4079,6 +4047,38 @@ ice: crypto@1d88000 {
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clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
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};
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cryptobam: dma-controller@1dc4000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0 0x01dc4000 0 0x28000>;
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interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>;
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#dma-cells = <1>;
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iommus = <&apps_smmu 0x480 0>,
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<&apps_smmu 0x481 0>;
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qcom,ee = <0>;
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qcom,num-ees = <4>;
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num-channels = <20>;
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qcom,controlled-remotely;
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};
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crypto: crypto@1dfa000 {
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compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce";
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reg = <0 0x01dfa000 0 0x6000>;
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interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
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interconnect-names = "memory";
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dmas = <&cryptobam 4>, <&cryptobam 5>;
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dma-names = "rx", "tx";
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iommus = <&apps_smmu 0x480 0>,
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<&apps_smmu 0x481 0>;
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};
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tcsr_mutex: hwlock@1f40000 {
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compatible = "qcom,tcsr-mutex";
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reg = <0 0x01f40000 0 0x20000>;
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@ -4962,6 +4962,170 @@ opp-202000000 {
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};
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};
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usb_1_hsphy: phy@88e3000 {
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compatible = "qcom,sm8650-snps-eusb2-phy",
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"qcom,sm8550-snps-eusb2-phy";
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reg = <0 0x088e3000 0 0x154>;
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clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
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clock-names = "ref";
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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#phy-cells = <0>;
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status = "disabled";
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};
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usb_dp_qmpphy: phy@88e8000 {
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compatible = "qcom,sm8650-qmp-usb3-dp-phy";
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reg = <0 0x088e8000 0 0x3000>;
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clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
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clock-names = "aux",
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"ref",
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"com_aux",
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"usb3_pipe";
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resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
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<&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
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reset-names = "phy",
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"common";
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power-domains = <&gcc USB3_PHY_GDSC>;
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#clock-cells = <1>;
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#phy-cells = <1>;
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orientation-switch;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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usb_dp_qmpphy_out: endpoint {
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};
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};
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port@1 {
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reg = <1>;
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usb_dp_qmpphy_usb_ss_in: endpoint {
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remote-endpoint = <&usb_1_dwc3_ss>;
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};
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};
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port@2 {
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reg = <2>;
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usb_dp_qmpphy_dp_in: endpoint {
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remote-endpoint = <&mdss_dp0_out>;
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};
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};
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};
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};
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usb_1: usb@a600000 {
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compatible = "qcom,sm8650-dwc3", "qcom,snps-dwc3";
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reg = <0 0x0a600000 0 0xfc100>;
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interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>,
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<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
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<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
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<&pdc 14 IRQ_TYPE_EDGE_RISING>,
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<&pdc 15 IRQ_TYPE_EDGE_RISING>,
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<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "dwc_usb3",
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"pwr_event",
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"hs_phy_irq",
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"dp_hs_phy_irq",
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"dm_hs_phy_irq",
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"ss_phy_irq";
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clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&tcsr TCSR_USB3_CLKREF_EN>;
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clock-names = "cfg_noc",
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"core",
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"iface",
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"sleep",
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"mock_utmi",
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"xo";
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assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_MASTER_CLK>;
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assigned-clock-rates = <19200000>, <200000000>;
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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phys = <&usb_1_hsphy>,
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<&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
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phy-names = "usb2-phy",
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"usb3-phy";
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interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
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interconnect-names = "usb-ddr",
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"apps-usb";
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iommus = <&apps_smmu 0x40 0>;
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power-domains = <&gcc USB30_PRIM_GDSC>;
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required-opps = <&rpmhpd_opp_nom>;
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snps,hird-threshold = /bits/ 8 <0x0>;
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snps,usb2-gadget-lpm-disable;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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snps,is-utmi-l1-suspend;
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snps,usb3_lpm_capable;
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snps,usb2-lpm-disable;
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snps,has-lpm-erratum;
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tx-fifo-resize;
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dma-coherent;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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usb_1_dwc3_hs: endpoint {
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};
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};
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port@1 {
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reg = <1>;
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usb_1_dwc3_ss: endpoint {
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remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
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};
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};
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};
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};
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iris: video-codec@aa00000 {
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compatible = "qcom,sm8650-iris";
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reg = <0 0x0aa00000 0 0xf0000>;
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@ -5580,170 +5744,6 @@ dispcc: clock-controller@af00000 {
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#power-domain-cells = <1>;
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};
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usb_1_hsphy: phy@88e3000 {
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compatible = "qcom,sm8650-snps-eusb2-phy",
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"qcom,sm8550-snps-eusb2-phy";
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reg = <0 0x088e3000 0 0x154>;
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clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
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clock-names = "ref";
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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#phy-cells = <0>;
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status = "disabled";
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};
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usb_dp_qmpphy: phy@88e8000 {
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compatible = "qcom,sm8650-qmp-usb3-dp-phy";
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reg = <0 0x088e8000 0 0x3000>;
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clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
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clock-names = "aux",
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"ref",
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"com_aux",
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"usb3_pipe";
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resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
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<&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
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reset-names = "phy",
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"common";
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power-domains = <&gcc USB3_PHY_GDSC>;
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#clock-cells = <1>;
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#phy-cells = <1>;
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orientation-switch;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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usb_dp_qmpphy_out: endpoint {
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};
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};
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port@1 {
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reg = <1>;
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usb_dp_qmpphy_usb_ss_in: endpoint {
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remote-endpoint = <&usb_1_dwc3_ss>;
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};
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};
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port@2 {
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reg = <2>;
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usb_dp_qmpphy_dp_in: endpoint {
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remote-endpoint = <&mdss_dp0_out>;
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};
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};
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};
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};
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usb_1: usb@a600000 {
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compatible = "qcom,sm8650-dwc3", "qcom,snps-dwc3";
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reg = <0 0x0a600000 0 0xfc100>;
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interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>,
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<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>,
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<&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>,
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<&pdc 14 IRQ_TYPE_EDGE_RISING>,
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<&pdc 15 IRQ_TYPE_EDGE_RISING>,
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<&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "dwc_usb3",
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"pwr_event",
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"hs_phy_irq",
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"dp_hs_phy_irq",
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"dm_hs_phy_irq",
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"ss_phy_irq";
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clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&tcsr TCSR_USB3_CLKREF_EN>;
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clock-names = "cfg_noc",
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"core",
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"iface",
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"sleep",
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"mock_utmi",
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"xo";
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assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_MASTER_CLK>;
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assigned-clock-rates = <19200000>, <200000000>;
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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phys = <&usb_1_hsphy>,
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<&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
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phy-names = "usb2-phy",
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"usb3-phy";
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interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
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&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
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<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
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&config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
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interconnect-names = "usb-ddr",
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"apps-usb";
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iommus = <&apps_smmu 0x40 0>;
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power-domains = <&gcc USB30_PRIM_GDSC>;
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required-opps = <&rpmhpd_opp_nom>;
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snps,hird-threshold = /bits/ 8 <0x0>;
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snps,usb2-gadget-lpm-disable;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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snps,is-utmi-l1-suspend;
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snps,usb3_lpm_capable;
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snps,usb2-lpm-disable;
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snps,has-lpm-erratum;
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tx-fifo-resize;
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dma-coherent;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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usb_1_dwc3_hs: endpoint {
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};
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};
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port@1 {
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reg = <1>;
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usb_1_dwc3_ss: endpoint {
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remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>;
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};
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};
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};
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};
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pdc: interrupt-controller@b220000 {
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compatible = "qcom,sm8650-pdc", "qcom,pdc";
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reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
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