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drm/i915/de: Use intel_de_wait_ms() for the obvious cases
Replace some users of intel_de_wait_custom() with intel_de_wait_ms(). This includes the cases where we pass in the default 2 microsecond fast timeout, which is also what intel_de_wait_ms() uses so there are no functional changes here. Done with cocci (with manual formatting fixes): @@ expression display, reg, mask, value, timeout_ms, out_value; @@ - intel_de_wait_custom(display, reg, mask, value, 2, timeout_ms, out_value) + intel_de_wait_ms(display, reg, mask, value, timeout_ms, out_value) Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patch.msgid.link/20251110172756.2132-7-ville.syrjala@linux.intel.com Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com> Acked-by: Jani Nikula <jani.nikula@intel.com>
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45554c1c64
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8da977a2f2
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@ -164,11 +164,10 @@ int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
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enum port port = encoder->port;
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enum phy phy = intel_encoder_to_phy(encoder);
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if (intel_de_wait_custom(display,
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XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
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XELPDP_PORT_P2M_RESPONSE_READY,
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XELPDP_PORT_P2M_RESPONSE_READY,
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2, XELPDP_MSGBUS_TIMEOUT_MS, val)) {
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if (intel_de_wait_ms(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
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XELPDP_PORT_P2M_RESPONSE_READY,
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XELPDP_PORT_P2M_RESPONSE_READY,
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XELPDP_MSGBUS_TIMEOUT_MS, val)) {
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drm_dbg_kms(display->drm,
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"PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
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phy_name(phy), *val);
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@ -2827,9 +2826,9 @@ void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
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intel_cx0_get_powerdown_update(lane_mask));
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/* Update Timeout Value */
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if (intel_de_wait_custom(display, buf_ctl2_reg,
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intel_cx0_get_powerdown_update(lane_mask), 0,
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2, XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS, NULL))
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if (intel_de_wait_ms(display, buf_ctl2_reg,
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intel_cx0_get_powerdown_update(lane_mask), 0,
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XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS, NULL))
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drm_warn(display->drm,
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"PHY %c failed to bring out of lane reset\n",
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phy_name(phy));
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@ -62,9 +62,9 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp)
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u32 status;
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int ret;
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ret = intel_de_wait_custom(display, ch_ctl, DP_AUX_CH_CTL_SEND_BUSY,
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0,
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2, timeout_ms, &status);
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ret = intel_de_wait_ms(display, ch_ctl,
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DP_AUX_CH_CTL_SEND_BUSY, 0,
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timeout_ms, &status);
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if (ret == -ETIMEDOUT)
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drm_err(display->drm,
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@ -410,9 +410,8 @@ static int intel_hdcp_load_keys(struct intel_display *display)
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}
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/* Wait for the keys to load (500us) */
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ret = intel_de_wait_custom(display, HDCP_KEY_STATUS,
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HDCP_KEY_LOAD_DONE, HDCP_KEY_LOAD_DONE,
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2, 1, &val);
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ret = intel_de_wait_ms(display, HDCP_KEY_STATUS, HDCP_KEY_LOAD_DONE,
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HDCP_KEY_LOAD_DONE, 1, &val);
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if (ret)
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return ret;
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else if (!(val & HDCP_KEY_LOAD_STATUS))
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@ -1201,10 +1201,9 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
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XELPDP_LANE_PCLK_PLL_REQUEST(0),
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XELPDP_LANE_PCLK_PLL_REQUEST(0));
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if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
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XELPDP_LANE_PCLK_PLL_ACK(0),
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XELPDP_LANE_PCLK_PLL_ACK(0),
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2, XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
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if (intel_de_wait_ms(display, XELPDP_PORT_CLOCK_CTL(display, port),
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XELPDP_LANE_PCLK_PLL_ACK(0), XELPDP_LANE_PCLK_PLL_ACK(0),
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XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
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drm_warn(display->drm, "PHY %c PLL MacCLK assertion ack not done\n",
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phy_name(phy));
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@ -1215,15 +1214,15 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
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intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
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lane_pipe_reset | lane_phy_pulse_status, 0);
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if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
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lane_phy_current_status, 0,
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2, XE3PLPD_RESET_END_LATENCY_MS, NULL))
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if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
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lane_phy_current_status, 0,
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XE3PLPD_RESET_END_LATENCY_MS, NULL))
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drm_warn(display->drm, "PHY %c failed to bring out of lane reset\n",
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phy_name(phy));
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if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
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lane_phy_pulse_status, lane_phy_pulse_status,
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2, XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
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if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
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lane_phy_pulse_status, lane_phy_pulse_status,
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XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
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drm_warn(display->drm, "PHY %c PLL rate not changed\n",
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phy_name(phy));
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@ -2002,10 +2001,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
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XELPDP_LANE_PCLK_PLL_REQUEST(0));
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/* 12. Poll for PORT_CLOCK_CTL[PCLK PLL Ack LN0]= 1. */
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if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
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XELPDP_LANE_PCLK_PLL_ACK(0),
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XELPDP_LANE_PCLK_PLL_ACK(0),
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2, XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
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if (intel_de_wait_ms(display, XELPDP_PORT_CLOCK_CTL(display, port),
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XELPDP_LANE_PCLK_PLL_ACK(0), XELPDP_LANE_PCLK_PLL_ACK(0),
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XE3PLPD_MACCLK_TURNON_LATENCY_MS, NULL))
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drm_warn(display->drm, "PHY %c PLL MacCLK ack assertion timeout\n",
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phy_name(phy));
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@ -2031,9 +2029,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
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rate_update, MB_WRITE_COMMITTED);
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/* 16. Poll for PORT_BUF_CTL2 register PHY Pulse Status = 1 for Owned PHY Lanes. */
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if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
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lane_phy_pulse_status, lane_phy_pulse_status,
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2, XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
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if (intel_de_wait_ms(display, XELPDP_PORT_BUF_CTL2(display, port),
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lane_phy_pulse_status, lane_phy_pulse_status,
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XE3PLPD_RATE_CALIB_DONE_LATENCY_MS, NULL))
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drm_warn(display->drm, "PHY %c PLL rate not changed\n",
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phy_name(phy));
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@ -462,9 +462,9 @@ static void intel_pmdemand_poll(struct intel_display *display)
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u32 status;
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int ret;
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ret = intel_de_wait_custom(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
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XELPDP_PMDEMAND_REQ_ENABLE, 0,
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2, timeout_ms, &status);
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ret = intel_de_wait_ms(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1),
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XELPDP_PMDEMAND_REQ_ENABLE, 0,
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timeout_ms, &status);
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if (ret == -ETIMEDOUT)
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drm_err(display->drm,
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