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i.MX arm64 device tree changes for 5.16:

Browse Source 
- New board support: LX2160A based BlueBox3, S32G2 EVB and RDB2 boards.
 - Quite some updates on imx8mq-librem5 board: delay the startup of the
   SDIO, add power sequencing for M.2 cards, add wifi regulator, add
   panel reset GPIO, fix led_r and led_g pinctrl, etc.
 - Fix the SPI chipselect polarity for a couple of i.MX8MM boards.
 - Add GPU nodes for i.MX8MM 2D and 3D core.
 - Add VPU and DISP blk-ctrl devices for i.MX8MM.
 - A series from Michael Walle to LS1028A device trees and add GPU
   support.
 - Random and small updates on various boards.
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Merge tag 'imx-dt64-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX arm64 device tree changes for 5.16:

- New board support: LX2160A based BlueBox3, S32G2 EVB and RDB2 boards.
- Quite some updates on imx8mq-librem5 board: delay the startup of the
  SDIO, add power sequencing for M.2 cards, add wifi regulator, add
  panel reset GPIO, fix led_r and led_g pinctrl, etc.
- Fix the SPI chipselect polarity for a couple of i.MX8MM boards.
- Add GPU nodes for i.MX8MM 2D and 3D core.
- Add VPU and DISP blk-ctrl devices for i.MX8MM.
- A series from Michael Walle to LS1028A device trees and add GPU
  support.
- Random and small updates on various boards.

* tag 'imx-dt64-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (37 commits)
  arm64: dts: imx8mm-kontron: Add support for ultra high speed modes on SD card
  arm64: dts: imx8mm-venice-gw7901.dts: disable pgc_gpumix
  arm64: dts: imx8mq-librem5: set debounce interval of volume buttons to 50ms
  arm64: dts: imx8mq-librem5: Limit the max sdio frequency
  arm64: dts: imx8mq-librem5: add power sequencing for M.2 cards
  arm64: dts: imx8mq-librem5: delay the startup of the SDIO
  arm64: dts: imx8mq-librem5: wire up the wifi regulator
  arm64: dts: imx8mq-librem5: Fix led_r and led_g pinctrl assignments
  arm64: dts: imx8mq-librem5: add reset gpio to mantix panel description
  arm64: dts: imx8mm-kontron: Fix reset delays for ethernet PHY
  arm64: dts: imx8mm: add DISP blk-ctrl
  arm64: dts: imx8mm: add VPU blk-ctrl
  arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core
  arm64: dts: imx8mm: put USB controllers into power-domains
  arm64: dts: imx8mm: add GPC node
  arm64: dts: ls1028a: mark internal links between Felix and ENETC as capable of flow control
  arm64: dts: freescale: Fix 'interrupt-map' parent address cells
  arm64: dts: ls1028a: use phy-mode instead of phy-connection-type
  arm64: dts: ls1028a: move PHY nodes to MDIO controller
  arm64: dts: ls1028a: disable usb controller by default
  ...

Link: https://lore.kernel.org/r/20211016140138.1603-4-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2021-10-20 15:19:15 +02:00
commit 8d2214d3a6
29 changed files with 1374 additions and 190 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/freescale/Makefile
View File

@ -25,6 +25,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-bluebox3.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-bluebox3-rev-a.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
@ -70,4 +72,6 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb
dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb
dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb

1
arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
View File

@ -15,6 +15,7 @@ / {
compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
aliases {
serial0 = &duart0;
mmc0 = &esdhc0;
mmc1 = &esdhc1;
};

60
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts
View File

@ -8,7 +8,7 @@
* None of the four SerDes lanes are used by the module, instead they are
* all led out to the carrier for customer use.
*
* Copyright (C) 2020 Michael Walle <michael@walle.cc>
* Copyright (C) 2021 Michael Walle <michael@walle.cc>
*
*/
@ -21,43 +21,39 @@ / {
compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
};
&enetc_mdio_pf3 {
/* Delete unused phy node */
/delete-node/ ethernet-phy@5;
phy0: ethernet-phy@4 {
reg = <0x4>;
eee-broken-1000t;
eee-broken-100tx;
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
qca,keep-pll-enabled;
vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-name = "VDDIO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddh: vddh-regulator {
regulator-name = "VDDH";
};
};
};
&enetc_port0 {
status = "disabled";
/*
* Delete both the phy-handle to the old phy0 label as well as
* the mdio node with the old phy node with the old phy0 label.
*/
/* Delete the phy-handle to the old phy0 label */
/delete-property/ phy-handle;
/delete-node/ mdio;
};
&enetc_port1 {
phy-handle = <&phy0>;
phy-connection-type = "rgmii-id";
phy-mode = "rgmii-id";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@4 {
reg = <0x4>;
eee-broken-1000t;
eee-broken-100tx;
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
qca,keep-pll-enabled;
vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-name = "VDDIO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddh: vddh-regulator {
regulator-name = "VDDH";
};
};
};
};

17
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts
View File

@ -5,7 +5,7 @@
* This is for the network variant 2 which has two ethernet ports. These
* ports are connected to the internal switch.
*
* Copyright (C) 2020 Michael Walle <michael@walle.cc>
* Copyright (C) 2021 Michael Walle <michael@walle.cc>
*
*/
@ -18,12 +18,6 @@ / {
};
&enetc_mdio_pf3 {
phy0: ethernet-phy@5 {
reg = <0x5>;
eee-broken-1000t;
eee-broken-100tx;
};
phy1: ethernet-phy@4 {
reg = <0x4>;
eee-broken-1000t;
@ -34,14 +28,11 @@ phy1: ethernet-phy@4 {
&enetc_port0 {
status = "disabled";
/*
* In the base device tree the PHY was registered in the mdio
* subnode as it is PHY for this port. On this module this PHY
* is connected to a switch port instead and registered above.
* Therefore, delete the mdio subnode as well as the phy-handle
* property here.
* In the base device tree the PHY at address 5 was assigned for
* this port. On this module this PHY is connected to a switch
* port instead. Therefore, delete the phy-handle property here.
*/
/delete-property/ phy-handle;
/delete-node/ mdio;
};
&enetc_port2 {

49
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts
View File

@ -5,7 +5,7 @@
* This is for the network variant 4 which has two ethernet ports. It
* extends the base and provides one more port connected via RGMII.
*
* Copyright (C) 2019 Michael Walle <michael@walle.cc>
* Copyright (C) 2021 Michael Walle <michael@walle.cc>
*
*/
@ -18,33 +18,30 @@ / {
compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a";
};
&enetc_port1 {
phy-handle = <&phy1>;
phy-connection-type = "rgmii-id";
status = "okay";
&enetc_mdio_pf3 {
phy1: ethernet-phy@4 {
reg = <0x4>;
eee-broken-1000t;
eee-broken-100tx;
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
qca,keep-pll-enabled;
vddio-supply = <&vddio>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
vddio: vddio-regulator {
regulator-name = "VDDIO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
phy1: ethernet-phy@4 {
reg = <0x4>;
eee-broken-1000t;
eee-broken-100tx;
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
qca,keep-pll-enabled;
vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-name = "VDDIO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddh: vddh-regulator {
regulator-name = "VDDH";
};
vddh: vddh-regulator {
regulator-name = "VDDH";
};
};
};
&enetc_port1 {
phy-handle = <&phy1>;
phy-mode = "rgmii-id";
status = "okay";
};

31
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts
View File

@ -2,7 +2,7 @@
/*
* Device Tree file for the Kontron SMARC-sAL28 board.
*
* Copyright (C) 2019 Michael Walle <michael@walle.cc>
* Copyright (C) 2021 Michael Walle <michael@walle.cc>
*
*/
@ -80,22 +80,19 @@ &duart1 {
status = "okay";
};
&enetc_mdio_pf3 {
phy0: ethernet-phy@5 {
reg = <0x5>;
eee-broken-1000t;
eee-broken-100tx;
};
};
&enetc_port0 {
phy-handle = <&phy0>;
phy-connection-type = "sgmii";
phy-mode = "sgmii";
managed = "in-band-status";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@5 {
reg = <0x5>;
eee-broken-1000t;
eee-broken-100tx;
};
};
};
&esdhc {
@ -309,3 +306,11 @@ eeprom@50 {
&lpuart1 {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};

10
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
View File

@ -320,7 +320,7 @@ mux: mux-controller {
&enetc_port1 {
phy-handle = <&qds_phy1>;
phy-connection-type = "rgmii-id";
phy-mode = "rgmii-id";
status = "okay";
};
@ -335,3 +335,11 @@ &sai1 {
&sata {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};

19
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
View File

@ -197,6 +197,10 @@ &duart1 {
};
&enetc_mdio_pf3 {
sgmii_phy0: ethernet-phy@2 {
reg = <0x2>;
};
/* VSC8514 QSGMII quad PHY */
qsgmii_phy0: ethernet-phy@10 {
reg = <0x10>;
@ -217,17 +221,9 @@ qsgmii_phy3: ethernet-phy@13 {
&enetc_port0 {
phy-handle = <&sgmii_phy0>;
phy-connection-type = "sgmii";
phy-mode = "sgmii";
managed = "in-band-status";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
sgmii_phy0: ethernet-phy@2 {
reg = <0x2>;
};
};
};
&enetc_port2 {
@ -287,6 +283,11 @@ &sata {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
dr_mode = "otg";
status = "okay";
};

72
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
View File

@ -80,13 +80,6 @@ osc_27m: clock-osc-27m {
clock-output-names = "phy_27m";
};
dpclk: clock-controller@f1f0000 {
compatible = "fsl,ls1028a-plldig";
reg = <0x0 0xf1f0000 0x0 0xffff>;
#clock-cells = <0>;
clocks = <&osc_27m>;
};
firmware {
optee: optee {
compatible = "linaro,optee-tz";
@ -592,6 +585,7 @@ usb0: usb@3100000 {
snps,dis_rxdet_inp3_quirk;
snps,quirk-frame-length-adjustment = <0x20>;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";
};
usb1: usb@3110000 {
@ -602,6 +596,7 @@ usb1: usb@3110000 {
snps,dis_rxdet_inp3_quirk;
snps,quirk-frame-length-adjustment = <0x20>;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
status = "disabled";
};
sata: sata@3200000 {
@ -800,6 +795,38 @@ QORIQ_CLK_PLL_DIV(16)>,
clock-names = "wdog_clk", "apb_pclk";
};
malidp0: display@f080000 {
compatible = "arm,mali-dp500";
reg = <0x0 0xf080000 0x0 0x10000>;
interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
<0 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "DE", "SE";
clocks = <&dpclk>,
<&clockgen QORIQ_CLK_HWACCEL 2>,
<&clockgen QORIQ_CLK_HWACCEL 2>,
<&clockgen QORIQ_CLK_HWACCEL 2>;
clock-names = "pxlclk", "mclk", "aclk", "pclk";
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
arm,malidp-arqos-value = <0xd000d000>;
port {
dpi0_out: endpoint {
};
};
};
gpu: gpu@f0c0000 {
compatible = "vivante,gc";
reg = <0x0 0xf0c0000 0x0 0x10000>;
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_HWACCEL 2>,
<&clockgen QORIQ_CLK_HWACCEL 2>,
<&clockgen QORIQ_CLK_HWACCEL 2>;
clock-names = "core", "shader", "bus";
#cooling-cells = <2>;
};
sai1: audio-controller@f100000 {
#sound-dai-cells = <0>;
compatible = "fsl,vf610-sai";
@ -926,6 +953,13 @@ QORIQ_CLK_PLL_DIV(2)>,
status = "disabled";
};
dpclk: clock-controller@f1f0000 {
compatible = "fsl,ls1028a-plldig";
reg = <0x0 0xf1f0000 0x0 0x10000>;
#clock-cells = <0>;
clocks = <&osc_27m>;
};
tmu: tmu@1f80000 {
compatible = "fsl,qoriq-tmu";
reg = <0x0 0x1f80000 0x0 0x10000>;
@ -1025,6 +1059,7 @@ enetc_port2: ethernet@0,2 {
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
@ -1083,6 +1118,7 @@ mscc_felix_port4: port@4 {
fixed-link {
speed = <2500>;
full-duplex;
pause;
};
};
@ -1094,6 +1130,7 @@ mscc_felix_port5: port@5 {
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
};
@ -1108,6 +1145,7 @@ enetc_port3: ethernet@0,6 {
fixed-link {
speed = <1000>;
full-duplex;
pause;
};
};
@ -1139,24 +1177,4 @@ ftm_alarm0: timer@2800000 {
};
};
malidp0: display@f080000 {
compatible = "arm,mali-dp500";
reg = <0x0 0xf080000 0x0 0x10000>;
interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
<0 223 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "DE", "SE";
clocks = <&dpclk>,
<&clockgen QORIQ_CLK_HWACCEL 2>,
<&clockgen QORIQ_CLK_HWACCEL 2>,
<&clockgen QORIQ_CLK_HWACCEL 2>;
clock-names = "pxlclk", "mclk", "aclk", "pclk";
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
arm,malidp-arqos-value = <0xd000d000>;
port {
dp0_out: endpoint {
};
};
};
};

40
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
View File

@ -241,18 +241,18 @@ extirq: interrupt-controller@14 {
interrupt-controller;
reg = <0x14 4>;
interrupt-map =
<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
<0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<1 0 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<2 0 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<3 0 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<4 0 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<5 0 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<6 0 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<7 0 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<8 0 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<9 0 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<10 0 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<11 0 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0xffffffff 0x0>;
};
};
@ -847,7 +847,7 @@ pcs7_3: ethernet-phy@3 {
};
cluster1_core0_watchdog: wdt@c000000 {
compatible = "arm,sp805-wdt", "arm,primecell";
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>,
@ -857,7 +857,7 @@ QORIQ_CLK_PLL_DIV(16)>,
};
cluster1_core1_watchdog: wdt@c010000 {
compatible = "arm,sp805-wdt", "arm,primecell";
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc010000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>,
@ -867,7 +867,7 @@ QORIQ_CLK_PLL_DIV(16)>,
};
cluster1_core2_watchdog: wdt@c020000 {
compatible = "arm,sp805-wdt", "arm,primecell";
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc020000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>,
@ -877,7 +877,7 @@ QORIQ_CLK_PLL_DIV(16)>,
};
cluster1_core3_watchdog: wdt@c030000 {
compatible = "arm,sp805-wdt", "arm,primecell";
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc030000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>,
@ -887,7 +887,7 @@ QORIQ_CLK_PLL_DIV(16)>,
};
cluster2_core0_watchdog: wdt@c100000 {
compatible = "arm,sp805-wdt", "arm,primecell";
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc100000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>,
@ -897,7 +897,7 @@ QORIQ_CLK_PLL_DIV(16)>,
};
cluster2_core1_watchdog: wdt@c110000 {
compatible = "arm,sp805-wdt", "arm,primecell";
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc110000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>,
@ -907,7 +907,7 @@ QORIQ_CLK_PLL_DIV(16)>,
};
cluster2_core2_watchdog: wdt@c120000 {
compatible = "arm,sp805-wdt", "arm,primecell";
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc120000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>,
@ -917,7 +917,7 @@ QORIQ_CLK_PLL_DIV(16)>,
};
cluster2_core3_watchdog: wdt@c130000 {
compatible = "arm,sp805-wdt", "arm,primecell";
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc130000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>,

40
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
View File

@ -293,18 +293,18 @@ extirq: interrupt-controller@14 {
interrupt-controller;
reg = <0x14 4>;
interrupt-map =
<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
<0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<1 0 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<2 0 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<3 0 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<4 0 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<5 0 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<6 0 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<7 0 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<8 0 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<9 0 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<10 0 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<11 0 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0xffffffff 0x0>;
};
};
@ -387,7 +387,7 @@ serial3: serial@21d0600 {
};
cluster1_core0_watchdog: wdt@c000000 {
compatible = "arm,sp805-wdt", "arm,primecell";
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc000000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>,
@ -397,7 +397,7 @@ QORIQ_CLK_PLL_DIV(4)>,
};
cluster1_core1_watchdog: wdt@c010000 {
compatible = "arm,sp805-wdt", "arm,primecell";
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc010000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>,
@ -407,7 +407,7 @@ QORIQ_CLK_PLL_DIV(4)>,
};
cluster2_core0_watchdog: wdt@c100000 {
compatible = "arm,sp805-wdt", "arm,primecell";
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc100000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>,
@ -417,7 +417,7 @@ QORIQ_CLK_PLL_DIV(4)>,
};
cluster2_core1_watchdog: wdt@c110000 {
compatible = "arm,sp805-wdt", "arm,primecell";
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc110000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>,
@ -427,7 +427,7 @@ QORIQ_CLK_PLL_DIV(4)>,
};
cluster3_core0_watchdog: wdt@c200000 {
compatible = "arm,sp805-wdt", "arm,primecell";
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc200000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>,
@ -437,7 +437,7 @@ QORIQ_CLK_PLL_DIV(4)>,
};
cluster3_core1_watchdog: wdt@c210000 {
compatible = "arm,sp805-wdt", "arm,primecell";
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc210000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>,
@ -447,7 +447,7 @@ QORIQ_CLK_PLL_DIV(4)>,
};
cluster4_core0_watchdog: wdt@c300000 {
compatible = "arm,sp805-wdt", "arm,primecell";
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc300000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>,
@ -457,7 +457,7 @@ QORIQ_CLK_PLL_DIV(4)>,
};
cluster4_core1_watchdog: wdt@c310000 {
compatible = "arm,sp805-wdt", "arm,primecell";
compatible = "arm,sp805", "arm,primecell";
reg = <0x0 0xc310000 0x0 0x1000>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>,

34
arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3-rev-a.dts Normal file
View File

@ -0,0 +1,34 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2160A BLUEBOX3
//
// Copyright 2020-2021 NXP
/dts-v1/;
#include "fsl-lx2160a-bluebox3.dts"
/ {
compatible = "fsl,lx2160a-bluebox3-rev-a", "fsl,lx2160a";
};
/* The RGMII PHYs have a different MDIO address */
&emdio1 {
/delete-node/ ethernet-phy@5;
sw1_mii3_phy: ethernet-phy@1 {
/* AR8035 */
compatible = "ethernet-phy-id004d.d072";
reg = <0x1>;
interrupts-extended = <&extirq 6 IRQ_TYPE_LEVEL_LOW>;
};
/delete-node/ ethernet-phy@6;
sw2_mii3_phy: ethernet-phy@2 {
/* AR8035 */
compatible = "ethernet-phy-id004d.d072";
reg = <0x2>;
interrupts-extended = <&extirq 7 IRQ_TYPE_LEVEL_LOW>;
};
};

658
arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts Normal file
View File

@ -0,0 +1,658 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2160A BLUEBOX3
//
// Copyright 2020-2021 NXP
/dts-v1/;
#include "fsl-lx2160a.dtsi"
/ {
model = "NXP Layerscape LX2160ABLUEBOX3";
compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
aliases {
crypto = &crypto;
mmc0 = &esdhc0;
mmc1 = &esdhc1;
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
sb_3v3: regulator-sb3v3 {
compatible = "regulator-fixed";
regulator-name = "MC34717-3.3VSB";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&can0 {
status = "okay";
can-transceiver {
max-bitrate = <5000000>;
};
};
&can1 {
status = "okay";
can-transceiver {
max-bitrate = <5000000>;
};
};
&crypto {
status = "okay";
};
&dpmac5 {
phy-handle = <&aqr113c_phy1>;
phy-mode = "usxgmii";
managed = "in-band-status";
};
&dpmac6 {
phy-handle = <&aqr113c_phy2>;
phy-mode = "usxgmii";
managed = "in-band-status";
};
&dpmac9 {
phy-handle = <&aqr113c_phy3>;
phy-mode = "usxgmii";
managed = "in-band-status";
};
&dpmac10 {
phy-handle = <&aqr113c_phy4>;
phy-mode = "usxgmii";
managed = "in-band-status";
};
&dpmac17 {
phy-mode = "rgmii";
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&dpmac18 {
phy-mode = "rgmii";
status = "okay";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&emdio1 {
status = "okay";
aqr113c_phy2: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
/* IRQ_10G_PHY2 */
interrupts-extended = <&extirq 3 IRQ_TYPE_LEVEL_LOW>;
};
aqr113c_phy1: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x8>;
/* IRQ_10G_PHY1 */
interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
};
sw1_mii3_phy: ethernet-phy@5 {
/* AR8035 */
compatible = "ethernet-phy-id004d.d072";
reg = <0x5>;
interrupts-extended = <&extirq 6 IRQ_TYPE_LEVEL_LOW>;
};
sw2_mii3_phy: ethernet-phy@6 {
/* AR8035 */
compatible = "ethernet-phy-id004d.d072";
reg = <0x6>;
interrupts-extended = <&extirq 7 IRQ_TYPE_LEVEL_LOW>;
};
};
&emdio2 {
status = "okay";
aqr113c_phy4: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
/* IRQ_10G_PHY4 */
interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>;
};
aqr113c_phy3: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x8>;
/* IRQ_10G_PHY3 */
interrupts-extended = <&extirq 4 IRQ_TYPE_LEVEL_LOW>;
};
};
&esdhc0 {
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
sd-uhs-sdr12;
status = "okay";
};
&esdhc1 {
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
status = "okay";
};
&fspi {
status = "okay";
mt35xu512aba0: flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <0>;
m25p,fast-read;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <8>;
spi-tx-bus-width = <8>;
};
mt35xu512aba1: flash@1 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
reg = <1>;
m25p,fast-read;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <8>;
spi-tx-bus-width = <8>;
};
};
&i2c0 {
status = "okay";
i2c-mux@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
power-monitor@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <500>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
temp2: temperature-sensor@48 {
compatible = "nxp,sa56004";
reg = <0x48>;
vcc-supply = <&sb_3v3>;
#thermal-sensor-cells = <1>;
};
temp1: temperature-sensor@4c {
compatible = "nxp,sa56004";
reg = <0x4c>;
vcc-supply = <&sb_3v3>;
#thermal-sensor-cells = <1>;
};
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x4>;
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
interrupts-extended = <&extirq 11 IRQ_TYPE_LEVEL_LOW>;
};
};
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7>;
i2c-mux@75 {
compatible = "nxp,pca9547";
reg = <0x75>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
spi_bridge: spi@28 {
compatible = "nxp,sc18is602b";
reg = <0x28>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
};
};
};
&i2c5 {
status = "okay";
i2c-mux@77 {
compatible = "nxp,pca9846";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
/* The I2C multiplexer and temperature sensors are on
* the T6 riser card.
*/
i2c-mux@70 {
compatible = "nxp,pca9548";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
i2c@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x6>;
q12: temperature-sensor@4c {
compatible = "nxp,sa56004";
reg = <0x4c>;
vcc-supply = <&sb_3v3>;
#thermal-sensor-cells = <1>;
};
};
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x7>;
q11: temperature-sensor@4c {
compatible = "nxp,sa56004";
reg = <0x4c>;
vcc-supply = <&sb_3v3>;
#thermal-sensor-cells = <1>;
};
q13: temperature-sensor@48 {
compatible = "nxp,sa56004";
reg = <0x48>;
vcc-supply = <&sb_3v3>;
#thermal-sensor-cells = <1>;
};
q14: temperature-sensor@4a {
compatible = "nxp,sa56004";
reg = <0x4a>;
vcc-supply = <&sb_3v3>;
#thermal-sensor-cells = <1>;
};
};
};
};
};
};
&pcs_mdio5 {
status = "okay";
};
&pcs_mdio6 {
status = "okay";
};
&pcs_mdio9 {
status = "okay";
};
&pcs_mdio10 {
status = "okay";
};
&spi_bridge {
sw1: ethernet-switch@0 {
compatible = "nxp,sja1110a";
reg = <0>;
spi-max-frequency = <4000000>;
spi-cpol;
dsa,member = <0 0>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
/* Microcontroller port */
port@0 {
reg = <0>;
status = "disabled";
};
/* SW1_P1 */
port@1 {
reg = <1>;
label = "con_2x20";
phy-mode = "sgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@2 {
reg = <2>;
ethernet = <&dpmac17>;
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@3 {
reg = <3>;
label = "1ge_p1";
phy-mode = "rgmii-id";
phy-handle = <&sw1_mii3_phy>;
};
sw1p4: port@4 {
reg = <4>;
link = <&sw2p1>;
phy-mode = "sgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@5 {
reg = <5>;
label = "trx1";
phy-mode = "internal";
phy-handle = <&sw1_port5_base_t1_phy>;
};
port@6 {
reg = <6>;
label = "trx2";
phy-mode = "internal";
phy-handle = <&sw1_port6_base_t1_phy>;
};
port@7 {
reg = <7>;
label = "trx3";
phy-mode = "internal";
phy-handle = <&sw1_port7_base_t1_phy>;
};
port@8 {
reg = <8>;
label = "trx4";
phy-mode = "internal";
phy-handle = <&sw1_port8_base_t1_phy>;
};
port@9 {
reg = <9>;
label = "trx5";
phy-mode = "internal";
phy-handle = <&sw1_port9_base_t1_phy>;
};
port@a {
reg = <10>;
label = "trx6";
phy-mode = "internal";
phy-handle = <&sw1_port10_base_t1_phy>;
};
};
mdios {
#address-cells = <1>;
#size-cells = <0>;
mdio@0 {
compatible = "nxp,sja1110-base-t1-mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
sw1_port5_base_t1_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
sw1_port6_base_t1_phy: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x2>;
};
sw1_port7_base_t1_phy: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x3>;
};
sw1_port8_base_t1_phy: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x4>;
};
sw1_port9_base_t1_phy: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x5>;
};
sw1_port10_base_t1_phy: ethernet-phy@6 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x6>;
};
};
};
};
sw2: ethernet-switch@2 {
compatible = "nxp,sja1110a";
reg = <2>;
spi-max-frequency = <4000000>;
spi-cpol;
dsa,member = <0 1>;
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
/* Microcontroller port */
port@0 {
reg = <0>;
status = "disabled";
};
sw2p1: port@1 {
reg = <1>;
link = <&sw1p4>;
phy-mode = "sgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@2 {
reg = <2>;
ethernet = <&dpmac18>;
phy-mode = "rgmii-id";
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@3 {
reg = <3>;
label = "1ge_p2";
phy-mode = "rgmii-id";
phy-handle = <&sw2_mii3_phy>;
};
port@4 {
reg = <4>;
label = "to_sw3";
phy-mode = "2500base-x";
fixed-link {
speed = <2500>;
full-duplex;
};
};
port@5 {
reg = <5>;
label = "trx7";
phy-mode = "internal";
phy-handle = <&sw2_port5_base_t1_phy>;
};
port@6 {
reg = <6>;
label = "trx8";
phy-mode = "internal";
phy-handle = <&sw2_port6_base_t1_phy>;
};
port@7 {
reg = <7>;
label = "trx9";
phy-mode = "internal";
phy-handle = <&sw2_port7_base_t1_phy>;
};
port@8 {
reg = <8>;
label = "trx10";
phy-mode = "internal";
phy-handle = <&sw2_port8_base_t1_phy>;
};
port@9 {
reg = <9>;
label = "trx11";
phy-mode = "internal";
phy-handle = <&sw2_port9_base_t1_phy>;
};
port@a {
reg = <10>;
label = "trx12";
phy-mode = "internal";
phy-handle = <&sw2_port10_base_t1_phy>;
};
};
mdios {
#address-cells = <1>;
#size-cells = <0>;
mdio@0 {
compatible = "nxp,sja1110-base-t1-mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
sw2_port5_base_t1_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
sw2_port6_base_t1_phy: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x2>;
};
sw2_port7_base_t1_phy: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x3>;
};
sw2_port8_base_t1_phy: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x4>;
};
sw2_port9_base_t1_phy: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x5>;
};
sw2_port10_base_t1_phy: ethernet-phy@6 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x6>;
};
};
};
};
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};

24
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View File

@ -680,18 +680,18 @@ extirq: interrupt-controller@14 {
interrupt-controller;
reg = <0x14 4>;
interrupt-map =
<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
<0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<1 0 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<2 0 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<3 0 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<4 0 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<5 0 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<6 0 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<7 0 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<8 0 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<9 0 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<10 0 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<11 0 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0xffffffff 0x0>;
};
};

32
arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts
View File

@ -121,8 +121,8 @@ mdio {
ethphy: ethernet-phy@0 {
reg = <0>;
reset-assert-us = <100>;
reset-deassert-us = <100>;
reset-assert-us = <1>;
reset-deassert-us = <15000>;
reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
};
};
@ -189,8 +189,10 @@ usbnet: usbether@1 {
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
vmmc-supply = <&reg_vdd_3v3>;
vqmmc-supply = <&reg_nvcc_sd>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
@ -319,4 +321,28 @@ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
>;
};
};

4
arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi
View File

@ -63,7 +63,7 @@ opp-750M {
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
spi-flash@0 {
@ -86,6 +86,7 @@ pca9450: pmic@25 {
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
regulators {
reg_vdd_soc: BUCK1 {
@ -225,6 +226,7 @@ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x141
>;
};

2
arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi
View File

@ -57,7 +57,7 @@ reg_usb_otg1_vbus: regulator-usb-otg1 {
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
View File

@ -76,7 +76,7 @@ reg_usb_otg2_vbus: regulator-usb-otg2 {
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
};

2
arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
View File

@ -96,7 +96,7 @@ reg_wifi_en: regulator-wifi-en {
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
};

24
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
View File

@ -255,6 +255,10 @@ opp-750M {
};
};
&disp_blk_ctrl {
status = "disabled";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
@ -282,6 +286,14 @@ fixed-link {
};
};
&gpu_2d {
status = "disabled";
};
&gpu_3d {
status = "disabled";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
@ -632,6 +644,18 @@ &i2c4 {
status = "okay";
};
&pgc_gpu {
status = "disabled";
};
&pgc_gpumix {
status = "disabled";
};
&pgc_mipi {
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;

180
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@ -7,6 +7,8 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/imx8mm-power.h>
#include <dt-bindings/reset/imx8mq-reset.h>
#include <dt-bindings/thermal/thermal.h>
#include "imx8mm-pinfunc.h"
@ -610,6 +612,111 @@ src: reset-controller@30390000 {
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
gpc: gpc@303a0000 {
compatible = "fsl,imx8mm-gpc";
reg = <0x303a0000 0x10000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupt-controller;
#interrupt-cells = <3>;
pgc {
#address-cells = <1>;
#size-cells = <0>;
pgc_hsiomix: power-domain@0 {
#power-domain-cells = <0>;
reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
clocks = <&clk IMX8MM_CLK_USB_BUS>;
assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
};
pgc_pcie: power-domain@1 {
#power-domain-cells = <0>;
reg = <IMX8MM_POWER_DOMAIN_PCIE>;
power-domains = <&pgc_hsiomix>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
};
pgc_otg1: power-domain@2 {
#power-domain-cells = <0>;
reg = <IMX8MM_POWER_DOMAIN_OTG1>;
power-domains = <&pgc_hsiomix>;
};
pgc_otg2: power-domain@3 {
#power-domain-cells = <0>;
reg = <IMX8MM_POWER_DOMAIN_OTG2>;
power-domains = <&pgc_hsiomix>;
};
pgc_gpumix: power-domain@4 {
#power-domain-cells = <0>;
reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
<&clk IMX8MM_CLK_GPU_AHB>;
assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>,
<&clk IMX8MM_CLK_GPU_AHB>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
<&clk IMX8MM_SYS_PLL1_800M>;
assigned-clock-rates = <800000000>, <400000000>;
};
pgc_gpu: power-domain@5 {
#power-domain-cells = <0>;
reg = <IMX8MM_POWER_DOMAIN_GPU>;
clocks = <&clk IMX8MM_CLK_GPU_AHB>,
<&clk IMX8MM_CLK_GPU_BUS_ROOT>,
<&clk IMX8MM_CLK_GPU2D_ROOT>,
<&clk IMX8MM_CLK_GPU3D_ROOT>;
resets = <&src IMX8MQ_RESET_GPU_RESET>;
power-domains = <&pgc_gpumix>;
};
pgc_vpumix: power-domain@6 {
#power-domain-cells = <0>;
reg = <IMX8MM_POWER_DOMAIN_VPUMIX>;
clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
resets = <&src IMX8MQ_RESET_VPU_RESET>;
};
pgc_vpu_g1: power-domain@7 {
#power-domain-cells = <0>;
reg = <IMX8MM_POWER_DOMAIN_VPUG1>;
};
pgc_vpu_g2: power-domain@8 {
#power-domain-cells = <0>;
reg = <IMX8MM_POWER_DOMAIN_VPUG2>;
};
pgc_vpu_h1: power-domain@9 {
#power-domain-cells = <0>;
reg = <IMX8MM_POWER_DOMAIN_VPUH1>;
};
pgc_dispmix: power-domain@10 {
#power-domain-cells = <0>;
reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
<&clk IMX8MM_CLK_DISP_AXI_ROOT>;
assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>,
<&clk IMX8MM_CLK_DISP_APB>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
<&clk IMX8MM_SYS_PLL1_800M>;
assigned-clock-rates = <500000000>, <200000000>;
};
pgc_mipi: power-domain@11 {
#power-domain-cells = <0>;
reg = <IMX8MM_POWER_DOMAIN_MIPI>;
};
};
};
};
aips2: bus@30400000 {
@ -961,6 +1068,33 @@ aips4: bus@32c00000 {
#size-cells = <1>;
ranges = <0x32c00000 0x32c00000 0x400000>;
disp_blk_ctrl: blk-ctrl@32e28000 {
compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
reg = <0x32e28000 0x100>;
power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
<&pgc_dispmix>, <&pgc_mipi>,
<&pgc_mipi>;
power-domain-names = "bus", "csi-bridge",
"lcdif", "mipi-dsi",
"mipi-csi";
clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
<&clk IMX8MM_CLK_DISP_APB_ROOT>,
<&clk IMX8MM_CLK_CSI1_ROOT>,
<&clk IMX8MM_CLK_DISP_AXI_ROOT>,
<&clk IMX8MM_CLK_DISP_APB_ROOT>,
<&clk IMX8MM_CLK_DISP_ROOT>,
<&clk IMX8MM_CLK_DSI_CORE>,
<&clk IMX8MM_CLK_DSI_PHY_REF>,
<&clk IMX8MM_CLK_CSI1_CORE>,
<&clk IMX8MM_CLK_CSI1_PHY_REF>;
clock-names = "csi-bridge-axi","csi-bridge-apb",
"csi-bridge-core", "lcdif-axi",
"lcdif-apb", "lcdif-pix",
"dsi-pclk", "dsi-ref",
"csi-aclk", "csi-pclk";
#power-domain-cells = <1>;
};
usbotg1: usb@32e40000 {
compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
reg = <0x32e40000 0x200>;
@ -971,6 +1105,7 @@ usbotg1: usb@32e40000 {
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
phys = <&usbphynop1>;
fsl,usbmisc = <&usbmisc1 0>;
power-domains = <&pgc_otg1>;
status = "disabled";
};
@ -990,6 +1125,7 @@ usbotg2: usb@32e50000 {
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
phys = <&usbphynop2>;
fsl,usbmisc = <&usbmisc2 0>;
power-domains = <&pgc_otg2>;
status = "disabled";
};
@ -1030,6 +1166,50 @@ gpmi: nand-controller@33002000{
status = "disabled";
};
gpu_3d: gpu@38000000 {
compatible = "vivante,gc";
reg = <0x38000000 0x8000>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_GPU_AHB>,
<&clk IMX8MM_CLK_GPU_BUS_ROOT>,
<&clk IMX8MM_CLK_GPU3D_ROOT>,
<&clk IMX8MM_CLK_GPU3D_ROOT>;
clock-names = "reg", "bus", "core", "shader";
assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
<&clk IMX8MM_GPU_PLL_OUT>;
assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
assigned-clock-rates = <0>, <1000000000>;
power-domains = <&pgc_gpu>;
};
gpu_2d: gpu@38008000 {
compatible = "vivante,gc";
reg = <0x38008000 0x8000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MM_CLK_GPU_AHB>,
<&clk IMX8MM_CLK_GPU_BUS_ROOT>,
<&clk IMX8MM_CLK_GPU2D_ROOT>;
clock-names = "reg", "bus", "core";
assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
<&clk IMX8MM_GPU_PLL_OUT>;
assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
assigned-clock-rates = <0>, <1000000000>;
power-domains = <&pgc_gpu>;
};
vpu_blk_ctrl: blk-ctrl@38330000 {
compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
reg = <0x38330000 0x100>;
power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
<&pgc_vpu_g2>, <&pgc_vpu_h1>;
power-domain-names = "bus", "g1", "g2", "h1";
clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
<&clk IMX8MM_CLK_VPU_G2_ROOT>,
<&clk IMX8MM_CLK_VPU_H1_ROOT>;
clock-names = "g1", "g2", "h1";
#power-domain-cells = <1>;
};
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>, /* GIC Dist */

2
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -785,7 +785,7 @@ flexspi: spi@30bb0000 {
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
<&clk IMX8MP_CLK_QSPI_ROOT>;
clock-names = "fspi", "fspi_en";
clock-names = "fspi_en", "fspi";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
#address-cells = <1>;

46
arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi
View File

@ -40,12 +40,14 @@ vol-down {
label = "VOL_DOWN";
gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
debounce-interval = <50>;
};
vol-up {
label = "VOL_UP";
gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
debounce-interval = <50>;
};
};
@ -138,9 +140,14 @@ reg_vsys_3v4: regulator-vsys-3v4 {
reg_wifi_3v3: regulator-wifi-3v3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_pwr>;
regulator-name = "3V3_WIFI";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio3 10 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_vdd_3v3>;
};
sound {
@ -193,6 +200,14 @@ simple-audio-card,codec {
};
};
usdhc2_pwrseq: pwrseq {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bt>, <&pinctrl_wifi_disable>;
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>,
<&gpio4 29 GPIO_ACTIVE_HIGH>;
};
bm818_codec: sound-wwan-codec {
compatible = "broadmobi,bm818", "option,gtm601";
#sound-dai-cells = <0>;
@ -225,7 +240,7 @@ &A53_3 {
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: ddrc-opp-table {
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
@ -307,6 +322,13 @@ MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x83
>;
};
pinctrl_bt: btgrp {
fsl,pins = <
/* BT_REG_ON */
MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x83
>;
};
pinctrl_charger_in: chargeringrp {
fsl,pins = <
/* CHRG_INT */
@ -638,6 +660,20 @@ MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0xc1
>;
};
pinctrl_wifi_disable: wifidisablegrp {
fsl,pins = <
/* WIFI_REG_ON */
MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x83
>;
};
pinctrl_wifi_pwr: wifipwrgrp {
fsl,pins = <
/* WIFI3V3_EN */
MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x83
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
/* nWDOG */
@ -1010,6 +1046,7 @@ lcd_panel: panel@0 {
vddi-supply = <&reg_lcd_1v8>;
backlight = <&backlight_dsi>;
reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
mantix,tp-rstn-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
port {
panel_in: endpoint {
@ -1055,13 +1092,13 @@ &pwm2 {
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led_g>;
pinctrl-0 = <&pinctrl_led_r>;
status = "okay";
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led_r>;
pinctrl-0 = <&pinctrl_led_g>;
status = "okay";
};
@ -1199,7 +1236,10 @@ &usdhc2 {
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
bus-width = <4>;
vmmc-supply = <&reg_wifi_3v3>;
mmc-pwrseq = <&usdhc2_pwrseq>;
post-power-on-delay-ms = <1000>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
max-frequency = <50000000>;
disable-wp;
cap-sdio-irq;
keep-power-in-suspend;

1
arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
View File

@ -202,6 +202,7 @@ MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3

2
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
View File

@ -555,6 +555,7 @@ &pcie0 {
<&clk IMX8MQ_CLK_PCIE1_PHY>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
vph-supply = <&vgen5_reg>;
status = "okay";
};
@ -567,6 +568,7 @@ &pcie1 {
<&clk IMX8MQ_CLK_PCIE2_PHY>,
<&pcie1_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
vph-supply = <&vgen5_reg>;
status = "okay";
};

10
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@ -1467,10 +1467,9 @@ pcie0: pcie@33800000 {
#size-cells = <2>;
device_type = "pci";
bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
<0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
@ -1505,10 +1504,9 @@ pcie1: pcie@33c00000 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */
<0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
num-lanes = <1>;
num-viewport = <4>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* NXP S32G2 SoC family
*
* Copyright (c) 2021 SUSE LLC
* Copyright (c) 2017-2021 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "nxp,s32g2";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
};
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x100>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
};
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x101>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
};
cluster0_l2: l2-cache0 {
compatible = "cache";
};
cluster1_l2: l2-cache1 {
compatible = "cache";
};
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
firmware {
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0x80000000>;
uart0: serial@401c8000 {
compatible = "nxp,s32g2-linflexuart",
"fsl,s32v234-linflexuart";
reg = <0x401c8000 0x3000>;
interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
uart1: serial@401cc000 {
compatible = "nxp,s32g2-linflexuart",
"fsl,s32v234-linflexuart";
reg = <0x401cc000 0x3000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
uart2: serial@402bc000 {
compatible = "nxp,s32g2-linflexuart",
"fsl,s32v234-linflexuart";
reg = <0x402bc000 0x3000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
gic: interrupt-controller@50800000 {
compatible = "arm,gic-v3";
reg = <0x50800000 0x10000>,
<0x50880000 0x80000>,
<0x50400000 0x2000>,
<0x50410000 0x2000>,
<0x50420000 0x2000>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
};
};
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2021 SUSE LLC
* Copyright (c) 2019-2021 NXP
*/
/dts-v1/;
#include "s32g2.dtsi"
/ {
model = "NXP S32G2 Evaluation Board (S32G-VNP-EVB)";
compatible = "nxp,s32g274a-evb", "nxp,s32g2";
aliases {
serial0 = &uart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
/* 4GiB RAM */
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0 0x80000000>,
<0x8 0x80000000 0 0x80000000>;
};
};
/* UART (J58) to Micro USB port */
&uart0 {
status = "okay";
};

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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2021 SUSE LLC
* Copyright (c) 2019-2021 NXP
*/
/dts-v1/;
#include "s32g2.dtsi"
/ {
model = "NXP S32G2 Reference Design Board 2 (S32G-VNP-RDB2)";
compatible = "nxp,s32g274a-rdb2", "nxp,s32g2";
aliases {
serial0 = &uart0;
serial1 = &uart1;
};
chosen {
stdout-path = "serial0:115200n8";
};
/* 4GiB RAM */
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0 0x80000000>,
<0x8 0x80000000 0 0x80000000>;
};
};
/* UART (J2) to Micro USB port */
&uart0 {
status = "okay";
};
/* UART (J1) to Micro USB port */
&uart1 {
status = "okay";
};