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clk: mediatek: clk-gate: Refactor mtk_clk_register_gate to use mtk_gate struct

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MT8196 uses a HW voter for gate enable/disable control, with
set/clr/sta registers located in a separate regmap. Refactor
mtk_clk_register_gate() to take a struct mtk_gate, and add a pointer to
it in struct mtk_clk_gate. This allows reuse of the static gate data
(including HW voter register offsets) without adding extra function
arguments, and removes redundant duplication in the runtime data struct.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Laura Nao 2025-09-15 17:19:26 +02:00 committed by Stephen Boyd
parent be89999259
commit 8ceff24a75
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GPG Key ID: AD028897C6E49525
1 changed files with 19 additions and 33 deletions
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52
drivers/clk/mediatek/clk-gate.c
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@ -17,10 +17,7 @@
struct mtk_clk_gate { struct mtk_clk_gate {
struct clk_hw hw; struct clk_hw hw;
struct regmap *regmap; struct regmap *regmap;
int set_ofs; const struct mtk_gate *gate;
int clr_ofs;
int sta_ofs;
u8 bit;
}; };
static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw) static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw)
@ -33,9 +30,9 @@ static u32 mtk_get_clockgating(struct clk_hw *hw)
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
u32 val; u32 val;
regmap_read(cg->regmap, cg->sta_ofs, &val); regmap_read(cg->regmap, cg->gate->regs->sta_ofs, &val);
return val & BIT(cg->bit); return val & BIT(cg->gate->shift);
} }
static int mtk_cg_bit_is_cleared(struct clk_hw *hw) static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
@ -52,28 +49,30 @@ static void mtk_cg_set_bit(struct clk_hw *hw)
{ {
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit)); regmap_write(cg->regmap, cg->gate->regs->set_ofs, BIT(cg->gate->shift));
} }
static void mtk_cg_clr_bit(struct clk_hw *hw) static void mtk_cg_clr_bit(struct clk_hw *hw)
{ {
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit)); regmap_write(cg->regmap, cg->gate->regs->clr_ofs, BIT(cg->gate->shift));
} }
static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw) static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
{ {
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
regmap_set_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit)); regmap_set_bits(cg->regmap, cg->gate->regs->sta_ofs,
BIT(cg->gate->shift));
} }
static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw) static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
{ {
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
regmap_clear_bits(cg->regmap, cg->sta_ofs, BIT(cg->bit)); regmap_clear_bits(cg->regmap, cg->gate->regs->sta_ofs,
BIT(cg->gate->shift));
} }
static int mtk_cg_enable(struct clk_hw *hw) static int mtk_cg_enable(struct clk_hw *hw)
@ -152,12 +151,9 @@ const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = {
}; };
EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv); EXPORT_SYMBOL_GPL(mtk_clk_gate_ops_no_setclr_inv);
static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name, static struct clk_hw *mtk_clk_register_gate(struct device *dev,
const char *parent_name, const struct mtk_gate *gate,
struct regmap *regmap, int set_ofs, struct regmap *regmap)
int clr_ofs, int sta_ofs, u8 bit,
const struct clk_ops *ops,
unsigned long flags)
{ {
struct mtk_clk_gate *cg; struct mtk_clk_gate *cg;
int ret; int ret;
@ -167,18 +163,14 @@ static struct clk_hw *mtk_clk_register_gate(struct device *dev, const char *name
if (!cg) if (!cg)
return ERR_PTR(-ENOMEM); return ERR_PTR(-ENOMEM);
init.name = name; init.name = gate->name;
init.flags = flags | CLK_SET_RATE_PARENT; init.flags = gate->flags | CLK_SET_RATE_PARENT;
init.parent_names = parent_name ? &parent_name : NULL; init.parent_names = gate->parent_name ? &gate->parent_name : NULL;
init.num_parents = parent_name ? 1 : 0; init.num_parents = gate->parent_name ? 1 : 0;
init.ops = ops; init.ops = gate->ops;
cg->regmap = regmap; cg->regmap = regmap;
cg->set_ofs = set_ofs; cg->gate = gate;
cg->clr_ofs = clr_ofs;
cg->sta_ofs = sta_ofs;
cg->bit = bit;
cg->hw.init = &init; cg->hw.init = &init;
ret = clk_hw_register(dev, &cg->hw); ret = clk_hw_register(dev, &cg->hw);
@ -228,13 +220,7 @@ int mtk_clk_register_gates(struct device *dev, struct device_node *node,
continue; continue;
} }
hw = mtk_clk_register_gate(dev, gate->name, gate->parent_name, hw = mtk_clk_register_gate(dev, gate, regmap);
regmap,
gate->regs->set_ofs,
gate->regs->clr_ofs,
gate->regs->sta_ofs,
gate->shift, gate->ops,
gate->flags);
if (IS_ERR(hw)) { if (IS_ERR(hw)) {
pr_err("Failed to register clk %s: %pe\n", gate->name, pr_err("Failed to register clk %s: %pe\n", gate->name,