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Renesas DTS updates for v6.13 (take two)

Browse Source 
- Add a CPU Operating Performance Points table for the RZ/V2H SoC,
   - Add Battery Backup Function (VBATTB) and RTC support for the RZ/G3S
     SoC and the RZ/G3S SMARC SoM,
   - Add DMAC support for MMC on the RZ/A1H SoC and the Genmai
     development board,
   - Miscellaneous fixes and improvements.
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Merge tag 'renesas-dts-for-v6.13-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v6.13 (take two)

  - Add a CPU Operating Performance Points table for the RZ/V2H SoC,
  - Add Battery Backup Function (VBATTB) and RTC support for the RZ/G3S
    SoC and the RZ/G3S SMARC SoM,
  - Add DMAC support for MMC on the RZ/A1H SoC and the Genmai
    development board,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v6.13-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: rzg3s-smarc-som: Enable RTC
  arm64: dts: renesas: rzg3s-smarc-som: Enable VBATTB
  arm64: dts: renesas: r9a08g045: Add RTC node
  arm64: dts: renesas: r9a08g045: Add VBATTB node
  arm64: dts: renesas: white-hawk-cpu-common: Add pin control for DSI-eDP IRQ
  ARM: dts: renesas: r7s72100: Add DMA support to MMCIF
  ARM: dts: renesas: r7s72100: Add DMAC node
  arm64: dts: renesas: hihope: Drop #sound-dai-cells
  dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
  dt-bindings: clock: r9a08g045-cpg: Add power domain ID for RTC
  arm64: dts: renesas: r9a09g057: Add OPP table

Link: https://lore.kernel.org/r/cover.1730726155.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2024-11-12 22:42:35 +01:00
commit 8cd0d9b997
10 changed files with 230 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

84
Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml Normal file
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@ -0,0 +1,84 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas Battery Backup Function (VBATTB)
description:
Renesas VBATTB is an always on powered module (backed by battery) which
controls the RTC clock (VBATTCLK), tamper detection logic and a small
general usage memory (128B).
maintainers:
- Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
properties:
compatible:
const: renesas,r9a08g045-vbattb
reg:
maxItems: 1
interrupts:
items:
- description: tamper detector interrupt
clocks:
items:
- description: VBATTB module clock
- description: RTC input clock (crystal or external clock device)
clock-names:
items:
- const: bclk
- const: rtx
'#clock-cells':
const: 1
power-domains:
maxItems: 1
resets:
items:
- description: VBATTB module reset
quartz-load-femtofarads:
description: load capacitance of the on board crystal
enum: [ 4000, 7000, 9000, 12500 ]
default: 4000
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- '#clock-cells'
- power-domains
- resets
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/r9a08g045-cpg.h>
#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
clock-controller@1005c000 {
compatible = "renesas,r9a08g045-vbattb";
reg = <0x1005c000 0x1000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
clock-names = "bclk", "rtx";
assigned-clocks = <&vbattb VBATTB_MUX>;
assigned-clock-parents = <&vbattb VBATTB_XC>;
#clock-cells = <1>;
power-domains = <&cpg>;
resets = <&cpg R9A08G045_VBAT_BRESETN>;
quartz-load-femtofarads = <12500>;
};

33
arch/arm/boot/dts/renesas/r7s72100.dtsi
View File

@ -332,6 +332,8 @@ mmcif: mmc@e804c800 {
<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
dmas = <&dmac 0x2cc9>, <&dmac 0x2cca>;
dma-names = "tx", "rx";
power-domains = <&cpg_clocks>;
status = "disabled";
};
@ -368,6 +370,37 @@ sdhi1: mmc@e804e800 {
status = "disabled";
};
dmac: dma-controller@e8200000 {
compatible = "renesas,r7s72100-dmac",
"renesas,rz-dmac";
reg = <0xe8200000 0x1000>,
<0xfcfe1000 0x20>;
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 9 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 13 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 14 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 15 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 16 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 17 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 18 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 23 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 24 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "error",
"ch0", "ch1", "ch2", "ch3",
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15";
#dma-cells = <1>;
dma-channels = <16>;
};
gic: interrupt-controller@e8201000 {
compatible = "arm,pl390";
#interrupt-cells = <3>;

3
arch/arm64/boot/dts/renesas/hihope-rev2.dtsi
View File

@ -69,9 +69,6 @@ &rcar_sound {
status = "okay";
/* Single DAI */
#sound-dai-cells = <0>;
rsnd_port: port {
rsnd_endpoint: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;

3
arch/arm64/boot/dts/renesas/hihope-rev4.dtsi
View File

@ -84,9 +84,6 @@ &rcar_sound {
pinctrl-names = "default";
status = "okay";
/* Single DAI */
#sound-dai-cells = <0>;
/* audio_clkout0/1/2/3 */
#clock-cells = <1>;
clock-frequency = <12288000 11289600>;

34
arch/arm64/boot/dts/renesas/r9a08g045.dtsi
View File

@ -7,6 +7,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a08g045-cpg.h>
#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
/ {
compatible = "renesas,r9a08g045";
@ -72,6 +73,32 @@ scif0: serial@1004b800 {
status = "disabled";
};
rtc: rtc@1004ec00 {
compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3";
reg = <0 0x1004ec00 0 0x400>;
interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "alarm", "period", "carry";
clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>;
clock-names = "bus", "counter";
power-domains = <&cpg>;
resets = <&cpg R9A08G045_VBAT_BRESETN>;
status = "disabled";
};
vbattb: clock-controller@1005c000 {
compatible = "renesas,r9a08g045-vbattb";
reg = <0 0x1005c000 0 0x1000>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;
clock-names = "bclk", "rtx";
#clock-cells = <1>;
power-domains = <&cpg>;
resets = <&cpg R9A08G045_VBAT_BRESETN>;
status = "disabled";
};
i2c0: i2c@10090000 {
compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
reg = <0 0x10090000 0 0x400>;
@ -425,4 +452,11 @@ timer {
interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
"hyp-virt";
};
vbattb_xtal: vbattb-xtal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
};
};

41
arch/arm64/boot/dts/renesas/r9a09g057.dtsi
View File

@ -20,6 +20,39 @@ audio_extal_clk: audio-clk {
clock-frequency = <0>;
};
/*
* The default cluster table is based on the assumption that the PLLCA55 clock
* frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
* 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be
* clocked to 1.8GHz as well). The table below should be overridden in the board
* DTS based on the PLLCA55 clock frequency.
*/
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <900000>;
clock-latency-ns = <300000>;
};
opp-850000000 {
opp-hz = /bits/ 64 <850000000>;
opp-microvolt = <800000>;
clock-latency-ns = <300000>;
};
opp-425000000 {
opp-hz = /bits/ 64 <425000000>;
opp-microvolt = <800000>;
clock-latency-ns = <300000>;
};
opp-212500000 {
opp-hz = /bits/ 64 <212500000>;
opp-microvolt = <800000>;
clock-latency-ns = <300000>;
opp-suspend;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -30,6 +63,8 @@ cpu0: cpu@0 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>;
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@100 {
@ -38,6 +73,8 @@ cpu1: cpu@100 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>;
operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@200 {
@ -46,6 +83,8 @@ cpu2: cpu@200 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>;
operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu@300 {
@ -54,6 +93,8 @@ cpu3: cpu@300 {
device_type = "cpu";
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>;
operating-points-v2 = <&cluster0_opp>;
};
L3_CA55: cache-controller-0 {

16
arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
View File

@ -5,6 +5,7 @@
* Copyright (C) 2023 Renesas Electronics Corp.
*/
#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
@ -344,6 +345,21 @@ mux {
};
};
&rtc {
status = "okay";
};
&vbattb {
assigned-clocks = <&vbattb VBATTB_MUX>;
assigned-clock-parents = <&vbattb VBATTB_XC>;
quartz-load-femtofarads = <12500>;
status = "okay";
};
&vbattb_xtal {
clock-frequency = <32768>;
};
&wdt0 {
timeout-sec = <60>;
status = "okay";

8
arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi
View File

@ -238,6 +238,9 @@ &i2c1 {
clock-frequency = <400000>;
bridge@2c {
pinctrl-0 = <&irq0_pins>;
pinctrl-names = "default";
compatible = "ti,sn65dsi86";
reg = <0x2c>;
@ -341,6 +344,11 @@ i2c1_pins: i2c1 {
function = "i2c1";
};
irq0_pins: irq0 {
groups = "intc_ex_irq0_a";
function = "intc_ex";
};
keys_pins: keys {
pins = "GP_5_0", "GP_5_1", "GP_5_2";
bias-pull-up;

1
include/dt-bindings/clock/r9a08g045-cpg.h
View File

@ -308,5 +308,6 @@
#define R9A08G045_PD_DDR 64
#define R9A08G045_PD_TZCDDR 65
#define R9A08G045_PD_OTFDE_DDR 66
#define R9A08G045_PD_RTC 67
#endif /* __DT_BINDINGS_CLOCK_R9A08G045_CPG_H__ */

13
include/dt-bindings/clock/renesas,r9a08g045-vbattb.h Normal file
View File

@ -0,0 +1,13 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
*
* Copyright (C) 2024 Renesas Electronics Corp.
*/
#ifndef __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__
#define __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__
#define VBATTB_XC 0
#define VBATTB_XBYP 1
#define VBATTB_MUX 2
#define VBATTB_VBATTCLK 3
#endif /* __DT_BINDINGS_CLOCK_R9A08G045_VBATTB_H__ */