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ARM: dts: sunxi: Use constants for RTC clock indexes

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The binding header provides descriptive names for the RTC clock indexes,
since the indexes were arbitrarily chosen by the binding, not by the
hardware. Let's use the names, so the meaning is clearer.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220607012438.18183-1-samuel@sholland.org
This commit is contained in:
Samuel Holland 2022-06-06 20:24:37 -05:00 committed by Jernej Skrabec
parent 4f05f03e8f
commit 8cce5702b6
13 changed files with 43 additions and 32 deletions
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12
arch/arm/boot/dts/sun6i-a31.dtsi
View File

@ -46,6 +46,7 @@
#include <dt-bindings/thermal/thermal.h>
#include <dt-bindings/clock/sun6i-a31-ccu.h>
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/reset/sun6i-a31-ccu.h>
/ {
@ -598,7 +599,7 @@ ohci2: usb@1c1c400 {
ccu: clock@1c20000 {
compatible = "allwinner,sun6i-a31-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&rtc 0>;
clocks = <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
@ -612,7 +613,8 @@ pio: pinctrl@1c20800 {
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_APB1_PIO>, <&osc24M>, <&rtc 0>;
clocks = <&ccu CLK_APB1_PIO>, <&osc24M>,
<&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
@ -1319,7 +1321,7 @@ prcm@1f01400 {
ar100: ar100_clk {
compatible = "allwinner,sun6i-a31-ar100-clk";
#clock-cells = <0>;
clocks = <&rtc 0>, <&osc24M>,
clocks = <&rtc CLK_OSC32K>, <&osc24M>,
<&ccu CLK_PLL_PERIPH>,
<&ccu CLK_PLL_PERIPH>;
clock-output-names = "ar100";
@ -1354,7 +1356,7 @@ apb0_gates: apb0_gates_clk {
ir_clk: ir_clk {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
clocks = <&rtc 0>, <&osc24M>;
clocks = <&rtc CLK_OSC32K>, <&osc24M>;
clock-output-names = "ir";
};
@ -1385,7 +1387,7 @@ r_pio: pinctrl@1f02c00 {
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
resets = <&apb0_rst 0>;
gpio-controller;

8
arch/arm/boot/dts/sun8i-a23-a33.dtsi
View File

@ -44,6 +44,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
@ -329,7 +330,7 @@ ohci0: usb@1c1a400 {
ccu: clock@1c20000 {
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&rtc 0>;
clocks = <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
@ -340,7 +341,8 @@ pio: pinctrl@1c20800 {
reg = <0x01c20800 0x400>;
interrupt-parent = <&r_intc>;
/* interrupts get set in SoC specific dtsi file */
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
<&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
@ -810,7 +812,7 @@ r_pio: pinctrl@1f02c00 {
reg = <0x01f02c00 0x400>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
clocks = <&apb0_gates 0>, <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
resets = <&apb0_rst 0>;
gpio-controller;

4
arch/arm/boot/dts/sun8i-h2-plus-bananapi-m2-zero.dts
View File

@ -106,7 +106,7 @@ poweroff {
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
};
@ -181,7 +181,7 @@ &uart1 {
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <1500000>;
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_vcc3v3>;
vddio-supply = <&reg_vcc3v3>;

2
arch/arm/boot/dts/sun8i-h3-beelink-x2.dts
View File

@ -125,7 +125,7 @@ spdif_out: spdif-out {
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
};

4
arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts
View File

@ -90,7 +90,7 @@ reg_vdd_sys: vdd-sys {
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
@ -151,7 +151,7 @@ &uart2 {
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_vcc3v3>;
vddio-supply = <&reg_vcc3v3>;

2
arch/arm/boot/dts/sun8i-h3-nanopi-neo-air.dts
View File

@ -127,7 +127,7 @@ &uart3 {
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_vcc3v3>;
vddio-supply = <&reg_vcc3v3>;

4
arch/arm/boot/dts/sun8i-h3-nanopi-r1.dts
View File

@ -46,7 +46,7 @@ reg_vdd_cpux: gpio-regulator {
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
@ -147,7 +147,7 @@ &uart3 {
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_vcc3v3>;
vddio-supply = <&reg_vcc3v3>;

4
arch/arm/boot/dts/sun8i-r16-bananapi-m2m.dts
View File

@ -91,7 +91,7 @@ reg_vcc5v0: vcc5v0 {
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
};
@ -283,7 +283,7 @@ &uart1 {
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_dldo1>;
vddio-supply = <&reg_aldo3>;

8
arch/arm/boot/dts/sun8i-r40.dtsi
View File

@ -42,6 +42,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-r40-ccu.h>
#include <dt-bindings/clock/sun8i-tcon-top.h>
@ -485,7 +486,7 @@ spi3: spi@1c1f000 {
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-r40-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&rtc 0>;
clocks = <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
@ -504,7 +505,8 @@ pio: pinctrl@1c20800 {
compatible = "allwinner,sun8i-r40-pinctrl";
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
<&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
interrupt-controller;
@ -1231,7 +1233,7 @@ hdmi: hdmi@1ee0000 {
reg-io-width = <1>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>,
<&ccu CLK_HDMI>, <&rtc 0>;
<&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
clock-names = "iahb", "isfr", "tmds", "cec";
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";

6
arch/arm/boot/dts/sun8i-v3s.dtsi
View File

@ -42,6 +42,7 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/clock/sun8i-v3s-ccu.h>
#include <dt-bindings/reset/sun8i-v3s-ccu.h>
#include <dt-bindings/clock/sun8i-de2.h>
@ -321,7 +322,7 @@ usbphy: phy@1c19400 {
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-v3s-ccu";
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&rtc 0>;
clocks = <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
@ -342,7 +343,8 @@ pio: pinctrl@1c20800 {
reg = <0x01c20800 0x400>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
<&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;

4
arch/arm/boot/dts/sunxi-bananapi-m2-plus.dtsi
View File

@ -101,7 +101,7 @@ reg_gmac_3v3: gmac-3v3 {
wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
};
@ -221,7 +221,7 @@ &uart1 {
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <1500000>;
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_vcc3v3>;
vddio-supply = <&reg_vcc3v3>;

4
arch/arm/boot/dts/sunxi-h3-h5-emlid-neutis.dtsi
View File

@ -22,7 +22,7 @@ wifi_pwrseq: wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */
post-power-on-delay-ms = <200>;
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "ext_clock";
};
};
@ -124,7 +124,7 @@ &uart1 {
bluetooth {
compatible = "brcm,bcm43438-bt";
clocks = <&rtc 1>;
clocks = <&rtc CLK_OSC32K_FANOUT>;
clock-names = "lpo";
vbat-supply = <&reg_vcc3v3>;
vddio-supply = <&reg_vcc3v3>;

13
arch/arm/boot/dts/sunxi-h3-h5.dtsi
View File

@ -40,6 +40,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/clock/sun6i-rtc.h>
#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-h3-ccu.h>
#include <dt-bindings/clock/sun8i-r-ccu.h>
@ -386,7 +387,7 @@ ohci3: usb@1c1d400 {
ccu: clock@1c20000 {
/* compatible is in per SoC .dtsi file */
reg = <0x01c20000 0x400>;
clocks = <&osc24M>, <&rtc 0>;
clocks = <&osc24M>, <&rtc CLK_OSC32K>;
clock-names = "hosc", "losc";
#clock-cells = <1>;
#reset-cells = <1>;
@ -398,7 +399,8 @@ pio: pinctrl@1c20800 {
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
<&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;
@ -818,7 +820,7 @@ hdmi: hdmi@1ee0000 {
reg-io-width = <1>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
<&ccu CLK_HDMI>, <&rtc 0>;
<&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
clock-names = "iahb", "isfr", "tmds", "cec";
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
@ -878,7 +880,7 @@ r_intc: interrupt-controller@1f00c00 {
r_ccu: clock@1f01400 {
compatible = "allwinner,sun8i-h3-r-ccu";
reg = <0x01f01400 0x100>;
clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
<&ccu CLK_PLL_PERIPH0>;
clock-names = "hosc", "losc", "iosc", "pll-periph";
#clock-cells = <1>;
@ -931,7 +933,8 @@ r_pio: pinctrl@1f02c00 {
reg = <0x01f02c00 0x400>;
interrupt-parent = <&r_intc>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>;
clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
<&rtc CLK_OSC32K>;
clock-names = "apb", "hosc", "losc";
gpio-controller;
#gpio-cells = <3>;