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drm/amdgpu/vcn2: read back register after written

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The addition of register read-back in VCN v2.0 is intended to prevent
potential race conditions.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
David (Ming Qiang) Wu 2025-05-14 18:52:13 -04:00 committed by Alex Deucher
parent 988b1d2164
commit 8c5ed7f5ab
1 changed files with 21 additions and 0 deletions
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21
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
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@ -978,6 +978,12 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)
/* Unstall DPG */
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS),
0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
/* Keeping one read-back to ensure all register writes are done,
* otherwise it may introduce race conditions.
*/
RREG32_SOC15(UVD, 0, mmUVD_STATUS);
return 0;
}
@ -1152,6 +1158,11 @@ static int vcn_v2_0_start(struct amdgpu_vcn_inst *vinst)
WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
/* Keeping one read-back to ensure all register writes are done,
* otherwise it may introduce race conditions.
*/
RREG32_SOC15(UVD, 0, mmUVD_STATUS);
return 0;
}
@ -1183,6 +1194,11 @@ static int vcn_v2_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)
WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
/* Keeping one read-back to ensure all register writes are done,
* otherwise it may introduce race conditions.
*/
RREG32_SOC15(UVD, 0, mmUVD_STATUS);
return 0;
}
@ -1248,6 +1264,11 @@ static int vcn_v2_0_stop(struct amdgpu_vcn_inst *vinst)
vcn_v2_0_enable_clock_gating(vinst);
vcn_v2_0_enable_static_power_gating(vinst);
/* Keeping one read-back to ensure all register writes are done,
* otherwise it may introduce race conditions.
*/
RREG32_SOC15(VCN, 0, mmUVD_STATUS);
power_off:
if (adev->pm.dpm_enabled)
amdgpu_dpm_enable_vcn(adev, false, 0);