mirror of
https://github.com/torvalds/linux.git
synced 2026-07-27 17:47:41 +02:00
Memory controller drivers for v7.2
1. Tegra MC/EMC:
- Handle system sleep, necessary to re-program registers after system
resume. A few more improvements.
- Add Tegra114 and Tegra238 Memory Controller, and Tegra114 External
MC support.
- Grow Tegra264 support.
2. Renesas XSPI: Document RZ/T2H and RZ/N2H variants, compatible with
existing devices.
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Merge tag 'memory-controller-drv-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers
Memory controller drivers for v7.2
1. Tegra MC/EMC:
- Handle system sleep, necessary to re-program registers after system
resume. A few more improvements.
- Add Tegra114 and Tegra238 Memory Controller, and Tegra114 External
MC support.
- Grow Tegra264 support.
2. Renesas XSPI: Document RZ/T2H and RZ/N2H variants, compatible with
existing devices.
* tag 'memory-controller-drv-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
memory: tegra264: Add full set of MC clients
dt-bindings: memory: tegra264: Add full set of MC client IDs
memory: tegra264: Skip clients without bpmp_id or type
memory: renesas-rpc-if: Fix duplicate device name on multi-instance platforms
dt-bindings: memory: renesas,rzg3e-xspi: Add RZ/T2H and RZ/N2H support
memory: omap-gpmc: Silence W=1 kerneldoc warnings
memory: tegra114-emc: Simplify tegra114_emc_interconnect_init() error message
memory: tegra114-emc: Do not print error on icc_node_create() failure
memory: tegra: Fix possible null pointer dereference
memory: tegra: Add Tegra114 EMC driver
memory: tegra: Implement EMEM regs and ICC ops for Tegra114
dt-bindings: memory: Document Tegra114 External Memory Controller
dt-bindings: memory: Document Tegra114 Memory Controller
memory: tegra: Add Tegra238 MC support
dt-bindings: memory: tegra: Add nvidia,tegra238-mc compatible
memory: tegra: Restore MC interrupt masks on resume
memory: tegra: Wire up system sleep PM ops
memory: tegra: Make ->resume() callback return void
memory: tegra: Deduplicate rate request management code
memory: atmel-ebi: Allow deferred probing
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
8c3fb979f1
|
|
@ -16,7 +16,9 @@ description: |
|
|||
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properties:
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compatible:
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const: nvidia,tegra124-emc
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enum:
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- nvidia,tegra114-emc
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- nvidia,tegra124-emc
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reg:
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maxItems: 1
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||||
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@ -29,6 +31,9 @@ properties:
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items:
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||||
- const: emc
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interrupts:
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maxItems: 1
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||||
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"#interconnect-cells":
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const: 0
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|
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@ -164,153 +169,12 @@ patternProperties:
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nvidia,emc-configuration:
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description:
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EMC timing characterization data. These are the registers (see
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section "15.6.2 EMC Registers" in the TRM) whose values need to
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section "20.11.2 EMC Registers" in the Tegra114 TRM or section
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"15.6.2 EMC Registers" in the Tegra124 TRM) whose values need to
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be specified, according to the board documentation.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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- description: EMC_RC
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- description: EMC_RFC
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- description: EMC_RFC_SLR
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- description: EMC_RAS
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- description: EMC_RP
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- description: EMC_R2W
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- description: EMC_W2R
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- description: EMC_R2P
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- description: EMC_W2P
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- description: EMC_RD_RCD
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- description: EMC_WR_RCD
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- description: EMC_RRD
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- description: EMC_REXT
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- description: EMC_WEXT
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- description: EMC_WDV
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- description: EMC_WDV_MASK
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- description: EMC_QUSE
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- description: EMC_QUSE_WIDTH
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- description: EMC_IBDLY
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- description: EMC_EINPUT
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- description: EMC_EINPUT_DURATION
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- description: EMC_PUTERM_EXTRA
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- description: EMC_PUTERM_WIDTH
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- description: EMC_PUTERM_ADJ
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- description: EMC_CDB_CNTL_1
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- description: EMC_CDB_CNTL_2
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- description: EMC_CDB_CNTL_3
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- description: EMC_QRST
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- description: EMC_QSAFE
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- description: EMC_RDV
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- description: EMC_RDV_MASK
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- description: EMC_REFRESH
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- description: EMC_BURST_REFRESH_NUM
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- description: EMC_PRE_REFRESH_REQ_CNT
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- description: EMC_PDEX2WR
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- description: EMC_PDEX2RD
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- description: EMC_PCHG2PDEN
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- description: EMC_ACT2PDEN
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- description: EMC_AR2PDEN
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- description: EMC_RW2PDEN
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- description: EMC_TXSR
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- description: EMC_TXSRDLL
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- description: EMC_TCKE
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- description: EMC_TCKESR
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- description: EMC_TPD
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- description: EMC_TFAW
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- description: EMC_TRPAB
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- description: EMC_TCLKSTABLE
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- description: EMC_TCLKSTOP
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- description: EMC_TREFBW
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- description: EMC_FBIO_CFG6
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- description: EMC_ODT_WRITE
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- description: EMC_ODT_READ
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- description: EMC_FBIO_CFG5
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- description: EMC_CFG_DIG_DLL
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- description: EMC_CFG_DIG_DLL_PERIOD
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- description: EMC_DLL_XFORM_DQS0
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- description: EMC_DLL_XFORM_DQS1
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- description: EMC_DLL_XFORM_DQS2
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- description: EMC_DLL_XFORM_DQS3
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- description: EMC_DLL_XFORM_DQS4
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- description: EMC_DLL_XFORM_DQS5
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- description: EMC_DLL_XFORM_DQS6
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- description: EMC_DLL_XFORM_DQS7
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- description: EMC_DLL_XFORM_DQS8
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- description: EMC_DLL_XFORM_DQS9
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- description: EMC_DLL_XFORM_DQS10
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- description: EMC_DLL_XFORM_DQS11
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- description: EMC_DLL_XFORM_DQS12
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- description: EMC_DLL_XFORM_DQS13
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- description: EMC_DLL_XFORM_DQS14
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- description: EMC_DLL_XFORM_DQS15
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- description: EMC_DLL_XFORM_QUSE0
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- description: EMC_DLL_XFORM_QUSE1
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- description: EMC_DLL_XFORM_QUSE2
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- description: EMC_DLL_XFORM_QUSE3
|
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- description: EMC_DLL_XFORM_QUSE4
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- description: EMC_DLL_XFORM_QUSE5
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- description: EMC_DLL_XFORM_QUSE6
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- description: EMC_DLL_XFORM_QUSE7
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- description: EMC_DLL_XFORM_ADDR0
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- description: EMC_DLL_XFORM_ADDR1
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- description: EMC_DLL_XFORM_ADDR2
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- description: EMC_DLL_XFORM_ADDR3
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- description: EMC_DLL_XFORM_ADDR4
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- description: EMC_DLL_XFORM_ADDR5
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- description: EMC_DLL_XFORM_QUSE8
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- description: EMC_DLL_XFORM_QUSE9
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- description: EMC_DLL_XFORM_QUSE10
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- description: EMC_DLL_XFORM_QUSE11
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- description: EMC_DLL_XFORM_QUSE12
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- description: EMC_DLL_XFORM_QUSE13
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- description: EMC_DLL_XFORM_QUSE14
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- description: EMC_DLL_XFORM_QUSE15
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- description: EMC_DLI_TRIM_TXDQS0
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- description: EMC_DLI_TRIM_TXDQS1
|
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- description: EMC_DLI_TRIM_TXDQS2
|
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- description: EMC_DLI_TRIM_TXDQS3
|
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- description: EMC_DLI_TRIM_TXDQS4
|
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- description: EMC_DLI_TRIM_TXDQS5
|
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- description: EMC_DLI_TRIM_TXDQS6
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- description: EMC_DLI_TRIM_TXDQS7
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- description: EMC_DLI_TRIM_TXDQS8
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- description: EMC_DLI_TRIM_TXDQS9
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- description: EMC_DLI_TRIM_TXDQS10
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- description: EMC_DLI_TRIM_TXDQS11
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- description: EMC_DLI_TRIM_TXDQS12
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- description: EMC_DLI_TRIM_TXDQS13
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- description: EMC_DLI_TRIM_TXDQS14
|
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- description: EMC_DLI_TRIM_TXDQS15
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- description: EMC_DLL_XFORM_DQ0
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- description: EMC_DLL_XFORM_DQ1
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- description: EMC_DLL_XFORM_DQ2
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- description: EMC_DLL_XFORM_DQ3
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- description: EMC_DLL_XFORM_DQ4
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- description: EMC_DLL_XFORM_DQ5
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- description: EMC_DLL_XFORM_DQ6
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- description: EMC_DLL_XFORM_DQ7
|
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- description: EMC_XM2CMDPADCTRL
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- description: EMC_XM2CMDPADCTRL4
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- description: EMC_XM2CMDPADCTRL5
|
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- description: EMC_XM2DQPADCTRL2
|
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- description: EMC_XM2DQPADCTRL3
|
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- description: EMC_XM2CLKPADCTRL
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- description: EMC_XM2CLKPADCTRL2
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- description: EMC_XM2COMPPADCTRL
|
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- description: EMC_XM2VTTGENPADCTRL
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- description: EMC_XM2VTTGENPADCTRL2
|
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- description: EMC_XM2VTTGENPADCTRL3
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- description: EMC_XM2DQSPADCTRL3
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- description: EMC_XM2DQSPADCTRL4
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- description: EMC_XM2DQSPADCTRL5
|
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- description: EMC_XM2DQSPADCTRL6
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- description: EMC_DSR_VTTGEN_DRV
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- description: EMC_TXDSRVTTGEN
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- description: EMC_FBIO_SPARE
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- description: EMC_ZCAL_WAIT_CNT
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- description: EMC_MRS_WAIT_CNT2
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- description: EMC_CTT
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- description: EMC_CTT_DURATION
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- description: EMC_CFG_PIPE
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- description: EMC_DYN_SELF_REF_CONTROL
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- description: EMC_QPOP
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minItems: 97
|
||||
maxItems: 143
|
||||
|
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required:
|
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- clock-frequency
|
||||
|
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@ -318,9 +182,7 @@ patternProperties:
|
|||
- nvidia,emc-auto-cal-config2
|
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- nvidia,emc-auto-cal-config3
|
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- nvidia,emc-auto-cal-interval
|
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- nvidia,emc-bgbias-ctl0
|
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- nvidia,emc-cfg
|
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- nvidia,emc-cfg-2
|
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- nvidia,emc-ctt-term-ctrl
|
||||
- nvidia,emc-mode-1
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- nvidia,emc-mode-2
|
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@ -344,6 +206,22 @@ required:
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- "#interconnect-cells"
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- operating-points-v2
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
|
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- nvidia,tegra124-emc
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then:
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patternProperties:
|
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"^emc-timings-[0-9]+$":
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patternProperties:
|
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"^timing-[0-9]+$":
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required:
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- nvidia,emc-bgbias-ctl0
|
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- nvidia,emc-cfg-2
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additionalProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -19,7 +19,9 @@ description: |
|
|||
|
||||
properties:
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compatible:
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const: nvidia,tegra124-mc
|
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enum:
|
||||
- nvidia,tegra114-mc
|
||||
- nvidia,tegra124-mc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
|
@ -64,29 +66,12 @@ patternProperties:
|
|||
|
||||
nvidia,emem-configuration:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description: |
|
||||
description:
|
||||
Values to be written to the EMEM register block. See section
|
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"15.6.1 MC Registers" in the TRM.
|
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items:
|
||||
- description: MC_EMEM_ARB_CFG
|
||||
- description: MC_EMEM_ARB_OUTSTANDING_REQ
|
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- description: MC_EMEM_ARB_TIMING_RCD
|
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- description: MC_EMEM_ARB_TIMING_RP
|
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- description: MC_EMEM_ARB_TIMING_RC
|
||||
- description: MC_EMEM_ARB_TIMING_RAS
|
||||
- description: MC_EMEM_ARB_TIMING_FAW
|
||||
- description: MC_EMEM_ARB_TIMING_RRD
|
||||
- description: MC_EMEM_ARB_TIMING_RAP2PRE
|
||||
- description: MC_EMEM_ARB_TIMING_WAP2PRE
|
||||
- description: MC_EMEM_ARB_TIMING_R2R
|
||||
- description: MC_EMEM_ARB_TIMING_W2W
|
||||
- description: MC_EMEM_ARB_TIMING_R2W
|
||||
- description: MC_EMEM_ARB_TIMING_W2R
|
||||
- description: MC_EMEM_ARB_DA_TURNS
|
||||
- description: MC_EMEM_ARB_DA_COVERS
|
||||
- description: MC_EMEM_ARB_MISC0
|
||||
- description: MC_EMEM_ARB_MISC1
|
||||
- description: MC_EMEM_ARB_RING1_THROTTLE
|
||||
"20.11.1 MC Registers" in the Tegea114 TRM or
|
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"15.6.1 MC Registers" in the Tegra124 TRM.
|
||||
minItems: 18
|
||||
maxItems: 19
|
||||
|
||||
required:
|
||||
- clock-frequency
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@ properties:
|
|||
- nvidia,tegra186-mc
|
||||
- nvidia,tegra194-mc
|
||||
- nvidia,tegra234-mc
|
||||
- nvidia,tegra238-mc
|
||||
- nvidia,tegra264-mc
|
||||
|
||||
reg:
|
||||
|
|
@ -266,6 +267,36 @@ allOf:
|
|||
|
||||
interrupt-names: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
const: nvidia,tegra238-mc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 10
|
||||
maxItems: 10
|
||||
description: 9 memory controller channels and 1 for stream-id registers
|
||||
|
||||
reg-names:
|
||||
items:
|
||||
- const: sid
|
||||
- const: broadcast
|
||||
- const: ch0
|
||||
- const: ch1
|
||||
- const: ch2
|
||||
- const: ch3
|
||||
- const: ch4
|
||||
- const: ch5
|
||||
- const: ch6
|
||||
- const: ch7
|
||||
|
||||
interrupts:
|
||||
items:
|
||||
- description: MC general interrupt
|
||||
|
||||
interrupt-names: false
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -30,6 +30,8 @@ properties:
|
|||
- enum:
|
||||
- renesas,r9a09g056-xspi # RZ/V2N
|
||||
- renesas,r9a09g057-xspi # RZ/V2H(P)
|
||||
- renesas,r9a09g077-xspi # RZ/T2H
|
||||
- renesas,r9a09g087-xspi # RZ/N2H
|
||||
- const: renesas,r9a09g047-xspi
|
||||
|
||||
reg:
|
||||
|
|
@ -53,28 +55,38 @@ properties:
|
|||
- const: err_pulse
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: AHB clock
|
||||
- description: AXI clock
|
||||
- description: SPI clock
|
||||
- description: Double speed SPI clock
|
||||
oneOf:
|
||||
- items:
|
||||
- description: AHB clock
|
||||
- description: AXI clock
|
||||
- description: SPI clock
|
||||
- description: Double speed SPI clock
|
||||
- items:
|
||||
- description: AHB clock
|
||||
- description: SPI clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ahb
|
||||
- const: axi
|
||||
- const: spi
|
||||
- const: spix2
|
||||
oneOf:
|
||||
- items:
|
||||
- const: ahb
|
||||
- const: axi
|
||||
- const: spi
|
||||
- const: spix2
|
||||
- items:
|
||||
- const: ahb
|
||||
- const: spi
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Hardware reset
|
||||
- description: AXI reset
|
||||
|
||||
reset-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: hresetn
|
||||
- const: aresetn
|
||||
|
|
@ -109,6 +121,34 @@ required:
|
|||
- '#address-cells'
|
||||
- '#size-cells'
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- renesas,r9a09g077-xspi
|
||||
- renesas,r9a09g087-xspi
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
maxItems: 2
|
||||
resets:
|
||||
maxItems: 1
|
||||
reset-names:
|
||||
maxItems: 1
|
||||
else:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 4
|
||||
clock-names:
|
||||
minItems: 4
|
||||
resets:
|
||||
minItems: 2
|
||||
reset-names:
|
||||
minItems: 2
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
|
|
|||
|
|
@ -628,10 +628,11 @@ static __maybe_unused int atmel_ebi_resume(struct device *dev)
|
|||
static SIMPLE_DEV_PM_OPS(atmel_ebi_pm_ops, NULL, atmel_ebi_resume);
|
||||
|
||||
static struct platform_driver atmel_ebi_driver = {
|
||||
.probe = atmel_ebi_probe,
|
||||
.driver = {
|
||||
.name = "atmel-ebi",
|
||||
.of_match_table = atmel_ebi_id_table,
|
||||
.pm = &atmel_ebi_pm_ops,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver_probe(atmel_ebi_driver, atmel_ebi_probe);
|
||||
builtin_platform_driver(atmel_ebi_driver);
|
||||
|
|
|
|||
|
|
@ -432,13 +432,9 @@ static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
|
|||
*
|
||||
*/
|
||||
static int get_gpmc_timing_reg(
|
||||
/* timing specifiers */
|
||||
int cs, int reg, int st_bit, int end_bit, int max,
|
||||
const char *name, const enum gpmc_clk_domain cd,
|
||||
/* value transform */
|
||||
int shift,
|
||||
/* format specifiers */
|
||||
bool raw, bool noval)
|
||||
int shift, bool raw, bool noval)
|
||||
{
|
||||
u32 l;
|
||||
int nr_bits;
|
||||
|
|
|
|||
|
|
@ -1034,7 +1034,7 @@ static int rpcif_probe(struct platform_device *pdev)
|
|||
return dev_err_probe(dev, PTR_ERR(rpc->spi_clk),
|
||||
"cannot get enabled spi clk\n");
|
||||
|
||||
vdev = platform_device_alloc(name, pdev->id);
|
||||
vdev = platform_device_alloc(name, PLATFORM_DEVID_AUTO);
|
||||
if (!vdev)
|
||||
return -ENOMEM;
|
||||
vdev->dev.parent = dev;
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@ config TEGRA20_EMC
|
|||
select DEVFREQ_GOV_SIMPLE_ONDEMAND
|
||||
select PM_DEVFREQ
|
||||
select DDR
|
||||
select TEGRA_EMC_COMMON
|
||||
help
|
||||
This driver is for the External Memory Controller (EMC) found on
|
||||
Tegra20 chips. The EMC controls the external DRAM on the board.
|
||||
|
|
@ -29,18 +30,33 @@ config TEGRA30_EMC
|
|||
depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST
|
||||
select PM_OPP
|
||||
select DDR
|
||||
select TEGRA_EMC_COMMON
|
||||
help
|
||||
This driver is for the External Memory Controller (EMC) found on
|
||||
Tegra30 chips. The EMC controls the external DRAM on the board.
|
||||
This driver is required to change memory timings / clock rate for
|
||||
external memory.
|
||||
|
||||
config TEGRA114_EMC
|
||||
tristate "NVIDIA Tegra114 External Memory Controller driver"
|
||||
default ARCH_TEGRA_114_SOC
|
||||
depends on ARCH_TEGRA_114_SOC || COMPILE_TEST
|
||||
select TEGRA124_CLK_EMC if ARCH_TEGRA
|
||||
select PM_OPP
|
||||
select TEGRA_EMC_COMMON
|
||||
help
|
||||
This driver is for the External Memory Controller (EMC) found on
|
||||
Tegra114 chips. The EMC controls the external DRAM on the board.
|
||||
This driver is required to change memory timings / clock rate for
|
||||
external memory.
|
||||
|
||||
config TEGRA124_EMC
|
||||
tristate "NVIDIA Tegra124 External Memory Controller driver"
|
||||
default ARCH_TEGRA_124_SOC
|
||||
depends on ARCH_TEGRA_124_SOC || COMPILE_TEST
|
||||
select TEGRA124_CLK_EMC if ARCH_TEGRA
|
||||
select PM_OPP
|
||||
select TEGRA_EMC_COMMON
|
||||
help
|
||||
This driver is for the External Memory Controller (EMC) found on
|
||||
Tegra124 chips. The EMC controls the external DRAM on the board.
|
||||
|
|
@ -61,4 +77,7 @@ config TEGRA210_EMC
|
|||
This driver is required to change memory timings / clock rate for
|
||||
external memory.
|
||||
|
||||
config TEGRA_EMC_COMMON
|
||||
tristate
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -10,12 +10,15 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
|
|||
tegra-mc-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o
|
||||
tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra194.o
|
||||
tegra-mc-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra186.o tegra234.o
|
||||
tegra-mc-$(CONFIG_ARCH_TEGRA_238_SOC) += tegra186.o tegra234.o tegra238.o
|
||||
tegra-mc-$(CONFIG_ARCH_TEGRA_264_SOC) += tegra186.o tegra264.o
|
||||
|
||||
obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
|
||||
|
||||
obj-$(CONFIG_TEGRA_EMC_COMMON) += tegra-emc-common.o
|
||||
obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o
|
||||
obj-$(CONFIG_TEGRA30_EMC) += tegra30-emc.o
|
||||
obj-$(CONFIG_TEGRA114_EMC) += tegra114-emc.o
|
||||
obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
|
||||
obj-$(CONFIG_TEGRA210_EMC_TABLE) += tegra210-emc-table.o
|
||||
obj-$(CONFIG_TEGRA210_EMC) += tegra210-emc.o
|
||||
|
|
|
|||
|
|
@ -13,6 +13,7 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/sort.h>
|
||||
#include <linux/tegra-icc.h>
|
||||
|
|
@ -49,6 +50,9 @@ static const struct of_device_id tegra_mc_of_match[] = {
|
|||
#ifdef CONFIG_ARCH_TEGRA_234_SOC
|
||||
{ .compatible = "nvidia,tegra234-mc", .data = &tegra234_mc_soc },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_TEGRA_238_SOC
|
||||
{ .compatible = "nvidia,tegra238-mc", .data = &tegra238_mc_soc },
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_TEGRA_264_SOC
|
||||
{ .compatible = "nvidia,tegra264-mc", .data = &tegra264_mc_soc },
|
||||
#endif
|
||||
|
|
@ -910,6 +914,19 @@ static void tegra_mc_num_channel_enabled(struct tegra_mc *mc)
|
|||
}
|
||||
}
|
||||
|
||||
static void tegra_mc_setup_intmask(struct tegra_mc *mc)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < mc->soc->num_intmasks; i++) {
|
||||
if (mc->soc->num_channels)
|
||||
mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask,
|
||||
mc->soc->intmasks[i].reg);
|
||||
else
|
||||
mc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg);
|
||||
}
|
||||
}
|
||||
|
||||
static int tegra_mc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct tegra_mc *mc;
|
||||
|
|
@ -970,13 +987,7 @@ static int tegra_mc_probe(struct platform_device *pdev)
|
|||
}
|
||||
}
|
||||
|
||||
for (i = 0; i < mc->soc->num_intmasks; i++) {
|
||||
if (mc->soc->num_channels)
|
||||
mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask,
|
||||
mc->soc->intmasks[i].reg);
|
||||
else
|
||||
mc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg);
|
||||
}
|
||||
tegra_mc_setup_intmask(mc);
|
||||
}
|
||||
|
||||
if (mc->soc->reset_ops) {
|
||||
|
|
@ -1010,10 +1021,25 @@ static void tegra_mc_sync_state(struct device *dev)
|
|||
icc_sync_state(dev);
|
||||
}
|
||||
|
||||
static int tegra_mc_resume(struct device *dev)
|
||||
{
|
||||
struct tegra_mc *mc = dev_get_drvdata(dev);
|
||||
|
||||
if (mc->soc->ops && mc->soc->ops->resume)
|
||||
mc->soc->ops->resume(mc);
|
||||
|
||||
tegra_mc_setup_intmask(mc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static DEFINE_SIMPLE_DEV_PM_OPS(tegra_mc_pm_ops, NULL, tegra_mc_resume);
|
||||
|
||||
static struct platform_driver tegra_mc_driver = {
|
||||
.driver = {
|
||||
.name = "tegra-mc",
|
||||
.of_match_table = tegra_mc_of_match,
|
||||
.pm = pm_sleep_ptr(&tegra_mc_pm_ops),
|
||||
.suppress_bind_attrs = true,
|
||||
.sync_state = tegra_mc_sync_state,
|
||||
},
|
||||
|
|
|
|||
|
|
@ -240,6 +240,14 @@ extern const struct tegra_mc_soc tegra194_mc_soc;
|
|||
extern const struct tegra_mc_soc tegra234_mc_soc;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARCH_TEGRA_234_SOC) || defined(CONFIG_ARCH_TEGRA_238_SOC)
|
||||
extern const struct tegra_mc_icc_ops tegra234_mc_icc_ops;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_238_SOC
|
||||
extern const struct tegra_mc_soc tegra238_mc_soc;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_TEGRA_264_SOC
|
||||
extern const struct tegra_mc_soc tegra264_mc_soc;
|
||||
#endif
|
||||
|
|
@ -256,6 +264,7 @@ extern const struct tegra_mc_ops tegra30_mc_ops;
|
|||
#if defined(CONFIG_ARCH_TEGRA_186_SOC) || \
|
||||
defined(CONFIG_ARCH_TEGRA_194_SOC) || \
|
||||
defined(CONFIG_ARCH_TEGRA_234_SOC) || \
|
||||
defined(CONFIG_ARCH_TEGRA_238_SOC) || \
|
||||
defined(CONFIG_ARCH_TEGRA_264_SOC)
|
||||
extern const struct tegra_mc_ops tegra186_mc_ops;
|
||||
#endif
|
||||
|
|
|
|||
143
drivers/memory/tegra/tegra-emc-common.c
Normal file
143
drivers/memory/tegra/tegra-emc-common.c
Normal file
|
|
@ -0,0 +1,143 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/pm_opp.h>
|
||||
|
||||
#include "tegra-emc-common.h"
|
||||
|
||||
/**
|
||||
* tegra_emc_rate_requests_init() - Initialize EMC rate request tracking
|
||||
* @reqs: struct tegra_emc_rate_requests to initialize.
|
||||
* @dev: EMC device.
|
||||
*
|
||||
* Initializes the rate request tracking state with default state
|
||||
* (no active requests). Must be called before using @reqs with
|
||||
* other functions.
|
||||
*/
|
||||
void tegra_emc_rate_requests_init(struct tegra_emc_rate_requests *reqs,
|
||||
struct device *dev)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
mutex_init(&reqs->rate_lock);
|
||||
reqs->dev = dev;
|
||||
|
||||
for (i = 0; i < TEGRA_EMC_RATE_TYPE_MAX; i++) {
|
||||
reqs->requested_rate[i].min_rate = 0;
|
||||
reqs->requested_rate[i].max_rate = ULONG_MAX;
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(tegra_emc_rate_requests_init);
|
||||
|
||||
/* Caller must hold reqs->rate_lock. */
|
||||
static int tegra_emc_request_rate(struct tegra_emc_rate_requests *reqs,
|
||||
unsigned long new_min_rate,
|
||||
unsigned long new_max_rate,
|
||||
enum tegra_emc_rate_request_type type)
|
||||
{
|
||||
struct tegra_emc_rate_request *req = reqs->requested_rate;
|
||||
unsigned long min_rate = 0, max_rate = ULONG_MAX;
|
||||
unsigned int i;
|
||||
int err;
|
||||
|
||||
lockdep_assert_held(&reqs->rate_lock);
|
||||
|
||||
/* select minimum and maximum rates among the requested rates */
|
||||
for (i = 0; i < TEGRA_EMC_RATE_TYPE_MAX; i++, req++) {
|
||||
if (i == type) {
|
||||
min_rate = max(new_min_rate, min_rate);
|
||||
max_rate = min(new_max_rate, max_rate);
|
||||
} else {
|
||||
min_rate = max(req->min_rate, min_rate);
|
||||
max_rate = min(req->max_rate, max_rate);
|
||||
}
|
||||
}
|
||||
|
||||
if (min_rate > max_rate) {
|
||||
dev_err_ratelimited(reqs->dev, "%s: type %u: out of range: %lu %lu\n",
|
||||
__func__, type, min_rate, max_rate);
|
||||
return -ERANGE;
|
||||
}
|
||||
|
||||
/*
|
||||
* EMC rate-changes should go via OPP API because it manages voltage
|
||||
* changes.
|
||||
*/
|
||||
err = dev_pm_opp_set_rate(reqs->dev, min_rate);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
reqs->requested_rate[type].min_rate = new_min_rate;
|
||||
reqs->requested_rate[type].max_rate = new_max_rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* tegra_emc_set_min_rate() - Update minimum rate request for a request type
|
||||
* @reqs: rate request tracking state
|
||||
* @rate: new minimum rate in Hz requested by @type
|
||||
* @type: type of request
|
||||
*
|
||||
* Records @rate as the new minimum rate request for @type, recalculates target
|
||||
* rate based on all requests and applies new rate through the OPP API.
|
||||
*
|
||||
* Context: Sleeps. Requests to same @reqs are synchronized via mutex.
|
||||
*
|
||||
* Return:
|
||||
* * %0 - success
|
||||
* * %-ERANGE - request would cause minimum rate request to be higher than
|
||||
* maximum rate request
|
||||
* * other - setting new rate failed
|
||||
*/
|
||||
int tegra_emc_set_min_rate(struct tegra_emc_rate_requests *reqs,
|
||||
unsigned long rate,
|
||||
enum tegra_emc_rate_request_type type)
|
||||
{
|
||||
struct tegra_emc_rate_request *req = &reqs->requested_rate[type];
|
||||
int ret;
|
||||
|
||||
mutex_lock(&reqs->rate_lock);
|
||||
ret = tegra_emc_request_rate(reqs, rate, req->max_rate, type);
|
||||
mutex_unlock(&reqs->rate_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(tegra_emc_set_min_rate);
|
||||
|
||||
/**
|
||||
* tegra_emc_set_max_rate() - Update maximum rate request for a request type
|
||||
* @reqs: rate request tracking state
|
||||
* @rate: new maximum rate in Hz requested by @type
|
||||
* @type: type of request
|
||||
*
|
||||
* Records @rate as the new maximum rate request for @type, recalculates target
|
||||
* rate based on all requests and applies new rate through the OPP API.
|
||||
*
|
||||
* Context: Sleeps. Requests to same @reqs are synchronized via mutex.
|
||||
*
|
||||
* Return:
|
||||
* * %0 - success
|
||||
* * %-ERANGE - request would cause minimum rate request to be higher than
|
||||
* maximum rate request
|
||||
* * other - setting new rate failed
|
||||
*/
|
||||
int tegra_emc_set_max_rate(struct tegra_emc_rate_requests *reqs,
|
||||
unsigned long rate,
|
||||
enum tegra_emc_rate_request_type type)
|
||||
{
|
||||
struct tegra_emc_rate_request *req = &reqs->requested_rate[type];
|
||||
int ret;
|
||||
|
||||
mutex_lock(&reqs->rate_lock);
|
||||
ret = tegra_emc_request_rate(reqs, req->min_rate, rate, type);
|
||||
mutex_unlock(&reqs->rate_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(tegra_emc_set_max_rate);
|
||||
|
||||
MODULE_DESCRIPTION("NVIDIA Tegra EMC common code");
|
||||
MODULE_LICENSE("GPL");
|
||||
46
drivers/memory/tegra/tegra-emc-common.h
Normal file
46
drivers/memory/tegra/tegra-emc-common.h
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
|
||||
#ifndef TEGRA_EMC_COMMON_H
|
||||
#define TEGRA_EMC_COMMON_H
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/mutex.h>
|
||||
|
||||
/**
|
||||
* enum tegra_emc_rate_request_type - source of rate request
|
||||
* @TEGRA_EMC_RATE_DEVFREQ: rate requested by devfreq governor
|
||||
* @TEGRA_EMC_RATE_DEBUG: rate requested through debugfs knobs
|
||||
* @TEGRA_EMC_RATE_ICC: rate requested by ICC framework
|
||||
* @TEGRA_EMC_RATE_TYPE_MAX: number of valid request types
|
||||
*/
|
||||
enum tegra_emc_rate_request_type {
|
||||
TEGRA_EMC_RATE_DEVFREQ,
|
||||
TEGRA_EMC_RATE_DEBUG,
|
||||
TEGRA_EMC_RATE_ICC,
|
||||
TEGRA_EMC_RATE_TYPE_MAX,
|
||||
};
|
||||
|
||||
struct tegra_emc_rate_request {
|
||||
unsigned long min_rate;
|
||||
unsigned long max_rate;
|
||||
};
|
||||
|
||||
struct tegra_emc_rate_requests {
|
||||
struct tegra_emc_rate_request requested_rate[TEGRA_EMC_RATE_TYPE_MAX];
|
||||
/* Protects @requested_rate. */
|
||||
struct mutex rate_lock;
|
||||
struct device *dev;
|
||||
};
|
||||
|
||||
void tegra_emc_rate_requests_init(struct tegra_emc_rate_requests *reqs,
|
||||
struct device *dev);
|
||||
|
||||
int tegra_emc_set_min_rate(struct tegra_emc_rate_requests *reqs,
|
||||
unsigned long rate,
|
||||
enum tegra_emc_rate_request_type type);
|
||||
|
||||
int tegra_emc_set_max_rate(struct tegra_emc_rate_requests *reqs,
|
||||
unsigned long rate,
|
||||
enum tegra_emc_rate_request_type type);
|
||||
|
||||
#endif /* TEGRA_EMC_COMMON_H */
|
||||
1351
drivers/memory/tegra/tegra114-emc.c
Normal file
1351
drivers/memory/tegra/tegra114-emc.c
Normal file
File diff suppressed because it is too large
Load Diff
|
|
@ -3,6 +3,7 @@
|
|||
* Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/mm.h>
|
||||
|
||||
|
|
@ -1101,6 +1102,195 @@ static const struct tegra_mc_reset tegra114_mc_resets[] = {
|
|||
TEGRA114_MC_RESET(VI, 0x200, 0x204, 17),
|
||||
};
|
||||
|
||||
static void tegra114_mc_tune_client_latency(struct tegra_mc *mc,
|
||||
const struct tegra_mc_client *client,
|
||||
unsigned int bandwidth_mbytes_sec)
|
||||
{
|
||||
u32 arb_tolerance_compensation_nsec, arb_tolerance_compensation_div;
|
||||
unsigned int fifo_size = client->fifo_size;
|
||||
u32 arb_nsec, la_ticks, value;
|
||||
|
||||
/* see 20.3.1.1 Client Configuration in Tegra4 TRM v01p */
|
||||
if (bandwidth_mbytes_sec)
|
||||
arb_nsec = fifo_size * NSEC_PER_USEC / bandwidth_mbytes_sec;
|
||||
else
|
||||
arb_nsec = U32_MAX;
|
||||
|
||||
/*
|
||||
* Latency allowness should be set with consideration for the module's
|
||||
* latency tolerance and internal buffering capabilities.
|
||||
*
|
||||
* Display memory clients use isochronous transfers and have very low
|
||||
* tolerance to a belated transfers. Hence we need to compensate the
|
||||
* memory arbitration imperfection for them in order to prevent FIFO
|
||||
* underflow condition when memory bus is busy.
|
||||
*
|
||||
* VI clients also need a stronger compensation.
|
||||
*/
|
||||
switch (client->swgroup) {
|
||||
case TEGRA_SWGROUP_MPCORE:
|
||||
case TEGRA_SWGROUP_PTC:
|
||||
/*
|
||||
* We always want lower latency for these clients, hence
|
||||
* don't touch them.
|
||||
*/
|
||||
return;
|
||||
|
||||
case TEGRA_SWGROUP_DC:
|
||||
case TEGRA_SWGROUP_DCB:
|
||||
arb_tolerance_compensation_nsec = 1050;
|
||||
arb_tolerance_compensation_div = 2;
|
||||
break;
|
||||
|
||||
case TEGRA_SWGROUP_VI:
|
||||
arb_tolerance_compensation_nsec = 1050;
|
||||
arb_tolerance_compensation_div = 1;
|
||||
break;
|
||||
|
||||
default:
|
||||
arb_tolerance_compensation_nsec = 150;
|
||||
arb_tolerance_compensation_div = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
if (arb_nsec > arb_tolerance_compensation_nsec)
|
||||
arb_nsec -= arb_tolerance_compensation_nsec;
|
||||
else
|
||||
arb_nsec = 0;
|
||||
|
||||
arb_nsec /= arb_tolerance_compensation_div;
|
||||
|
||||
/*
|
||||
* Latency allowance is a number of ticks a request from a particular
|
||||
* client may wait in the EMEM arbiter before it becomes a high-priority
|
||||
* request.
|
||||
*/
|
||||
la_ticks = arb_nsec / mc->tick;
|
||||
la_ticks = min(la_ticks, client->regs.la.mask);
|
||||
|
||||
value = mc_readl(mc, client->regs.la.reg);
|
||||
value &= ~(client->regs.la.mask << client->regs.la.shift);
|
||||
value |= la_ticks << client->regs.la.shift;
|
||||
mc_writel(mc, value, client->regs.la.reg);
|
||||
}
|
||||
|
||||
static int tegra114_mc_icc_set(struct icc_node *src, struct icc_node *dst)
|
||||
{
|
||||
struct tegra_mc *mc = icc_provider_to_tegra_mc(src->provider);
|
||||
const struct tegra_mc_client *client = &mc->soc->clients[src->id];
|
||||
u64 peak_bandwidth = icc_units_to_bps(src->peak_bw);
|
||||
|
||||
/*
|
||||
* Skip pre-initialization that is done by icc_node_add(), which sets
|
||||
* bandwidth to maximum for all clients before drivers are loaded.
|
||||
*
|
||||
* This doesn't make sense for us because we don't have drivers for all
|
||||
* clients and it's okay to keep configuration left from bootloader
|
||||
* during boot, at least for today.
|
||||
*/
|
||||
if (src == dst)
|
||||
return 0;
|
||||
|
||||
/* convert bytes/sec to megabytes/sec */
|
||||
do_div(peak_bandwidth, 1000000);
|
||||
|
||||
tegra114_mc_tune_client_latency(mc, client, peak_bandwidth);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra114_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw,
|
||||
u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
|
||||
{
|
||||
/*
|
||||
* ISO clients need to reserve extra bandwidth up-front because
|
||||
* there could be high bandwidth pressure during initial filling
|
||||
* of the client's FIFO buffers. Secondly, we need to take into
|
||||
* account impurities of the memory subsystem.
|
||||
*/
|
||||
if (tag & TEGRA_MC_ICC_TAG_ISO)
|
||||
peak_bw = tegra_mc_scale_percents(peak_bw, 400);
|
||||
|
||||
*agg_avg += avg_bw;
|
||||
*agg_peak = max(*agg_peak, peak_bw);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct icc_node_data *
|
||||
tegra114_mc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)
|
||||
{
|
||||
struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
|
||||
const struct tegra_mc_client *client;
|
||||
unsigned int i, idx = spec->args[0];
|
||||
struct icc_node_data *ndata;
|
||||
struct icc_node *node;
|
||||
|
||||
list_for_each_entry(node, &mc->provider.nodes, node_list) {
|
||||
if (node->id != idx)
|
||||
continue;
|
||||
|
||||
ndata = kzalloc_obj(*ndata);
|
||||
if (!ndata)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
client = &mc->soc->clients[idx];
|
||||
ndata->node = node;
|
||||
|
||||
switch (client->swgroup) {
|
||||
case TEGRA_SWGROUP_DC:
|
||||
case TEGRA_SWGROUP_DCB:
|
||||
case TEGRA_SWGROUP_PTC:
|
||||
case TEGRA_SWGROUP_VI:
|
||||
/* these clients are isochronous by default */
|
||||
ndata->tag = TEGRA_MC_ICC_TAG_ISO;
|
||||
break;
|
||||
|
||||
default:
|
||||
ndata->tag = TEGRA_MC_ICC_TAG_DEFAULT;
|
||||
break;
|
||||
}
|
||||
|
||||
return ndata;
|
||||
}
|
||||
|
||||
for (i = 0; i < mc->soc->num_clients; i++) {
|
||||
if (mc->soc->clients[i].id == idx)
|
||||
return ERR_PTR(-EPROBE_DEFER);
|
||||
}
|
||||
|
||||
dev_err(mc->dev, "invalid ICC client ID %u\n", idx);
|
||||
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
static const struct tegra_mc_icc_ops tegra114_mc_icc_ops = {
|
||||
.xlate_extended = tegra114_mc_of_icc_xlate_extended,
|
||||
.aggregate = tegra114_mc_icc_aggreate,
|
||||
.set = tegra114_mc_icc_set,
|
||||
};
|
||||
|
||||
static const unsigned long tegra114_mc_emem_regs[] = {
|
||||
MC_EMEM_ARB_CFG,
|
||||
MC_EMEM_ARB_OUTSTANDING_REQ,
|
||||
MC_EMEM_ARB_TIMING_RCD,
|
||||
MC_EMEM_ARB_TIMING_RP,
|
||||
MC_EMEM_ARB_TIMING_RC,
|
||||
MC_EMEM_ARB_TIMING_RAS,
|
||||
MC_EMEM_ARB_TIMING_FAW,
|
||||
MC_EMEM_ARB_TIMING_RRD,
|
||||
MC_EMEM_ARB_TIMING_RAP2PRE,
|
||||
MC_EMEM_ARB_TIMING_WAP2PRE,
|
||||
MC_EMEM_ARB_TIMING_R2R,
|
||||
MC_EMEM_ARB_TIMING_W2W,
|
||||
MC_EMEM_ARB_TIMING_R2W,
|
||||
MC_EMEM_ARB_TIMING_W2R,
|
||||
MC_EMEM_ARB_DA_TURNS,
|
||||
MC_EMEM_ARB_DA_COVERS,
|
||||
MC_EMEM_ARB_MISC0,
|
||||
MC_EMEM_ARB_RING1_THROTTLE,
|
||||
};
|
||||
|
||||
static const struct tegra_mc_intmask tegra114_mc_intmasks[] = {
|
||||
{
|
||||
.reg = MC_INTMASK,
|
||||
|
|
@ -1116,11 +1306,14 @@ const struct tegra_mc_soc tegra114_mc_soc = {
|
|||
.atom_size = 32,
|
||||
.client_id_mask = 0x7f,
|
||||
.smmu = &tegra114_smmu_soc,
|
||||
.emem_regs = tegra114_mc_emem_regs,
|
||||
.num_emem_regs = ARRAY_SIZE(tegra114_mc_emem_regs),
|
||||
.intmasks = tegra114_mc_intmasks,
|
||||
.num_intmasks = ARRAY_SIZE(tegra114_mc_intmasks),
|
||||
.reset_ops = &tegra_mc_reset_ops_common,
|
||||
.resets = tegra114_mc_resets,
|
||||
.num_resets = ARRAY_SIZE(tegra114_mc_resets),
|
||||
.icc_ops = &tegra114_mc_icc_ops,
|
||||
.ops = &tegra30_mc_ops,
|
||||
.regs = &tegra20_mc_regs,
|
||||
.handle_irq = tegra30_mc_irq_handlers,
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@
|
|||
#include <soc/tegra/mc.h>
|
||||
|
||||
#include "mc.h"
|
||||
#include "tegra-emc-common.h"
|
||||
|
||||
#define EMC_FBIO_CFG5 0x104
|
||||
#define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
|
||||
|
|
@ -467,17 +468,6 @@ struct emc_timing {
|
|||
u32 emc_zcal_interval;
|
||||
};
|
||||
|
||||
enum emc_rate_request_type {
|
||||
EMC_RATE_DEBUG,
|
||||
EMC_RATE_ICC,
|
||||
EMC_RATE_TYPE_MAX,
|
||||
};
|
||||
|
||||
struct emc_rate_request {
|
||||
unsigned long min_rate;
|
||||
unsigned long max_rate;
|
||||
};
|
||||
|
||||
struct tegra_emc {
|
||||
struct device *dev;
|
||||
|
||||
|
|
@ -503,14 +493,7 @@ struct tegra_emc {
|
|||
|
||||
struct icc_provider provider;
|
||||
|
||||
/*
|
||||
* There are multiple sources in the EMC driver which could request
|
||||
* a min/max clock rate, these rates are contained in this array.
|
||||
*/
|
||||
struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX];
|
||||
|
||||
/* protect shared rate-change code path */
|
||||
struct mutex rate_lock;
|
||||
struct tegra_emc_rate_requests reqs;
|
||||
};
|
||||
|
||||
/* Timing change sequence functions */
|
||||
|
|
@ -1041,83 +1024,6 @@ tegra124_emc_find_node_by_ram_code(struct device_node *node, u32 ram_code)
|
|||
return NULL;
|
||||
}
|
||||
|
||||
static void tegra124_emc_rate_requests_init(struct tegra_emc *emc)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < EMC_RATE_TYPE_MAX; i++) {
|
||||
emc->requested_rate[i].min_rate = 0;
|
||||
emc->requested_rate[i].max_rate = ULONG_MAX;
|
||||
}
|
||||
}
|
||||
|
||||
static int emc_request_rate(struct tegra_emc *emc,
|
||||
unsigned long new_min_rate,
|
||||
unsigned long new_max_rate,
|
||||
enum emc_rate_request_type type)
|
||||
{
|
||||
struct emc_rate_request *req = emc->requested_rate;
|
||||
unsigned long min_rate = 0, max_rate = ULONG_MAX;
|
||||
unsigned int i;
|
||||
int err;
|
||||
|
||||
/* select minimum and maximum rates among the requested rates */
|
||||
for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) {
|
||||
if (i == type) {
|
||||
min_rate = max(new_min_rate, min_rate);
|
||||
max_rate = min(new_max_rate, max_rate);
|
||||
} else {
|
||||
min_rate = max(req->min_rate, min_rate);
|
||||
max_rate = min(req->max_rate, max_rate);
|
||||
}
|
||||
}
|
||||
|
||||
if (min_rate > max_rate) {
|
||||
dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n",
|
||||
__func__, type, min_rate, max_rate);
|
||||
return -ERANGE;
|
||||
}
|
||||
|
||||
/*
|
||||
* EMC rate-changes should go via OPP API because it manages voltage
|
||||
* changes.
|
||||
*/
|
||||
err = dev_pm_opp_set_rate(emc->dev, min_rate);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
emc->requested_rate[type].min_rate = new_min_rate;
|
||||
emc->requested_rate[type].max_rate = new_max_rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,
|
||||
enum emc_rate_request_type type)
|
||||
{
|
||||
struct emc_rate_request *req = &emc->requested_rate[type];
|
||||
int ret;
|
||||
|
||||
mutex_lock(&emc->rate_lock);
|
||||
ret = emc_request_rate(emc, rate, req->max_rate, type);
|
||||
mutex_unlock(&emc->rate_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,
|
||||
enum emc_rate_request_type type)
|
||||
{
|
||||
struct emc_rate_request *req = &emc->requested_rate[type];
|
||||
int ret;
|
||||
|
||||
mutex_lock(&emc->rate_lock);
|
||||
ret = emc_request_rate(emc, req->min_rate, rate, type);
|
||||
mutex_unlock(&emc->rate_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* debugfs interface
|
||||
*
|
||||
|
|
@ -1190,7 +1096,7 @@ static int tegra124_emc_debug_min_rate_set(void *data, u64 rate)
|
|||
if (!tegra124_emc_validate_rate(emc, rate))
|
||||
return -EINVAL;
|
||||
|
||||
err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);
|
||||
err = tegra_emc_set_min_rate(&emc->reqs, rate, TEGRA_EMC_RATE_DEBUG);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
|
|
@ -1220,7 +1126,7 @@ static int tegra124_emc_debug_max_rate_set(void *data, u64 rate)
|
|||
if (!tegra124_emc_validate_rate(emc, rate))
|
||||
return -EINVAL;
|
||||
|
||||
err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);
|
||||
err = tegra_emc_set_max_rate(&emc->reqs, rate, TEGRA_EMC_RATE_DEBUG);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
|
|
@ -1327,7 +1233,7 @@ static int emc_icc_set(struct icc_node *src, struct icc_node *dst)
|
|||
do_div(rate, ddr * dram_data_bus_width_bytes);
|
||||
rate = min_t(u64, rate, U32_MAX);
|
||||
|
||||
err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);
|
||||
err = tegra_emc_set_min_rate(&emc->reqs, rate, TEGRA_EMC_RATE_ICC);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
|
|
@ -1441,7 +1347,6 @@ static int tegra124_emc_probe(struct platform_device *pdev)
|
|||
if (!emc)
|
||||
return -ENOMEM;
|
||||
|
||||
mutex_init(&emc->rate_lock);
|
||||
emc->dev = &pdev->dev;
|
||||
|
||||
emc->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
|
|
@ -1487,7 +1392,7 @@ static int tegra124_emc_probe(struct platform_device *pdev)
|
|||
if (err)
|
||||
return err;
|
||||
|
||||
tegra124_emc_rate_requests_init(emc);
|
||||
tegra_emc_rate_requests_init(&emc->reqs, &pdev->dev);
|
||||
|
||||
if (IS_ENABLED(CONFIG_DEBUG_FS))
|
||||
emc_debugfs_init(&pdev->dev, emc);
|
||||
|
|
|
|||
|
|
@ -154,7 +154,7 @@ static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int tegra186_mc_resume(struct tegra_mc *mc)
|
||||
static void tegra186_mc_resume(struct tegra_mc *mc)
|
||||
{
|
||||
#if IS_ENABLED(CONFIG_IOMMU_API)
|
||||
unsigned int i;
|
||||
|
|
@ -165,8 +165,6 @@ static int tegra186_mc_resume(struct tegra_mc *mc)
|
|||
tegra186_mc_client_sid_override(mc, client, client->sid);
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct tegra_mc_ops tegra186_mc_ops = {
|
||||
|
|
|
|||
|
|
@ -32,6 +32,7 @@
|
|||
#include "../of_memory.h"
|
||||
|
||||
#include "mc.h"
|
||||
#include "tegra-emc-common.h"
|
||||
|
||||
#define EMC_INTSTATUS 0x000
|
||||
#define EMC_INTMASK 0x004
|
||||
|
|
@ -182,18 +183,6 @@ struct emc_timing {
|
|||
u32 data[ARRAY_SIZE(emc_timing_registers)];
|
||||
};
|
||||
|
||||
enum emc_rate_request_type {
|
||||
EMC_RATE_DEVFREQ,
|
||||
EMC_RATE_DEBUG,
|
||||
EMC_RATE_ICC,
|
||||
EMC_RATE_TYPE_MAX,
|
||||
};
|
||||
|
||||
struct emc_rate_request {
|
||||
unsigned long min_rate;
|
||||
unsigned long max_rate;
|
||||
};
|
||||
|
||||
struct tegra_emc {
|
||||
struct device *dev;
|
||||
struct tegra_mc *mc;
|
||||
|
|
@ -212,14 +201,7 @@ struct tegra_emc {
|
|||
unsigned long max_rate;
|
||||
} debugfs;
|
||||
|
||||
/*
|
||||
* There are multiple sources in the EMC driver which could request
|
||||
* a min/max clock rate, these rates are contained in this array.
|
||||
*/
|
||||
struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX];
|
||||
|
||||
/* protect shared rate-change code path */
|
||||
struct mutex rate_lock;
|
||||
struct tegra_emc_rate_requests reqs;
|
||||
|
||||
struct devfreq_simple_ondemand_data ondemand_data;
|
||||
|
||||
|
|
@ -710,83 +692,6 @@ static long emc_round_rate(unsigned long rate,
|
|||
return timing->rate;
|
||||
}
|
||||
|
||||
static void tegra20_emc_rate_requests_init(struct tegra_emc *emc)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < EMC_RATE_TYPE_MAX; i++) {
|
||||
emc->requested_rate[i].min_rate = 0;
|
||||
emc->requested_rate[i].max_rate = ULONG_MAX;
|
||||
}
|
||||
}
|
||||
|
||||
static int emc_request_rate(struct tegra_emc *emc,
|
||||
unsigned long new_min_rate,
|
||||
unsigned long new_max_rate,
|
||||
enum emc_rate_request_type type)
|
||||
{
|
||||
struct emc_rate_request *req = emc->requested_rate;
|
||||
unsigned long min_rate = 0, max_rate = ULONG_MAX;
|
||||
unsigned int i;
|
||||
int err;
|
||||
|
||||
/* select minimum and maximum rates among the requested rates */
|
||||
for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) {
|
||||
if (i == type) {
|
||||
min_rate = max(new_min_rate, min_rate);
|
||||
max_rate = min(new_max_rate, max_rate);
|
||||
} else {
|
||||
min_rate = max(req->min_rate, min_rate);
|
||||
max_rate = min(req->max_rate, max_rate);
|
||||
}
|
||||
}
|
||||
|
||||
if (min_rate > max_rate) {
|
||||
dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n",
|
||||
__func__, type, min_rate, max_rate);
|
||||
return -ERANGE;
|
||||
}
|
||||
|
||||
/*
|
||||
* EMC rate-changes should go via OPP API because it manages voltage
|
||||
* changes.
|
||||
*/
|
||||
err = dev_pm_opp_set_rate(emc->dev, min_rate);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
emc->requested_rate[type].min_rate = new_min_rate;
|
||||
emc->requested_rate[type].max_rate = new_max_rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,
|
||||
enum emc_rate_request_type type)
|
||||
{
|
||||
struct emc_rate_request *req = &emc->requested_rate[type];
|
||||
int ret;
|
||||
|
||||
mutex_lock(&emc->rate_lock);
|
||||
ret = emc_request_rate(emc, rate, req->max_rate, type);
|
||||
mutex_unlock(&emc->rate_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,
|
||||
enum emc_rate_request_type type)
|
||||
{
|
||||
struct emc_rate_request *req = &emc->requested_rate[type];
|
||||
int ret;
|
||||
|
||||
mutex_lock(&emc->rate_lock);
|
||||
ret = emc_request_rate(emc, req->min_rate, rate, type);
|
||||
mutex_unlock(&emc->rate_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* debugfs interface
|
||||
*
|
||||
|
|
@ -857,7 +762,7 @@ static int tegra20_emc_debug_min_rate_set(void *data, u64 rate)
|
|||
if (!tegra20_emc_validate_rate(emc, rate))
|
||||
return -EINVAL;
|
||||
|
||||
err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);
|
||||
err = tegra_emc_set_min_rate(&emc->reqs, rate, TEGRA_EMC_RATE_DEBUG);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
|
|
@ -887,7 +792,7 @@ static int tegra20_emc_debug_max_rate_set(void *data, u64 rate)
|
|||
if (!tegra20_emc_validate_rate(emc, rate))
|
||||
return -EINVAL;
|
||||
|
||||
err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);
|
||||
err = tegra_emc_set_max_rate(&emc->reqs, rate, TEGRA_EMC_RATE_DEBUG);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
|
|
@ -993,7 +898,7 @@ static int emc_icc_set(struct icc_node *src, struct icc_node *dst)
|
|||
do_div(rate, dram_data_bus_width_bytes);
|
||||
rate = min_t(u64, rate, U32_MAX);
|
||||
|
||||
err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);
|
||||
err = tegra_emc_set_min_rate(&emc->reqs, rate, TEGRA_EMC_RATE_ICC);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
|
|
@ -1111,7 +1016,7 @@ static int tegra20_emc_devfreq_target(struct device *dev, unsigned long *freq,
|
|||
rate = dev_pm_opp_get_freq(opp);
|
||||
dev_pm_opp_put(opp);
|
||||
|
||||
return emc_set_min_rate(emc, rate, EMC_RATE_DEVFREQ);
|
||||
return tegra_emc_set_min_rate(&emc->reqs, rate, TEGRA_EMC_RATE_DEVFREQ);
|
||||
}
|
||||
|
||||
static int tegra20_emc_devfreq_get_dev_status(struct device *dev,
|
||||
|
|
@ -1190,7 +1095,6 @@ static int tegra20_emc_probe(struct platform_device *pdev)
|
|||
if (!emc)
|
||||
return -ENOMEM;
|
||||
|
||||
mutex_init(&emc->rate_lock);
|
||||
emc->clk_nb.notifier_call = tegra20_emc_clk_change_notify;
|
||||
emc->dev = &pdev->dev;
|
||||
|
||||
|
|
@ -1228,7 +1132,7 @@ static int tegra20_emc_probe(struct platform_device *pdev)
|
|||
return err;
|
||||
|
||||
platform_set_drvdata(pdev, emc);
|
||||
tegra20_emc_rate_requests_init(emc);
|
||||
tegra_emc_rate_requests_init(&emc->reqs, &pdev->dev);
|
||||
tegra20_emc_debugfs_init(emc);
|
||||
tegra20_emc_interconnect_init(emc);
|
||||
tegra20_emc_devfreq_init(emc);
|
||||
|
|
|
|||
|
|
@ -1125,7 +1125,7 @@ static int tegra234_mc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *pea
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const struct tegra_mc_icc_ops tegra234_mc_icc_ops = {
|
||||
const struct tegra_mc_icc_ops tegra234_mc_icc_ops = {
|
||||
.xlate = tegra_mc_icc_xlate,
|
||||
.aggregate = tegra234_mc_icc_aggregate,
|
||||
.get_bw = tegra234_mc_icc_get_init_bw,
|
||||
|
|
|
|||
391
drivers/memory/tegra/tegra238.c
Normal file
391
drivers/memory/tegra/tegra238.c
Normal file
|
|
@ -0,0 +1,391 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2026, NVIDIA CORPORATION. All rights reserved.
|
||||
*/
|
||||
|
||||
#include <soc/tegra/mc.h>
|
||||
|
||||
#include <dt-bindings/memory/tegra234-mc.h>
|
||||
#include <dt-bindings/memory/nvidia,tegra238-mc.h>
|
||||
#include <linux/interconnect.h>
|
||||
#include <linux/tegra-icc.h>
|
||||
|
||||
#include <soc/tegra/bpmp.h>
|
||||
#include "mc.h"
|
||||
|
||||
static const struct tegra_mc_client tegra238_mc_clients[] = {
|
||||
{
|
||||
.id = TEGRA234_MEMORY_CLIENT_HDAR,
|
||||
.name = "hdar",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_HDA,
|
||||
.type = TEGRA_ICC_ISO_AUDIO,
|
||||
.sid = TEGRA238_SID_HDA,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0xa8,
|
||||
.security = 0xac,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_HDAW,
|
||||
.name = "hdaw",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_HDA,
|
||||
.type = TEGRA_ICC_ISO_AUDIO,
|
||||
.sid = TEGRA238_SID_HDA,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x1a8,
|
||||
.security = 0x1ac,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_SDMMCRAB,
|
||||
.name = "sdmmcrab",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_SDMMC_4,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.sid = TEGRA238_SID_SDMMC4A,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x318,
|
||||
.security = 0x31c,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_SDMMCWAB,
|
||||
.name = "sdmmcwab",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_SDMMC_4,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.sid = TEGRA238_SID_SDMMC4A,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x338,
|
||||
.security = 0x33c,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_APER,
|
||||
.name = "aper",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_APE,
|
||||
.type = TEGRA_ICC_ISO_AUDIO,
|
||||
.sid = TEGRA238_SID_ISO_APE0,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x3d0,
|
||||
.security = 0x3d4,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_APEW,
|
||||
.name = "apew",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_APE,
|
||||
.type = TEGRA_ICC_ISO_AUDIO,
|
||||
.sid = TEGRA238_SID_ISO_APE0,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x3d8,
|
||||
.security = 0x3dc,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR,
|
||||
.name = "nvdisplayr",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
|
||||
.type = TEGRA_ICC_ISO_DISPLAY,
|
||||
.sid = TEGRA238_SID_ISO_NVDISPLAY,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x490,
|
||||
.security = 0x494,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1,
|
||||
.name = "nvdisplayr1",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
|
||||
.type = TEGRA_ICC_ISO_DISPLAY,
|
||||
.sid = TEGRA238_SID_ISO_NVDISPLAY,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x508,
|
||||
.security = 0x50c,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_BPMPR,
|
||||
.name = "bpmpr",
|
||||
.sid = TEGRA238_SID_BPMP,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x498,
|
||||
.security = 0x49c,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_BPMPW,
|
||||
.name = "bpmpw",
|
||||
.sid = TEGRA238_SID_BPMP,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x4a0,
|
||||
.security = 0x4a4,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_BPMPDMAR,
|
||||
.name = "bpmpdmar",
|
||||
.sid = TEGRA238_SID_BPMP,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x4a8,
|
||||
.security = 0x4ac,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_BPMPDMAW,
|
||||
.name = "bpmpdmaw",
|
||||
.sid = TEGRA238_SID_BPMP,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x4b0,
|
||||
.security = 0x4b4,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_APEDMAR,
|
||||
.name = "apedmar",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_APEDMA,
|
||||
.type = TEGRA_ICC_ISO_AUDIO,
|
||||
.sid = TEGRA238_SID_ISO_APE1,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x4f8,
|
||||
.security = 0x4fc,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_APEDMAW,
|
||||
.name = "apedmaw",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_APEDMA,
|
||||
.type = TEGRA_ICC_ISO_AUDIO,
|
||||
.sid = TEGRA238_SID_ISO_APE1,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x500,
|
||||
.security = 0x504,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_VICSRD,
|
||||
.name = "vicsrd",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_VIC,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.sid = TEGRA238_SID_VIC,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x360,
|
||||
.security = 0x364,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_VICSWR,
|
||||
.name = "vicswr",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_VIC,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.sid = TEGRA238_SID_VIC,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x368,
|
||||
.security = 0x36c,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_NVDECSRD,
|
||||
.name = "nvdecsrd",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_NVDEC,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.sid = TEGRA238_SID_NVDEC,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x3c0,
|
||||
.security = 0x3c4,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_NVDECSWR,
|
||||
.name = "nvdecswr",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_NVDEC,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.sid = TEGRA238_SID_NVDEC,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x3c8,
|
||||
.security = 0x3cc,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_NVENCSRD,
|
||||
.name = "nvencsrd",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_NVENC,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.sid = TEGRA238_SID_NVENC,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0xe0,
|
||||
.security = 0xe4,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_NVENCSWR,
|
||||
.name = "nvencswr",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_NVENC,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.sid = TEGRA238_SID_NVENC,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x158,
|
||||
.security = 0x15c,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_PCIE0R,
|
||||
.name = "pcie0r",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_PCIE_0,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.sid = TEGRA238_SID_PCIE0,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x6c0,
|
||||
.security = 0x6c4,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_PCIE0W,
|
||||
.name = "pcie0w",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_PCIE_0,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.sid = TEGRA238_SID_PCIE0,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x6c8,
|
||||
.security = 0x6cc,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_PCIE1R,
|
||||
.name = "pcie1r",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_PCIE_1,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.sid = TEGRA238_SID_PCIE1,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x6d0,
|
||||
.security = 0x6d4,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_PCIE1W,
|
||||
.name = "pcie1w",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_PCIE_1,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.sid = TEGRA238_SID_PCIE1,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x6d8,
|
||||
.security = 0x6dc,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_PCIE2AR,
|
||||
.name = "pcie2ar",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_PCIE_2,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.sid = TEGRA238_SID_PCIE2,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x6e0,
|
||||
.security = 0x6e4,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_PCIE2AW,
|
||||
.name = "pcie2aw",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_PCIE_2,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.sid = TEGRA238_SID_PCIE2,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x6e8,
|
||||
.security = 0x6ec,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_PCIE3R,
|
||||
.name = "pcie3r",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_PCIE_3,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.sid = TEGRA238_SID_PCIE3,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x6f0,
|
||||
.security = 0x6f4,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_PCIE3W,
|
||||
.name = "pcie3w",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_PCIE_3,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.sid = TEGRA238_SID_PCIE3,
|
||||
.regs = {
|
||||
.sid = {
|
||||
.override = 0x6f8,
|
||||
.security = 0x6fc,
|
||||
},
|
||||
},
|
||||
}, {
|
||||
.id = TEGRA_ICC_MC_CPU_CLUSTER0,
|
||||
.name = "sw_cluster0",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER0,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_NVL1R,
|
||||
.name = "nvl1r",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_GPU,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA234_MEMORY_CLIENT_NVL1W,
|
||||
.name = "nvl1w",
|
||||
.bpmp_id = TEGRA_ICC_BPMP_GPU,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}
|
||||
};
|
||||
|
||||
static const struct tegra_mc_intmask tegra238_mc_intmasks[] = {
|
||||
{
|
||||
.reg = MC_INTMASK,
|
||||
.mask = MC_INT_DECERR_ROUTE_SANITY | MC_INT_DECERR_GENERALIZED_CARVEOUT |
|
||||
MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
|
||||
MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
|
||||
},
|
||||
};
|
||||
|
||||
const struct tegra_mc_soc tegra238_mc_soc = {
|
||||
.num_clients = ARRAY_SIZE(tegra238_mc_clients),
|
||||
.clients = tegra238_mc_clients,
|
||||
.num_address_bits = 40,
|
||||
.num_channels = 8,
|
||||
.client_id_mask = 0x1ff,
|
||||
.intmasks = tegra238_mc_intmasks,
|
||||
.num_intmasks = ARRAY_SIZE(tegra238_mc_intmasks),
|
||||
.has_addr_hi_reg = true,
|
||||
.ops = &tegra186_mc_ops,
|
||||
.icc_ops = &tegra234_mc_icc_ops,
|
||||
.ch_intmask = 0x0000ff00,
|
||||
.global_intstatus_channel_shift = 8,
|
||||
.num_carveouts = 32,
|
||||
.regs = &tegra20_mc_regs,
|
||||
.handle_irq = tegra30_mc_irq_handlers,
|
||||
.num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers),
|
||||
.mc_addr_hi_mask = 0x3,
|
||||
.mc_err_status_type_mask = (0x7 << 28),
|
||||
};
|
||||
|
|
@ -21,45 +21,62 @@
|
|||
*/
|
||||
static const struct tegra_mc_client tegra264_mc_clients[] = {
|
||||
{
|
||||
.id = TEGRA264_MEMORY_CLIENT_HDAR,
|
||||
.name = "hdar",
|
||||
.bpmp_id = TEGRA264_BWMGR_HDA,
|
||||
.type = TEGRA_ICC_ISO_AUDIO,
|
||||
.id = TEGRA264_MEMORY_CLIENT_PTCR,
|
||||
.name = "ptcr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_HDAW,
|
||||
.name = "hdaw",
|
||||
.bpmp_id = TEGRA264_BWMGR_HDA,
|
||||
.type = TEGRA_ICC_ISO_AUDIO,
|
||||
.id = TEGRA264_MEMORY_CLIENT_HOST1XR,
|
||||
.name = "host1xr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MGBE0R,
|
||||
.name = "mgbe0r",
|
||||
.bpmp_id = TEGRA264_BWMGR_EQOS,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.id = TEGRA264_MEMORY_CLIENT_MPCORER,
|
||||
.name = "mpcorer",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MGBE0W,
|
||||
.name = "mgbe0w",
|
||||
.bpmp_id = TEGRA264_BWMGR_EQOS,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.id = TEGRA264_MEMORY_CLIENT_PSCR,
|
||||
.name = "pscr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MGBE1R,
|
||||
.name = "mgbe1r",
|
||||
.bpmp_id = TEGRA264_BWMGR_EQOS,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.id = TEGRA264_MEMORY_CLIENT_PSCW,
|
||||
.name = "pscw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MGBE1W,
|
||||
.name = "mgbe1w",
|
||||
.bpmp_id = TEGRA264_BWMGR_EQOS,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.id = TEGRA264_MEMORY_CLIENT_ISP0R,
|
||||
.name = "isp0r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SDMMC0R,
|
||||
.name = "sdmmc0r",
|
||||
.bpmp_id = TEGRA264_BWMGR_SDMMC_1,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.id = TEGRA264_MEMORY_CLIENT_MPCOREW,
|
||||
.name = "mpcorew",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SDMMC0W,
|
||||
.name = "sdmmc0w",
|
||||
.bpmp_id = TEGRA264_BWMGR_SDMMC_1,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
.id = TEGRA264_MEMORY_CLIENT_ISP0W,
|
||||
.name = "isp0w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_ISP1W,
|
||||
.name = "isp1w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_ISPFALCONR,
|
||||
.name = "ispfalconr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_ISPFALCONW,
|
||||
.name = "ispfalconw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MGBE2R,
|
||||
.name = "mgbe2r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_OFAR2MC,
|
||||
.name = "ofar2mc",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_OFAW2MC,
|
||||
.name = "ofaw2mc",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MGBE2W,
|
||||
.name = "mgbe2w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MGBE3R,
|
||||
.name = "mgbe3r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MGBE3W,
|
||||
.name = "mgbe3w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SEU1RD,
|
||||
.name = "seu1rd",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SEU1WR,
|
||||
.name = "seu1wr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_VICR,
|
||||
.name = "vicr",
|
||||
|
|
@ -70,6 +87,15 @@ static const struct tegra_mc_client tegra264_mc_clients[] = {
|
|||
.name = "vicw",
|
||||
.bpmp_id = TEGRA264_BWMGR_VIC,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_VIW,
|
||||
.name = "viw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_XSPI0R,
|
||||
.name = "xspi0r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_XSPI0W,
|
||||
.name = "xspi0w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_APER,
|
||||
.name = "aper",
|
||||
|
|
@ -80,6 +106,48 @@ static const struct tegra_mc_client tegra264_mc_clients[] = {
|
|||
.name = "apew",
|
||||
.bpmp_id = TEGRA264_BWMGR_APE,
|
||||
.type = TEGRA_ICC_ISO_AUDIO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SER,
|
||||
.name = "ser",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SEW,
|
||||
.name = "sew",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_AXIAPR,
|
||||
.name = "axiapr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_AXIAPW,
|
||||
.name = "axiapw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_ETRR,
|
||||
.name = "etrr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_ETRW,
|
||||
.name = "etrw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_TSECR,
|
||||
.name = "tsecr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_TSECW,
|
||||
.name = "tsecw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_BPMPR,
|
||||
.name = "bpmpr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_BPMPW,
|
||||
.name = "bpmpw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_AONR,
|
||||
.name = "aonr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_AONW,
|
||||
.name = "aonw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_GPCDMAR,
|
||||
.name = "gpcdmar",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_GPCDMAW,
|
||||
.name = "gpcdmaw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_APEDMAR,
|
||||
.name = "apedmar",
|
||||
|
|
@ -90,6 +158,36 @@ static const struct tegra_mc_client tegra264_mc_clients[] = {
|
|||
.name = "apedmaw",
|
||||
.bpmp_id = TEGRA264_BWMGR_APEDMA,
|
||||
.type = TEGRA_ICC_ISO_AUDIO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MIU0R,
|
||||
.name = "miu0r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MIU0W,
|
||||
.name = "miu0w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MIU1R,
|
||||
.name = "miu1r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MIU1W,
|
||||
.name = "miu1w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MIU2R,
|
||||
.name = "miu2r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MIU2W,
|
||||
.name = "miu2w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MIU3R,
|
||||
.name = "miu3r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MIU3W,
|
||||
.name = "miu3w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MIU4R,
|
||||
.name = "miu4r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MIU4W,
|
||||
.name = "miu4w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_VIFALCONR,
|
||||
.name = "vifalconr",
|
||||
|
|
@ -110,6 +208,12 @@ static const struct tegra_mc_client tegra264_mc_clients[] = {
|
|||
.name = "rcew",
|
||||
.bpmp_id = TEGRA264_BWMGR_RCE,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_NVENC1SRD2MC,
|
||||
.name = "nvenc1srd2mc",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_NVENC1SWR2MC,
|
||||
.name = "nvenc1swr2mc",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_PCIE0W,
|
||||
.name = "pcie0w",
|
||||
|
|
@ -185,6 +289,402 @@ static const struct tegra_mc_client tegra264_mc_clients[] = {
|
|||
.name = "nvdecswr2mc",
|
||||
.bpmp_id = TEGRA264_BWMGR_NVDEC,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MIU5R,
|
||||
.name = "miu5r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MIU5W,
|
||||
.name = "miu5w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MIU6W,
|
||||
.name = "miu6w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_RISTR,
|
||||
.name = "ristr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_RISTW,
|
||||
.name = "ristw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_OESPR,
|
||||
.name = "oespr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_OESPW,
|
||||
.name = "oespw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MIU7W,
|
||||
.name = "miu7w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MIU8R,
|
||||
.name = "miu8r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MIU8W,
|
||||
.name = "miu8w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MIU9R,
|
||||
.name = "miu9r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MIU9W,
|
||||
.name = "miu9w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_PMA0AWR,
|
||||
.name = "pma0awr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_NVJPG1SRD2MC,
|
||||
.name = "nvjpg1srd2mc",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_NVJPG1SWR2MC,
|
||||
.name = "nvjpg1swr2mc",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU0CTWR,
|
||||
.name = "smmu0ctwr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU0CMDQVR,
|
||||
.name = "smmu0cmdqvr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU0CMDQVW,
|
||||
.name = "smmu0cmdqvw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU0EVNTQW,
|
||||
.name = "smmu0evntqw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU1PTWR,
|
||||
.name = "smmu1ptwr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU1CTWR,
|
||||
.name = "smmu1ctwr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU1CMDQVR,
|
||||
.name = "smmu1cmdqvr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU1CMDQVW,
|
||||
.name = "smmu1cmdqvw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU1EVNTQW,
|
||||
.name = "smmu1evntqw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU2PTWR,
|
||||
.name = "smmu2ptwr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU2CTWR,
|
||||
.name = "smmu2ctwr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU2CMDQVR,
|
||||
.name = "smmu2cmdqvr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU2CMDQVW,
|
||||
.name = "smmu2cmdqvw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU2EVNTQW,
|
||||
.name = "smmu2evntqw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU0CMDQR,
|
||||
.name = "smmu0cmdqr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU1CMDQR,
|
||||
.name = "smmu1cmdqr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU2CMDQR,
|
||||
.name = "smmu2cmdqr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_APE1R,
|
||||
.name = "ape1r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_APE1W,
|
||||
.name = "ape1w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_UFSR,
|
||||
.name = "ufsr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_UFSW,
|
||||
.name = "ufsw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_XUSB_DEVR,
|
||||
.name = "xusb_devr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_XUSB_DEVW,
|
||||
.name = "xusb_devw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_XUSB_DEV1R,
|
||||
.name = "xusb_dev1r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_XUSB_DEV2W,
|
||||
.name = "xusb_dev2w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_XUSB_DEV3R,
|
||||
.name = "xusb_dev3r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_XUSB_DEV3W,
|
||||
.name = "xusb_dev3w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_XUSB_DEV4R,
|
||||
.name = "xusb_dev4r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_XUSB_DEV4W,
|
||||
.name = "xusb_dev4w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_XUSB_DEV5R,
|
||||
.name = "xusb_dev5r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_XUSB_DEV5W,
|
||||
.name = "xusb_dev5w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_DCER,
|
||||
.name = "dcer",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_DCEW,
|
||||
.name = "dcew",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_HDAR,
|
||||
.name = "hdar",
|
||||
.bpmp_id = TEGRA264_BWMGR_HDA,
|
||||
.type = TEGRA_ICC_ISO_AUDIO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_HDAW,
|
||||
.name = "hdaw",
|
||||
.bpmp_id = TEGRA264_BWMGR_HDA,
|
||||
.type = TEGRA_ICC_ISO_AUDIO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_DISPNISOR,
|
||||
.name = "dispnisor",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_DISPNISOW,
|
||||
.name = "dispnisow",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_XUSB_DEV1W,
|
||||
.name = "xusb_dev1w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_XUSB_DEV2R,
|
||||
.name = "xusb_dev2r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_DISPR,
|
||||
.name = "dispr",
|
||||
.bpmp_id = TEGRA264_BWMGR_DISPLAY,
|
||||
.type = TEGRA_ICC_ISO_DISPLAY,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MSSSEQR,
|
||||
.name = "mssseqr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MSSSEQW,
|
||||
.name = "mssseqw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU3PTWR,
|
||||
.name = "smmu3ptwr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU3CTWR,
|
||||
.name = "smmu3ctwr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU3CMDQVR,
|
||||
.name = "smmu3cmdqvr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU3CMDQVW,
|
||||
.name = "smmu3cmdqvw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU3EVNTQW,
|
||||
.name = "smmu3evntqw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU3CMDQR,
|
||||
.name = "smmu3cmdqr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU4PTWR,
|
||||
.name = "smmu4ptwr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU4CTWR,
|
||||
.name = "smmu4ctwr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU4CMDQVR,
|
||||
.name = "smmu4cmdqvr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU4CMDQVW,
|
||||
.name = "smmu4cmdqvw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU4EVNTQW,
|
||||
.name = "smmu4evntqw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SMMU4CMDQR,
|
||||
.name = "smmu4cmdqr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MGBE0R,
|
||||
.name = "mgbe0r",
|
||||
.bpmp_id = TEGRA264_BWMGR_EQOS,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MGBE0W,
|
||||
.name = "mgbe0w",
|
||||
.bpmp_id = TEGRA264_BWMGR_EQOS,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MGBE1R,
|
||||
.name = "mgbe1r",
|
||||
.bpmp_id = TEGRA264_BWMGR_EQOS,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_MGBE1W,
|
||||
.name = "mgbe1w",
|
||||
.bpmp_id = TEGRA264_BWMGR_EQOS,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_VI1W,
|
||||
.name = "vi1w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_VIFALCON1R,
|
||||
.name = "vifalcon1r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_VIFALCON1W,
|
||||
.name = "vifalcon1w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_ISPFALCON1R,
|
||||
.name = "ispfalcon1r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_ISPFALCON1W,
|
||||
.name = "ispfalcon1w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_RCE1R,
|
||||
.name = "rce1r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_RCE1W,
|
||||
.name = "rce1w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SEU2R,
|
||||
.name = "seu2r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SEU2W,
|
||||
.name = "seu2w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SEU3R,
|
||||
.name = "seu3r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SEU3W,
|
||||
.name = "seu3w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_PVA0R,
|
||||
.name = "pva0r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_PVA0W,
|
||||
.name = "pva0w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_PVA1R,
|
||||
.name = "pva1r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_PVA1W,
|
||||
.name = "pva1w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_PVA2R,
|
||||
.name = "pva2r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_PVA2W,
|
||||
.name = "pva2w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_ISP3W,
|
||||
.name = "isp3w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_ISP2R,
|
||||
.name = "isp2r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_ISP2W,
|
||||
.name = "isp2w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_EQOSR,
|
||||
.name = "eqosr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_EQOSW,
|
||||
.name = "eqosw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_FSI0R,
|
||||
.name = "fsi0r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_FSI0W,
|
||||
.name = "fsi0w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_FSI1R,
|
||||
.name = "fsi1r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_FSI1W,
|
||||
.name = "fsi1w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SDMMC0R,
|
||||
.name = "sdmmc0r",
|
||||
.bpmp_id = TEGRA264_BWMGR_SDMMC_1,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SDMMC0W,
|
||||
.name = "sdmmc0w",
|
||||
.bpmp_id = TEGRA264_BWMGR_SDMMC_1,
|
||||
.type = TEGRA_ICC_NISO,
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SBR,
|
||||
.name = "sbr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SBW,
|
||||
.name = "sbw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_HSS_MIU0R,
|
||||
.name = "hss_miu0r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_HSS_MIU0W,
|
||||
.name = "hss_miu0w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_HSS_MIU1R,
|
||||
.name = "hss_miu1r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_HSS_MIU1W,
|
||||
.name = "hss_miu1w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_HSS_MIU2R,
|
||||
.name = "hss_miu2r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_HSS_MIU2W,
|
||||
.name = "hss_miu2w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_HSS_MIU3R,
|
||||
.name = "hss_miu3r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_HSS_MIU3W,
|
||||
.name = "hss_miu3w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_HSS_MIU4R,
|
||||
.name = "hss_miu4r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_HSS_MIU4W,
|
||||
.name = "hss_miu4w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_HSS_MIU5R,
|
||||
.name = "hss_miu5r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_HSS_MIU5W,
|
||||
.name = "hss_miu5w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_HSS_MIU6R,
|
||||
.name = "hss_miu6r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_HSS_MIU6W,
|
||||
.name = "hss_miu6w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_HSS_MIU7R,
|
||||
.name = "hss_miu7r",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_HSS_MIU7W,
|
||||
.name = "hss_miu7w",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_GMMUR2MC,
|
||||
.name = "gmmur2mc",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_UCFELAR,
|
||||
.name = "ucfelar",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_UCFELAW,
|
||||
.name = "ucfelaw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SLCR,
|
||||
.name = "slcr",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_SLCW,
|
||||
.name = "slcw",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_REMOTER,
|
||||
.name = "remoter",
|
||||
}, {
|
||||
.id = TEGRA264_MEMORY_CLIENT_REMOTEW,
|
||||
.name = "remotew",
|
||||
},
|
||||
};
|
||||
|
||||
|
|
@ -262,6 +762,10 @@ static int tegra264_mc_icc_set(struct icc_node *src, struct icc_node *dst)
|
|||
return -ENOENT;
|
||||
}
|
||||
|
||||
/* Skip forwarding bw requests to BPMP from clients without bpmp_id/type. */
|
||||
if (pclient->type == TEGRA_ICC_NONE || !pclient->bpmp_id)
|
||||
return 0;
|
||||
|
||||
if (pclient->type == TEGRA_ICC_NISO)
|
||||
bwmgr_req.bwmgr_calc_set_req.niso_bw = src->avg_bw;
|
||||
else
|
||||
|
|
|
|||
|
|
@ -36,6 +36,7 @@
|
|||
#include "../of_memory.h"
|
||||
|
||||
#include "mc.h"
|
||||
#include "tegra-emc-common.h"
|
||||
|
||||
#define EMC_INTSTATUS 0x000
|
||||
#define EMC_INTMASK 0x004
|
||||
|
|
@ -341,17 +342,6 @@ struct emc_timing {
|
|||
bool emc_cfg_dyn_self_ref;
|
||||
};
|
||||
|
||||
enum emc_rate_request_type {
|
||||
EMC_RATE_DEBUG,
|
||||
EMC_RATE_ICC,
|
||||
EMC_RATE_TYPE_MAX,
|
||||
};
|
||||
|
||||
struct emc_rate_request {
|
||||
unsigned long min_rate;
|
||||
unsigned long max_rate;
|
||||
};
|
||||
|
||||
struct tegra_emc {
|
||||
struct device *dev;
|
||||
struct tegra_mc *mc;
|
||||
|
|
@ -383,14 +373,7 @@ struct tegra_emc {
|
|||
unsigned long max_rate;
|
||||
} debugfs;
|
||||
|
||||
/*
|
||||
* There are multiple sources in the EMC driver which could request
|
||||
* a min/max clock rate, these rates are contained in this array.
|
||||
*/
|
||||
struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX];
|
||||
|
||||
/* protect shared rate-change code path */
|
||||
struct mutex rate_lock;
|
||||
struct tegra_emc_rate_requests reqs;
|
||||
|
||||
bool mrr_error;
|
||||
};
|
||||
|
|
@ -1228,83 +1211,6 @@ static long emc_round_rate(unsigned long rate,
|
|||
return timing->rate;
|
||||
}
|
||||
|
||||
static void tegra30_emc_rate_requests_init(struct tegra_emc *emc)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < EMC_RATE_TYPE_MAX; i++) {
|
||||
emc->requested_rate[i].min_rate = 0;
|
||||
emc->requested_rate[i].max_rate = ULONG_MAX;
|
||||
}
|
||||
}
|
||||
|
||||
static int emc_request_rate(struct tegra_emc *emc,
|
||||
unsigned long new_min_rate,
|
||||
unsigned long new_max_rate,
|
||||
enum emc_rate_request_type type)
|
||||
{
|
||||
struct emc_rate_request *req = emc->requested_rate;
|
||||
unsigned long min_rate = 0, max_rate = ULONG_MAX;
|
||||
unsigned int i;
|
||||
int err;
|
||||
|
||||
/* select minimum and maximum rates among the requested rates */
|
||||
for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) {
|
||||
if (i == type) {
|
||||
min_rate = max(new_min_rate, min_rate);
|
||||
max_rate = min(new_max_rate, max_rate);
|
||||
} else {
|
||||
min_rate = max(req->min_rate, min_rate);
|
||||
max_rate = min(req->max_rate, max_rate);
|
||||
}
|
||||
}
|
||||
|
||||
if (min_rate > max_rate) {
|
||||
dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n",
|
||||
__func__, type, min_rate, max_rate);
|
||||
return -ERANGE;
|
||||
}
|
||||
|
||||
/*
|
||||
* EMC rate-changes should go via OPP API because it manages voltage
|
||||
* changes.
|
||||
*/
|
||||
err = dev_pm_opp_set_rate(emc->dev, min_rate);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
emc->requested_rate[type].min_rate = new_min_rate;
|
||||
emc->requested_rate[type].max_rate = new_max_rate;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,
|
||||
enum emc_rate_request_type type)
|
||||
{
|
||||
struct emc_rate_request *req = &emc->requested_rate[type];
|
||||
int ret;
|
||||
|
||||
mutex_lock(&emc->rate_lock);
|
||||
ret = emc_request_rate(emc, rate, req->max_rate, type);
|
||||
mutex_unlock(&emc->rate_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,
|
||||
enum emc_rate_request_type type)
|
||||
{
|
||||
struct emc_rate_request *req = &emc->requested_rate[type];
|
||||
int ret;
|
||||
|
||||
mutex_lock(&emc->rate_lock);
|
||||
ret = emc_request_rate(emc, req->min_rate, rate, type);
|
||||
mutex_unlock(&emc->rate_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* debugfs interface
|
||||
*
|
||||
|
|
@ -1375,7 +1281,7 @@ static int tegra30_emc_debug_min_rate_set(void *data, u64 rate)
|
|||
if (!tegra30_emc_validate_rate(emc, rate))
|
||||
return -EINVAL;
|
||||
|
||||
err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);
|
||||
err = tegra_emc_set_min_rate(&emc->reqs, rate, TEGRA_EMC_RATE_DEBUG);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
|
|
@ -1405,7 +1311,7 @@ static int tegra30_emc_debug_max_rate_set(void *data, u64 rate)
|
|||
if (!tegra30_emc_validate_rate(emc, rate))
|
||||
return -EINVAL;
|
||||
|
||||
err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);
|
||||
err = tegra_emc_set_max_rate(&emc->reqs, rate, TEGRA_EMC_RATE_DEBUG);
|
||||
if (err < 0)
|
||||
return err;
|
||||
|
||||
|
|
@ -1511,7 +1417,7 @@ static int emc_icc_set(struct icc_node *src, struct icc_node *dst)
|
|||
do_div(rate, ddr * dram_data_bus_width_bytes);
|
||||
rate = min_t(u64, rate, U32_MAX);
|
||||
|
||||
err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);
|
||||
err = tegra_emc_set_min_rate(&emc->reqs, rate, TEGRA_EMC_RATE_ICC);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
|
|
@ -1622,7 +1528,6 @@ static int tegra30_emc_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(emc->mc))
|
||||
return PTR_ERR(emc->mc);
|
||||
|
||||
mutex_init(&emc->rate_lock);
|
||||
emc->clk_nb.notifier_call = emc_clk_change_notify;
|
||||
emc->dev = &pdev->dev;
|
||||
|
||||
|
|
@ -1664,7 +1569,7 @@ static int tegra30_emc_probe(struct platform_device *pdev)
|
|||
return err;
|
||||
|
||||
platform_set_drvdata(pdev, emc);
|
||||
tegra30_emc_rate_requests_init(emc);
|
||||
tegra_emc_rate_requests_init(&emc->reqs, &pdev->dev);
|
||||
tegra30_emc_debugfs_init(emc);
|
||||
tegra30_emc_interconnect_init(emc);
|
||||
|
||||
|
|
|
|||
74
include/dt-bindings/memory/nvidia,tegra238-mc.h
Normal file
74
include/dt-bindings/memory/nvidia,tegra238-mc.h
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
|
||||
/* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */
|
||||
|
||||
#ifndef DT_BINDINGS_MEMORY_TEGRA238_MC_H
|
||||
#define DT_BINDINGS_MEMORY_TEGRA238_MC_H
|
||||
|
||||
/* special clients */
|
||||
#define TEGRA238_SID_INVALID 0x0
|
||||
#define TEGRA238_SID_PASSTHROUGH 0x7f
|
||||
|
||||
/* ISO stream IDs */
|
||||
#define TEGRA238_SID_ISO_NVDISPLAY 0x1
|
||||
#define TEGRA238_SID_ISO_APE0 0x2
|
||||
#define TEGRA238_SID_ISO_APE1 0x3
|
||||
|
||||
/* NISO stream IDs */
|
||||
#define TEGRA238_SID_AON 0x1
|
||||
#define TEGRA238_SID_BPMP 0x2
|
||||
#define TEGRA238_SID_ETR 0x3
|
||||
#define TEGRA238_SID_FDE 0x4
|
||||
#define TEGRA238_SID_HC 0x5
|
||||
#define TEGRA238_SID_HDA 0x6
|
||||
#define TEGRA238_SID_NVDEC 0x7
|
||||
#define TEGRA238_SID_NVDISPLAY 0x8
|
||||
#define TEGRA238_SID_NVENC 0x9
|
||||
#define TEGRA238_SID_OFA 0xa
|
||||
#define TEGRA238_SID_PCIE0 0xb
|
||||
#define TEGRA238_SID_PCIE1 0xc
|
||||
#define TEGRA238_SID_PCIE2 0xd
|
||||
#define TEGRA238_SID_PCIE3 0xe
|
||||
#define TEGRA238_SID_HWMP_PMA 0xf
|
||||
#define TEGRA238_SID_PSC 0x10
|
||||
#define TEGRA238_SID_SDMMC1A 0x11
|
||||
#define TEGRA238_SID_SDMMC4A 0x12
|
||||
#define TEGRA238_SID_SES_SE0 0x13
|
||||
#define TEGRA238_SID_SES_SE1 0x14
|
||||
#define TEGRA238_SID_SES_SE2 0x15
|
||||
#define TEGRA238_SID_SEU1_SE0 0x16
|
||||
#define TEGRA238_SID_SEU1_SE1 0x17
|
||||
#define TEGRA238_SID_SEU1_SE2 0x18
|
||||
#define TEGRA238_SID_TSEC 0x19
|
||||
#define TEGRA238_SID_UFSHC 0x1a
|
||||
#define TEGRA238_SID_VIC 0x1b
|
||||
#define TEGRA238_SID_XUSB_HOST 0x1c
|
||||
#define TEGRA238_SID_XUSB_DEV 0x1d
|
||||
#define TEGRA238_SID_GPCDMA_0 0x1e
|
||||
#define TEGRA238_SID_SMMU_TEST 0x1f
|
||||
|
||||
/* Host1x virtualization clients. */
|
||||
#define TEGRA238_SID_HOST1X_CTX0 0x20
|
||||
#define TEGRA238_SID_HOST1X_CTX1 0x21
|
||||
#define TEGRA238_SID_HOST1X_CTX2 0x22
|
||||
#define TEGRA238_SID_HOST1X_CTX3 0x23
|
||||
#define TEGRA238_SID_HOST1X_CTX4 0x24
|
||||
#define TEGRA238_SID_HOST1X_CTX5 0x25
|
||||
#define TEGRA238_SID_HOST1X_CTX6 0x26
|
||||
#define TEGRA238_SID_HOST1X_CTX7 0x27
|
||||
|
||||
#define TEGRA238_SID_XUSB_VF0 0x28
|
||||
#define TEGRA238_SID_XUSB_VF1 0x29
|
||||
#define TEGRA238_SID_XUSB_VF2 0x2a
|
||||
#define TEGRA238_SID_XUSB_VF3 0x2b
|
||||
|
||||
/* Host1x command buffers */
|
||||
#define TEGRA238_SID_HC_VM0 0x2c
|
||||
#define TEGRA238_SID_HC_VM1 0x2d
|
||||
#define TEGRA238_SID_HC_VM2 0x2e
|
||||
#define TEGRA238_SID_HC_VM3 0x2f
|
||||
#define TEGRA238_SID_HC_VM4 0x30
|
||||
#define TEGRA238_SID_HC_VM5 0x31
|
||||
#define TEGRA238_SID_HC_VM6 0x32
|
||||
#define TEGRA238_SID_HC_VM7 0x33
|
||||
|
||||
#endif
|
||||
|
|
@ -58,24 +58,108 @@
|
|||
* memory client IDs
|
||||
*/
|
||||
|
||||
/* PTW read client mapped to SOC SMMU0 */
|
||||
#define TEGRA264_MEMORY_CLIENT_PTCR 0x00
|
||||
/* HOST1X read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_HOST1XR 0x16
|
||||
#define TEGRA264_MEMORY_CLIENT_MPCORER 0x27
|
||||
/* Platform security (PSC) Read clients */
|
||||
#define TEGRA264_MEMORY_CLIENT_PSCR 0x33
|
||||
/* PSC Write clients */
|
||||
#define TEGRA264_MEMORY_CLIENT_PSCW 0x34
|
||||
/* ISP0 Read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_ISP0R 0x37
|
||||
#define TEGRA264_MEMORY_CLIENT_MPCOREW 0x39
|
||||
/* ISP0 Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_ISP0W 0x44
|
||||
/* ISP1 Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_ISP1W 0x45
|
||||
/* ISP FALCON Read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_ISPFALCONR 0x47
|
||||
/* ISP FALCON Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_ISPFALCONW 0x4f
|
||||
/* MGBE2 Read mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_MGBE2R 0x5c
|
||||
#define TEGRA264_MEMORY_CLIENT_OFAR2MC 0x5d
|
||||
#define TEGRA264_MEMORY_CLIENT_OFAW2MC 0x5e
|
||||
/* MGBE2 Write mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_MGBE2W 0x5f
|
||||
/* MGBE3 Read mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_MGBE3R 0x61
|
||||
/* MGBE3 Write mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_MGBE3W 0x65
|
||||
/* SEU1 Memory Read Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_SEU1RD 0x68
|
||||
/* SEU1 Memory Write Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_SEU1WR 0x69
|
||||
/* VIC read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_VICR 0x6c
|
||||
/* VIC Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_VICW 0x6d
|
||||
/* VI R5 Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_VIW 0x72
|
||||
/* QSPI Read Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_XSPI0R 0x75
|
||||
/* QSPI Write Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_XSPI0W 0x76
|
||||
#define TEGRA264_MEMORY_CLIENT_NVDECSRD2MC 0x78
|
||||
#define TEGRA264_MEMORY_CLIENT_NVDECSWR2MC 0x79
|
||||
/* Audio processor(APE) Read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_APER 0x7a
|
||||
/* Audio processor(APE) Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_APEW 0x7b
|
||||
/* SEU0 read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_SER 0x80
|
||||
/* SEU0 write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_SEW 0x81
|
||||
/* AXI AP and DFD/Coresight1-AUX0/1 Read clients both share the same interface on MSS */
|
||||
#define TEGRA264_MEMORY_CLIENT_AXIAPR 0x82
|
||||
/* AXI AP and DFD/Coresight1-AUX0/1 Write clients both share the same interface on MSS */
|
||||
#define TEGRA264_MEMORY_CLIENT_AXIAPW 0x83
|
||||
/* ETR or DFD/Coresight0 Read Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_ETRR 0x84
|
||||
/* ETR or DFD/Coresight0 Write Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_ETRW 0x85
|
||||
/* Security(tsec) Read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_TSECR 0x86
|
||||
/* Security(tsec) Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_TSECW 0x87
|
||||
/* BPMP read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_BPMPR 0x93
|
||||
/* BPMP write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_BPMPW 0x94
|
||||
/* AON Read Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_AONR 0x97
|
||||
/* AON write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_AONW 0x98
|
||||
/* GPCDMA debug Read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_GPCDMAR 0x99
|
||||
/* GPCDMA debug Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_GPCDMAW 0x9a
|
||||
/* Audio DMA Read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_APEDMAR 0x9f
|
||||
/* Audio DMA Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_APEDMAW 0xa0
|
||||
/* mss internal memqual MIU0 reads */
|
||||
#define TEGRA264_MEMORY_CLIENT_MIU0R 0xa6
|
||||
/* mss internal memqual MIU0 writes */
|
||||
#define TEGRA264_MEMORY_CLIENT_MIU0W 0xa7
|
||||
/* mss internal memqual MIU1 reads */
|
||||
#define TEGRA264_MEMORY_CLIENT_MIU1R 0xa8
|
||||
/* mss internal memqual MIU1 writes */
|
||||
#define TEGRA264_MEMORY_CLIENT_MIU1W 0xa9
|
||||
/* mss internal memqual MIU2 reads */
|
||||
#define TEGRA264_MEMORY_CLIENT_MIU2R 0xae
|
||||
/* mss internal memqual MIU2 writes */
|
||||
#define TEGRA264_MEMORY_CLIENT_MIU2W 0xaf
|
||||
/* mss internal memqual MIU3 reads */
|
||||
#define TEGRA264_MEMORY_CLIENT_MIU3R 0xb0
|
||||
/* mss internal memqual MIU3 writes */
|
||||
#define TEGRA264_MEMORY_CLIENT_MIU3W 0xb1
|
||||
/* mss internal memqual MIU4 reads */
|
||||
#define TEGRA264_MEMORY_CLIENT_MIU4R 0xb2
|
||||
/* mss internal memqual MIU4 writes */
|
||||
#define TEGRA264_MEMORY_CLIENT_MIU4W 0xb3
|
||||
#define TEGRA264_MEMORY_CLIENT_GPUR02MC 0xb6
|
||||
#define TEGRA264_MEMORY_CLIENT_GPUW02MC 0xb7
|
||||
/* VI Falcon Read client */
|
||||
|
|
@ -86,6 +170,8 @@
|
|||
#define TEGRA264_MEMORY_CLIENT_RCER 0xd2
|
||||
/* Write client of RCE */
|
||||
#define TEGRA264_MEMORY_CLIENT_RCEW 0xd3
|
||||
#define TEGRA264_MEMORY_CLIENT_NVENC1SRD2MC 0xd6
|
||||
#define TEGRA264_MEMORY_CLIENT_NVENC1SWR2MC 0xd7
|
||||
/* PCIE0/MSI Write clients */
|
||||
#define TEGRA264_MEMORY_CLIENT_PCIE0W 0xd9
|
||||
/* PCIE1/RPX4 Read clients */
|
||||
|
|
@ -108,16 +194,140 @@
|
|||
#define TEGRA264_MEMORY_CLIENT_PCIE5R 0xe2
|
||||
/* PCIE5/DMX4 Write clients */
|
||||
#define TEGRA264_MEMORY_CLIENT_PCIE5W 0xe3
|
||||
/* mss internal memqual MIU5 reads */
|
||||
#define TEGRA264_MEMORY_CLIENT_MIU5R 0xfc
|
||||
/* mss internal memqual MIU5 writes */
|
||||
#define TEGRA264_MEMORY_CLIENT_MIU5W 0xfd
|
||||
/* mss internal memqual MIU6 writes */
|
||||
#define TEGRA264_MEMORY_CLIENT_MIU6W 0xff
|
||||
#define TEGRA264_MEMORY_CLIENT_RISTR 0x100
|
||||
#define TEGRA264_MEMORY_CLIENT_RISTW 0x101
|
||||
/* OESP (Pluton) Read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_OESPR 0x102
|
||||
/* OESP (Pluton) Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_OESPW 0x103
|
||||
/* mss internal memqual MIU7 writes */
|
||||
#define TEGRA264_MEMORY_CLIENT_MIU7W 0x105
|
||||
/* mss internal memqual MIU8 reads */
|
||||
#define TEGRA264_MEMORY_CLIENT_MIU8R 0x106
|
||||
/* mss internal memqual MIU8 writes */
|
||||
#define TEGRA264_MEMORY_CLIENT_MIU8W 0x107
|
||||
/* mss internal memqual MIU9 reads */
|
||||
#define TEGRA264_MEMORY_CLIENT_MIU9R 0x108
|
||||
/* mss internal memqual MIU9 writes */
|
||||
#define TEGRA264_MEMORY_CLIENT_MIU9W 0x109
|
||||
/* HWPM Write Interface */
|
||||
#define TEGRA264_MEMORY_CLIENT_PMA0AWR 0x122
|
||||
#define TEGRA264_MEMORY_CLIENT_NVJPG1SRD2MC 0x123
|
||||
#define TEGRA264_MEMORY_CLIENT_NVJPG1SWR2MC 0x124
|
||||
/* CTW read client mapped to SMMU0 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU0CTWR 0x12e
|
||||
/* CMDQV read client mapped to SMMU0 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU0CMDQVR 0x12f
|
||||
/* CMDQV write client mapped to SMMU0 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU0CMDQVW 0x130
|
||||
/* EVNTQ write client mapped to SMMU0 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU0EVNTQW 0x131
|
||||
/* PTW read client mapped to SMMU1 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU1PTWR 0x132
|
||||
/* CTW read client mapped to SMMU1 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU1CTWR 0x134
|
||||
/* CMDQV read client mapped to SMMU1 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU1CMDQVR 0x135
|
||||
/* CMDQV write client mapped to SMMU1 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU1CMDQVW 0x136
|
||||
/* EVNTQ write client mapped to SMMU1 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU1EVNTQW 0x137
|
||||
/* PTW read client mapped to SMMU2 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU2PTWR 0x138
|
||||
/* CTW read client mapped to SMMU2 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU2CTWR 0x13a
|
||||
/* CMDQV read client mapped to SMMU2 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU2CMDQVR 0x13b
|
||||
/* CMDQV write client mapped to SMMU2 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU2CMDQVW 0x13c
|
||||
/* EVNTQ write client mapped to SMMU2 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU2EVNTQW 0x13d
|
||||
/* CMDQ read client mapped to SMMU0 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU0CMDQR 0x144
|
||||
/* CMDQ read client mapped to SMMU1 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU1CMDQR 0x145
|
||||
/* CMDQ read client mapped to SMMU2 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU2CMDQR 0x146
|
||||
/* Audio processor1(APE1) Read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_APE1R 0x150
|
||||
/* Audio processor1(APE1) Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_APE1W 0x151
|
||||
/* UFS Read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_UFSR 0x15c
|
||||
/* UFS write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_UFSW 0x15d
|
||||
/* XUSB HOST Read Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_XUSB_DEVR 0x166
|
||||
/* XUSB HOST Write Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_XUSB_DEVW 0x167
|
||||
/* XUSB SS0 Read Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_XUSB_DEV1R 0x168
|
||||
/* XUSB SS1 Write Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_XUSB_DEV2W 0x169
|
||||
/* XUSB SS2 Read Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_XUSB_DEV3R 0x16a
|
||||
/* XUSB SS2 Write Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_XUSB_DEV3W 0x16b
|
||||
/* XUSB SS3 Read Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_XUSB_DEV4R 0x16c
|
||||
/* XUSB SS3 Write Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_XUSB_DEV4W 0x16d
|
||||
/* XUSB DEV Read Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_XUSB_DEV5R 0x16e
|
||||
/* XUSB DEV Write Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_XUSB_DEV5W 0x16f
|
||||
/* DCE Read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_DCER 0x17a
|
||||
/* DCE Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_DCEW 0x17b
|
||||
/* HDA Read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_HDAR 0x17c
|
||||
/* HDA Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_HDAW 0x17d
|
||||
/* DISPNISO read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_DISPNISOR 0x17e
|
||||
/* DISPNISO write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_DISPNISOW 0x17f
|
||||
/* XUSB SS0 Write Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_XUSB_DEV1W 0x180
|
||||
/* XUSB SS1 Read Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_XUSB_DEV2R 0x181
|
||||
/* Disp ISO Read Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_DISPR 0x182
|
||||
/* MSSSEQ Read Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_MSSSEQR 0x185
|
||||
/* MSSSEQ Write Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_MSSSEQW 0x186
|
||||
/* PTW read client mapped to SMMU3 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU3PTWR 0x18b
|
||||
/* CTW read client mapped to SMMU3 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU3CTWR 0x18d
|
||||
/* CMDQV read client mapped to SMMU3 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU3CMDQVR 0x18e
|
||||
/* CMDQV write client mapped to SMMU3 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU3CMDQVW 0x18f
|
||||
/* EVNTQ write client mapped to SMMU3 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU3EVNTQW 0x190
|
||||
/* CMDQ read client mapped to SMMU3 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU3CMDQR 0x191
|
||||
/* PTW read client mapped to SMMU4 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU4PTWR 0x192
|
||||
/* CTW read client mapped to SMMU4 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU4CTWR 0x194
|
||||
/* CMDQV read client mapped to SMMU4 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU4CMDQVR 0x195
|
||||
/* CMDQV write client mapped to SMMU4 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU4CMDQVW 0x196
|
||||
/* EVNTQ write client mapped to SMMU4 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU4EVNTQW 0x197
|
||||
/* CMDQ read client mapped to SMMU4 */
|
||||
#define TEGRA264_MEMORY_CLIENT_SMMU4CMDQR 0x198
|
||||
/* MGBE0 Read mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_MGBE0R 0x1a2
|
||||
/* MGBE0 Write mccif */
|
||||
|
|
@ -128,9 +338,86 @@
|
|||
#define TEGRA264_MEMORY_CLIENT_MGBE1W 0x1a5
|
||||
/* VI1 R5 Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_VI1W 0x1a6
|
||||
/* VI Falcon1 Read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_VIFALCON1R 0x1a7
|
||||
/* VI Falcon1 Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_VIFALCON1W 0x1a8
|
||||
/* ISP FALCON1 Read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_ISPFALCON1R 0x1a9
|
||||
/* ISP FALCON1 Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_ISPFALCON1W 0x1aa
|
||||
/* Read Client of RCE1 */
|
||||
#define TEGRA264_MEMORY_CLIENT_RCE1R 0x1ab
|
||||
/* Write client of RCE1 */
|
||||
#define TEGRA264_MEMORY_CLIENT_RCE1W 0x1ac
|
||||
/* SEU2 Read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_SEU2R 0x1ad
|
||||
/* SEU2 Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_SEU2W 0x1ae
|
||||
/* SEU3 Read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_SEU3R 0x1af
|
||||
/* SEU3 Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_SEU3W 0x1b0
|
||||
/* PVA0 Falcon Read mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_PVA0R 0x1b1
|
||||
/* PVA0 Falcon Write mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_PVA0W 0x1b2
|
||||
/* PVA1 Read mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_PVA1R 0x1b3
|
||||
/* PVA1 Write mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_PVA1W 0x1b4
|
||||
/* PVA2 Read mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_PVA2R 0x1b5
|
||||
/* PVA2 Write mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_PVA2W 0x1b6
|
||||
/* ISP3 Write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_ISP3W 0x1b7
|
||||
/* ISP2 Read Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_ISP2R 0x1b8
|
||||
/* ISP2 Write Client */
|
||||
#define TEGRA264_MEMORY_CLIENT_ISP2W 0x1b9
|
||||
/* EQOS Read mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_EQOSR 0x1bc
|
||||
/* EQOS Write mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_EQOSW 0x1bd
|
||||
/* FSI0 Read mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_FSI0R 0x1be
|
||||
/* FSI0 Write mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_FSI0W 0x1bf
|
||||
/* FSI1 Read mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_FSI1R 0x1c0
|
||||
/* FSI1 Write mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_FSI1W 0x1c1
|
||||
/* SDMMC0 Read mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_SDMMC0R 0x1c2
|
||||
/* SDMMC0 Write mccif */
|
||||
#define TEGRA264_MEMORY_CLIENT_SDMMC0W 0x1c3
|
||||
/* Strongbox (SB) read client */
|
||||
#define TEGRA264_MEMORY_CLIENT_SBR 0x1c6
|
||||
/* Strongbox (SB) write client */
|
||||
#define TEGRA264_MEMORY_CLIENT_SBW 0x1c7
|
||||
#define TEGRA264_MEMORY_CLIENT_HSS_MIU0R 0x1c8
|
||||
#define TEGRA264_MEMORY_CLIENT_HSS_MIU0W 0x1c9
|
||||
#define TEGRA264_MEMORY_CLIENT_HSS_MIU1R 0x1ca
|
||||
#define TEGRA264_MEMORY_CLIENT_HSS_MIU1W 0x1cb
|
||||
#define TEGRA264_MEMORY_CLIENT_HSS_MIU2R 0x1cc
|
||||
#define TEGRA264_MEMORY_CLIENT_HSS_MIU2W 0x1cd
|
||||
#define TEGRA264_MEMORY_CLIENT_HSS_MIU3R 0x1ce
|
||||
#define TEGRA264_MEMORY_CLIENT_HSS_MIU3W 0x1cf
|
||||
#define TEGRA264_MEMORY_CLIENT_HSS_MIU4R 0x1d0
|
||||
#define TEGRA264_MEMORY_CLIENT_HSS_MIU4W 0x1d1
|
||||
#define TEGRA264_MEMORY_CLIENT_HSS_MIU5R 0x1d2
|
||||
#define TEGRA264_MEMORY_CLIENT_HSS_MIU5W 0x1d3
|
||||
#define TEGRA264_MEMORY_CLIENT_HSS_MIU6R 0x1d4
|
||||
#define TEGRA264_MEMORY_CLIENT_HSS_MIU6W 0x1d5
|
||||
#define TEGRA264_MEMORY_CLIENT_HSS_MIU7R 0x1d6
|
||||
#define TEGRA264_MEMORY_CLIENT_HSS_MIU7W 0x1d7
|
||||
#define TEGRA264_MEMORY_CLIENT_GMMUR2MC 0x1d8
|
||||
#define TEGRA264_MEMORY_CLIENT_UCFELAR 0x1d9
|
||||
#define TEGRA264_MEMORY_CLIENT_UCFELAW 0x1da
|
||||
#define TEGRA264_MEMORY_CLIENT_SLCR 0x1db
|
||||
#define TEGRA264_MEMORY_CLIENT_SLCW 0x1dc
|
||||
#define TEGRA264_MEMORY_CLIENT_REMOTER 0x1dd
|
||||
#define TEGRA264_MEMORY_CLIENT_REMOTEW 0x1de
|
||||
|
||||
#endif /* DT_BINDINGS_MEMORY_NVIDIA_TEGRA264_H */
|
||||
|
|
|
|||
|
|
@ -40,4 +40,71 @@
|
|||
#define TEGRA114_MC_RESET_VDE 14
|
||||
#define TEGRA114_MC_RESET_VI 15
|
||||
|
||||
#define TEGRA114_MC_PTCR 0
|
||||
#define TEGRA114_MC_DISPLAY0A 1
|
||||
#define TEGRA114_MC_DISPLAY0AB 2
|
||||
#define TEGRA114_MC_DISPLAY0B 3
|
||||
#define TEGRA114_MC_DISPLAY0BB 4
|
||||
#define TEGRA114_MC_DISPLAY0C 5
|
||||
#define TEGRA114_MC_DISPLAY0CB 6
|
||||
#define TEGRA114_MC_DISPLAY1B 7
|
||||
#define TEGRA114_MC_DISPLAY1BB 8
|
||||
#define TEGRA114_MC_EPPUP 9
|
||||
#define TEGRA114_MC_G2PR 10
|
||||
#define TEGRA114_MC_G2SR 11
|
||||
#define TEGRA114_MC_MPEUNIFBR 12
|
||||
#define TEGRA114_MC_VIRUV 13
|
||||
#define TEGRA114_MC_AFIR 14
|
||||
#define TEGRA114_MC_AVPCARM7R 15
|
||||
#define TEGRA114_MC_DISPLAYHC 16
|
||||
#define TEGRA114_MC_DISPLAYHCB 17
|
||||
#define TEGRA114_MC_FDCDRD 18
|
||||
#define TEGRA114_MC_FDCDRD2 19
|
||||
#define TEGRA114_MC_G2DR 20
|
||||
#define TEGRA114_MC_HDAR 21
|
||||
#define TEGRA114_MC_HOST1XDMAR 22
|
||||
#define TEGRA114_MC_HOST1XR 23
|
||||
#define TEGRA114_MC_IDXSRD 24
|
||||
#define TEGRA114_MC_IDXSRD2 25
|
||||
#define TEGRA114_MC_MPE_IPRED 26
|
||||
#define TEGRA114_MC_MPEAMEMRD 27
|
||||
#define TEGRA114_MC_MPECSRD 28
|
||||
#define TEGRA114_MC_PPCSAHBDMAR 29
|
||||
#define TEGRA114_MC_PPCSAHBSLVR 30
|
||||
#define TEGRA114_MC_SATAR 31
|
||||
#define TEGRA114_MC_TEXSRD 32
|
||||
#define TEGRA114_MC_TEXSRD2 33
|
||||
#define TEGRA114_MC_VDEBSEVR 34
|
||||
#define TEGRA114_MC_VDEMBER 35
|
||||
#define TEGRA114_MC_VDEMCER 36
|
||||
#define TEGRA114_MC_VDETPER 37
|
||||
#define TEGRA114_MC_MPCORELPR 38
|
||||
#define TEGRA114_MC_MPCORER 39
|
||||
#define TEGRA114_MC_EPPU 40
|
||||
#define TEGRA114_MC_EPPV 41
|
||||
#define TEGRA114_MC_EPPY 42
|
||||
#define TEGRA114_MC_MPEUNIFBW 43
|
||||
#define TEGRA114_MC_VIWSB 44
|
||||
#define TEGRA114_MC_VIWU 45
|
||||
#define TEGRA114_MC_VIWV 46
|
||||
#define TEGRA114_MC_VIWY 47
|
||||
#define TEGRA114_MC_G2DW 48
|
||||
#define TEGRA114_MC_AFIW 49
|
||||
#define TEGRA114_MC_AVPCARM7W 50
|
||||
#define TEGRA114_MC_FDCDWR 51
|
||||
#define TEGRA114_MC_FDCDWR2 52
|
||||
#define TEGRA114_MC_HDAW 53
|
||||
#define TEGRA114_MC_HOST1XW 54
|
||||
#define TEGRA114_MC_ISPW 55
|
||||
#define TEGRA114_MC_MPCORELPW 56
|
||||
#define TEGRA114_MC_MPCOREW 57
|
||||
#define TEGRA114_MC_MPECSWR 58
|
||||
#define TEGRA114_MC_PPCSAHBDMAW 59
|
||||
#define TEGRA114_MC_PPCSAHBSLVW 60
|
||||
#define TEGRA114_MC_SATAW 61
|
||||
#define TEGRA114_MC_VDEBSEVW 62
|
||||
#define TEGRA114_MC_VDEDBGW 63
|
||||
#define TEGRA114_MC_VDEMBEW 64
|
||||
#define TEGRA114_MC_VDETPMW 65
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -164,7 +164,7 @@ struct tegra_mc_ops {
|
|||
*/
|
||||
int (*probe)(struct tegra_mc *mc);
|
||||
void (*remove)(struct tegra_mc *mc);
|
||||
int (*resume)(struct tegra_mc *mc);
|
||||
void (*resume)(struct tegra_mc *mc);
|
||||
int (*probe_device)(struct tegra_mc *mc, struct device *dev);
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user