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drm/amd/pm: add PWR_CKS_CNTL setting

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This is for some special Polaris10 ASICs.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2020-06-18 16:28:02 +08:00 committed by Alex Deucher
parent 92995254af
commit 8c23cc29d5
1 changed files with 11 additions and 4 deletions
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15
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
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@ -2138,10 +2138,17 @@ static int smu7_patch_voltage_workaround(struct pp_hwmgr *hwmgr)
sub_sys_id = adev->pdev->subsystem_device;
sub_vendor_id = adev->pdev->subsystem_vendor;
if (hwmgr->chip_id == CHIP_POLARIS10 && hw_revision == 0xC7 &&
((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) ||
(sub_sys_id == 0x4a8 && sub_vendor_id == 0x1043) ||
(sub_sys_id == 0x9480 && sub_vendor_id == 0x1682))) {
if (adev->pdev->device == 0x67DF && hw_revision == 0xC7 &&
((sub_sys_id == 0xb37 && sub_vendor_id == 0x1002) ||
(sub_sys_id == 0x4a8 && sub_vendor_id == 0x1043) ||
(sub_sys_id == 0x9480 && sub_vendor_id == 0x1682))) {
PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device,
CGS_IND_REG__SMC,
PWR_CKS_CNTL,
CKS_STRETCH_AMOUNT,
0x3);
if (lookup_table->entries[dep_mclk_table->entries[dep_mclk_table->count-1].vddInd].us_vdd >= 1000)
return 0;