From e378b965330d99e8622eb369021d0dac01591046 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 2 May 2022 14:07:45 +0530 Subject: [PATCH 01/48] ARM: dts: qcom: sdx65: Add Shared memory manager support Add smem node to support shared memory manager on SDX65 platform. Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1651480665-14978-5-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index df6f9d6288fe..610e6b90b6cb 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -87,8 +87,10 @@ aop_mem: memory@8fe00000 { }; smem_mem: memory@8fe20000 { - no-map; + compatible = "qcom,smem"; reg = <0x8fe20000 0xc0000>; + hwlocks = <&tcsr_mutex 3>; + no-map; }; cmd_db: reserved-memory@8fee0000 { From b456b5e7d1df276a4e1050680eec86ccb99d8a82 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 2 May 2022 14:36:32 +0530 Subject: [PATCH 02/48] ARM: dts: qcom: sdx65: Add interconnect nodes Add interconnect devicetree nodes in SDX65 platform. Signed-off-by: Rohit Agarwal Acked-by: Krzysztof Kozlowski [bjorn: Sorted nodes] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1651482395-29443-2-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 610e6b90b6cb..93ac4c740d96 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -51,6 +51,12 @@ cpu0: cpu@0 { }; }; + mc_virt: interconnect-mc-virt { + compatible = "qcom,sdx65-mc-virt"; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -139,6 +145,13 @@ blsp1_uart3: serial@831000 { status = "disabled"; }; + system_noc: interconnect@1620000 { + compatible = "qcom,sdx65-system-noc"; + reg = <0x01620000 0x31200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>; @@ -158,6 +171,13 @@ sdhc_1: sdhci@8804000 { status = "disabled"; }; + mem_noc: interconnect@9680000 { + compatible = "qcom,sdx65-mem-noc"; + reg = <0x09680000 0x27200>; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0xd00>, @@ -401,6 +421,11 @@ rpmhpd_opp_turbo_l1: opp10 { }; }; }; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + }; }; From fbb6447deba87dc409e274d9d6d90d9c79851fb7 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 2 May 2022 14:36:34 +0530 Subject: [PATCH 03/48] ARM: dts: qcom: sdx65: Add USB3 and PHY support Add devicetree nodes for enabling USB3 controller, Qcom QMP PHY and SNPS HS PHY on SDX65. Signed-off-by: Rohit Agarwal Reviewed-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1651482395-29443-4-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 83 +++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 93ac4c740d96..9af5e3d3822a 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -132,6 +132,7 @@ gcc: clock-controller@100000 { reg = <0x00100000 0x001f7400>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + #power-domain-cells = <1>; #clock-cells = <1>; #reset-cells = <1>; }; @@ -145,6 +146,45 @@ blsp1_uart3: serial@831000 { status = "disabled"; }; + usb_hsphy: phy@ff4000 { + compatible = "qcom,usb-snps-hs-7nm-phy"; + reg = <0xff4000 0x120>; + #phy-cells = <0>; + status = "disabled"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + resets = <&gcc GCC_QUSB2PHY_BCR>; + }; + + usb_qmpphy: phy@ff6000 { + compatible = "qcom,sdx65-qmp-usb3-uni-phy"; + reg = <0x00ff6000 0x1c8>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_EN>; + clock-names = "aux", "cfg_ahb", "ref"; + + resets = <&gcc GCC_USB3PHY_PHY_BCR>, + <&gcc GCC_USB3_PHY_BCR>; + reset-names = "phy", "common"; + + usb_ssphy: phy@ff6200 { + reg = <0x00ff6e00 0x160>, + <0x00ff7000 0x1ec>, + <0x00ff6200 0x1e00>; + #phy-cells = <0>; + #clock-cells = <0>; + clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_uni_phy_pipe_clk_src"; + }; + }; + system_noc: interconnect@1620000 { compatible = "qcom,sdx65-system-noc"; reg = <0x01620000 0x31200>; @@ -178,6 +218,49 @@ mem_noc: interconnect@9680000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + usb: usb@a6f8800 { + compatible = "qcom,sdx65-dwc3", "qcom,dwc3"; + reg = <0x0a6f8800 0x400>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB30_SLV_AHB_CLK>, + <&gcc GCC_USB30_MASTER_CLK>, + <&gcc GCC_USB30_MSTR_AXI_CLK>, + <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 19 IRQ_TYPE_EDGE_BOTH>, + <&pdc 76 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 18 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + + power-domains = <&gcc USB30_GDSC>; + + resets = <&gcc GCC_USB30_BCR>; + + usb_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0x0a600000 0xcd00>; + interrupts = ; + iommus = <&apps_smmu 0x1a0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_hsphy>, <&usb_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0xd00>, From eeaec4f2b926ffcb35a9c1c4af549ac9f7a6ce56 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 2 May 2022 14:36:35 +0530 Subject: [PATCH 04/48] ARM: dts: qcom: sdx65-mtp: Enable USB3 and PHY support Enable the support for USB3 controller, QMP PHY and HS PHY on SDX65 MTP. Signed-off-by: Rohit Agarwal Reviewed-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1651482395-29443-5-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 29 ++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 79dc31aa7cd1..6920524ad65a 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -123,7 +123,7 @@ vreg_s8b_0p824: smps8 { regulator-max-microvolt = <1300000>; }; - ldo1 { + vreg_l1b_1p2: ldo1 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; regulator-initial-mode = ; @@ -141,13 +141,13 @@ ldo3 { regulator-initial-mode = ; }; - ldo4 { + vreg_l4b_0p88: ldo4 { regulator-min-microvolt = <880000>; regulator-max-microvolt = <912000>; regulator-initial-mode = ; }; - ldo5 { + vreg_l5b_1p8: ldo5 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; @@ -177,7 +177,7 @@ ldo9 { regulator-initial-mode = ; }; - ldo10 { + vreg_l10b_3p08: ldo10 { regulator-min-microvolt = <3088000>; regulator-max-microvolt = <3088000>; regulator-initial-mode = ; @@ -244,3 +244,24 @@ ldo21 { }; }; }; + +&usb { + status = "okay"; +}; + +&usb_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_hsphy { + status = "okay"; + vdda-pll-supply = <&vreg_l4b_0p88>; + vdda33-supply = <&vreg_l10b_3p08>; + vdda18-supply = <&vreg_l5b_1p8>; +}; + +&usb_qmpphy { + status = "okay"; + vdda-phy-supply = <&vreg_l4b_0p88>; + vdda-pll-supply = <&vreg_l1b_1p2>; +}; From ab11b74d87ddadb1e6e6d8dc36f3145a26158ef2 Mon Sep 17 00:00:00 2001 From: Kaushal Kumar Date: Mon, 2 May 2022 10:08:03 -0700 Subject: [PATCH 05/48] ARM: dts: qcom: sdx65: Add QPIC BAM support Add devicetree node to enable support for QPIC BAM DMA controller on Qualcomm SDX65 platform. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Kaushal Kumar Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1651511286-18690-2-git-send-email-quic_kaushalk@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 9af5e3d3822a..91c9dc18fe3a 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -192,6 +192,18 @@ system_noc: interconnect@1620000 { qcom,bcm-voters = <&apps_bcm_voter>; }; + qpic_bam: dma-controller@1b04000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x01b04000 0x1c000>; + interrupts = ; + clocks = <&rpmhcc RPMH_QPIC_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + qcom,controlled-remotely; + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>; From 0ec15b6f7621c2e5ded3d3d1a67361da1895c26b Mon Sep 17 00:00:00 2001 From: Kaushal Kumar Date: Mon, 2 May 2022 10:08:04 -0700 Subject: [PATCH 06/48] ARM: dts: qcom: sdx65: Add QPIC NAND support Add devicetree node to enable support for QPIC NAND controller on Qualcomm SDX65 platform. Since there is no "aon" clock in SDX65, a dummy clock is provided. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Kaushal Kumar Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1651511286-18690-3-git-send-email-quic_kaushalk@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 91c9dc18fe3a..7fd75c441289 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -37,6 +37,12 @@ sleep_clk: sleep-clk { clock-output-names = "sleep_clk"; #clock-cells = <0>; }; + + nand_clk_dummy: nand-clk-dummy { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; }; cpus { @@ -204,6 +210,22 @@ qpic_bam: dma-controller@1b04000 { status = "disabled"; }; + qpic_nand: nand-controller@1b30000 { + compatible = "qcom,sdx55-nand"; + reg = <0x01b30000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&rpmhcc RPMH_QPIC_CLK>, + <&nand_clk_dummy>; + clock-names = "core", "aon"; + + dmas = <&qpic_bam 0>, + <&qpic_bam 1>, + <&qpic_bam 2>; + dma-names = "tx", "rx", "cmd"; + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>; From eae61fddd64861fc496a7786b02449abe8188145 Mon Sep 17 00:00:00 2001 From: Kaushal Kumar Date: Mon, 2 May 2022 10:08:05 -0700 Subject: [PATCH 07/48] ARM: dts: qcom: sdx65-mtp: Enable QPIC BAM support Enable QPIC BAM devicetree node for Qualcomm SDX65-MTP board. While at it, sort the blsp1_uart3 node in alphabetical order and set it's status as "okay". Reviewed-by: Manivannan Sadhasivam Signed-off-by: Kaushal Kumar Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1651511286-18690-4-git-send-email-quic_kaushalk@quicinc.com --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 6920524ad65a..e9c8df9da9c3 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -64,10 +64,6 @@ vreg_bob_3p3: pmx65_bob { }; }; -&blsp1_uart3 { - status = "ok"; -}; - &apps_rsc { pmx65-rpmh-regulators { compatible = "qcom,pmx65-rpmh-regulators"; @@ -245,6 +241,14 @@ ldo21 { }; }; +&blsp1_uart3 { + status = "okay"; +}; + +&qpic_bam { + status = "okay"; +}; + &usb { status = "okay"; }; From 59e73f67e14b95eddbbff2f009c98a55cef47f8a Mon Sep 17 00:00:00 2001 From: Kaushal Kumar Date: Mon, 2 May 2022 10:08:06 -0700 Subject: [PATCH 08/48] ARM: dts: qcom: sdx65-mtp: Enable QPIC NAND support Enable QPIC NAND devicetree node for Qualcomm SDX65-MTP board. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Kaushal Kumar Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1651511286-18690-5-git-send-email-quic_kaushalk@quicinc.com --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index e9c8df9da9c3..e747ec0ccbf6 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -249,6 +249,21 @@ &qpic_bam { status = "okay"; }; +&qpic_nand { + status = "okay"; + + nand@0 { + reg = <0>; + + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + nand-bus-width = <8>; + /* ico and efs2 partitions are secured */ + secure-regions = /bits/ 64 <0x500000 0x500000 + 0xa00000 0xb00000>; + }; +}; + &usb { status = "okay"; }; From b427679adcddf9d56b28175d435fc7ec4d4c99ef Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 1 Jun 2022 16:15:02 +0530 Subject: [PATCH 09/48] ARM: dts: qcom: sdx65: Add CPUFreq support Add CPUFreq support to SDX65 platform using the cpufreq-dt driver. There is no dedicated hardware block available on this platform to carry on the CPUFreq duties. Hence, it is accomplished using the CPU clock and regulators tied together by the operating points table. Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1654080312-5408-2-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 7fd75c441289..aea361df47be 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -54,6 +54,35 @@ cpu0: cpu@0 { compatible = "arm,cortex-a7"; reg = <0x0>; enable-method = "psci"; + clocks = <&apcs>; + power-domains = <&rpmhpd SDX65_CX_AO>; + power-domain-names = "rpmhpd"; + operating-points-v2 = <&cpu_opp_table>; + }; + }; + + cpu_opp_table: cpu-opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-345600000 { + opp-hz = /bits/ 64 <345600000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + required-opps = <&rpmhpd_opp_turbo>; }; }; From 7f928c735880ed20e4d7670416aa7877b47a47d1 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 1 Jun 2022 16:15:03 +0530 Subject: [PATCH 10/48] ARM: dts: qcom: sdx65: Add modem SMP2P node Add SMP2P nodes for the SDX65 platform to communicate with the modem. Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1654080312-5408-3-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index aea361df47be..217ae4f4b44e 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -156,6 +156,37 @@ llcc_tcm_mem: memory@15800000 { }; }; + smp2p-mpss { + compatible = "qcom,smp2p"; + qcom,smem = <435>, <428>; + interrupts = ; + mboxes = <&apcs 14>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + modem_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + modem_smp2p_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; From 69117a2abfe0b02c6828979e8a6f9b039908b42a Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 1 Jun 2022 16:15:04 +0530 Subject: [PATCH 11/48] ARM: dts: qcom: sdx65: Add IMEM and PIL info region Add a simple-mfd representing IMEM on SDX65 and define the PIL relocation info region, so that post mortem tools will be able to locate the loaded remoteproc. Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1654080312-5408-4-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 217ae4f4b44e..34f548a942a5 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -395,6 +395,19 @@ pdc: interrupt-controller@b210000 { interrupt-controller; }; + imem@1468f000 { + compatible = "simple-mfd"; + reg = <0x1468f000 0x1000>; + ranges = <0x0 0x1468f000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sdx65-smmu-500", "arm,mmu-500"; reg = <0x15000000 0x40000>; From 261e09b4e3fb847b9a1e99538e31fdfdc2d1ee90 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 1 Jun 2022 16:15:06 +0530 Subject: [PATCH 12/48] ARM: dts: qcom: sdx65: Add SCM node Add SCM node to enable SCM functionality on SDX65 platform. Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1654080312-5408-6-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 34f548a942a5..8695579a7dc8 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -86,6 +86,12 @@ opp-1497600000 { }; }; + firmware { + scm { + compatible = "qcom,scm-sdx65", "qcom,scm"; + }; + }; + mc_virt: interconnect-mc-virt { compatible = "qcom,sdx65-mc-virt"; #interconnect-cells = <1>; From a3ae01ed96e7efc2525125c36dc8e34186f0d7bc Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 1 Jun 2022 16:15:07 +0530 Subject: [PATCH 13/48] ARM: dts: qcom: sdx65: Add Modem remoteproc node Add modem support to SDX65 using the PAS remoteproc driver. Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1654080312-5408-7-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 33 +++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 8695579a7dc8..fd9a6a7126bf 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -298,6 +298,39 @@ tcsr_mutex: hwlock@1f40000 { #hwlock-cells = <1>; }; + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sdx55-mpss-pas"; + reg = <0x04080000 0x4040>; + + interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SDX65_CX>, + <&rpmhpd SDX65_MSS>; + power-domain-names = "cx", "mss"; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts = ; + label = "mpss"; + qcom,remote-pid = <1>; + mboxes = <&apcs 15>; + }; + }; + sdhc_1: sdhci@8804000 { compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>; From aae0f5314f95df66962acfcce23158e2a047b03c Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 1 Jun 2022 16:15:08 +0530 Subject: [PATCH 14/48] ARM: dts: qcom: sdx65-mtp: Enable modem Enable modem on SDX65 MTP board. Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1654080312-5408-8-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index e747ec0ccbf6..85ea02d8362d 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -264,6 +264,11 @@ nand@0 { }; }; +&remoteproc_mpss { + status = "okay"; + memory-region = <&mpss_adsp_mem>; +}; + &usb { status = "okay"; }; From df6d7b86f4885d370886a44339017e32c80556e7 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 1 Jun 2022 16:15:12 +0530 Subject: [PATCH 15/48] ARM: dts: qcom: sdx65: Add pshold support Add support for pshold block to drive pshold towards the PMIC, which is used to trigger a configurable event such as reboot or poweroff of the SDX65 platform. Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1654080312-5408-12-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index fd9a6a7126bf..67b8ad23cac8 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -394,6 +394,11 @@ usb_dwc3: usb@a600000 { }; }; + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0x0c264000 0x1000>; + }; + spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0xd00>, From 39eebfce4bdb88f53959d570ab9c8956bb9f0988 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 1 Jun 2022 16:15:11 +0530 Subject: [PATCH 16/48] ARM: dts: qcom: sdx65: Add Watchdog support Enable Watchdog support for Application Processor Subsystem (APSS) block on SDX65 platform. Signed-off-by: Rohit Agarwal Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1654080312-5408-11-git-send-email-quic_rohiagar@quicinc.com --- arch/arm/boot/dts/qcom-sdx65.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 67b8ad23cac8..1881b6d2485b 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -518,6 +518,12 @@ apcs: mailbox@17810000 { #clock-cells = <0>; }; + watchdog@17817000 { + compatible = "qcom,apss-wdt-sdx65", "qcom,kpss-wdt"; + reg = <0x17817000 0x1000>; + clocks = <&sleep_clk>; + }; + timer@17820000 { #address-cells = <1>; #size-cells = <1>; From 4fcdaf4b0320f93d0ccb4d36b795ed258fb07b27 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 7 May 2022 21:49:11 +0200 Subject: [PATCH 17/48] ARM: dts: qcom: align PMIC GPIO pin configuration with DT schema DT schema expects PMIC GPIO pin configuration nodes to be named with '-state' suffix. Optional children should be either 'pinconf' or followed with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220507194913.261121-10-krzysztof.kozlowski@linaro.org --- .../arm/boot/dts/qcom-apq8060-dragonboard.dts | 20 +++++++++---------- arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 4 ++-- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 8 ++++---- .../qcom-apq8064-sony-xperia-lagan-yuga.dts | 2 +- arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi | 2 +- .../qcom-msm8974-lge-nexus5-hammerhead.dts | 8 ++++---- .../dts/qcom-msm8974-sony-xperia-rhine.dtsi | 2 +- .../dts/qcom-msm8974pro-fairphone-fp2.dts | 2 +- .../boot/dts/qcom-msm8974pro-samsung-klte.dts | 14 ++++++------- ...-msm8974pro-sony-xperia-shinano-castor.dts | 10 +++++----- arch/arm/boot/dts/qcom-pm8941.dtsi | 2 +- 11 files changed, 37 insertions(+), 37 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index 138d6478ac84..a104acbfee05 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -273,7 +273,7 @@ MATRIX_KEY(4, 3, KEY_KBDILLUMTOGGLE) }; gpio@150 { - dragon_ethernet_gpios: ethernet-gpios { + dragon_ethernet_gpios: ethernet-state { pinconf { pins = "gpio7"; function = "normal"; @@ -282,7 +282,7 @@ pinconf { power-source = ; }; }; - dragon_bmp085_gpios: bmp085-gpios { + dragon_bmp085_gpios: bmp085-state { pinconf { pins = "gpio16"; function = "normal"; @@ -291,7 +291,7 @@ pinconf { power-source = ; }; }; - dragon_mpu3050_gpios: mpu3050-gpios { + dragon_mpu3050_gpios: mpu3050-state { pinconf { pins = "gpio17"; function = "normal"; @@ -300,7 +300,7 @@ pinconf { power-source = ; }; }; - dragon_sdcc3_gpios: sdcc3-gpios { + dragon_sdcc3_gpios: sdcc3-state { pinconf { pins = "gpio22"; function = "normal"; @@ -309,7 +309,7 @@ pinconf { power-source = ; }; }; - dragon_sdcc5_gpios: sdcc5-gpios { + dragon_sdcc5_gpios: sdcc5-state { pinconf { pins = "gpio26"; function = "normal"; @@ -319,7 +319,7 @@ pinconf { power-source = ; }; }; - dragon_ak8975_gpios: ak8975-gpios { + dragon_ak8975_gpios: ak8975-state { pinconf { pins = "gpio33"; function = "normal"; @@ -328,9 +328,9 @@ pinconf { power-source = ; }; }; - dragon_cm3605_gpios: cm3605-gpios { + dragon_cm3605_gpios: cm3605-state { /* Pin 34 connected to the proxy IRQ */ - pinconf_gpio34 { + gpio34-pins { pins = "gpio34"; function = "normal"; input-enable; @@ -338,7 +338,7 @@ pinconf_gpio34 { power-source = ; }; /* Pin 35 connected to ASET */ - pinconf_gpio35 { + gpio35-pins { pins = "gpio35"; function = "normal"; output-high; @@ -346,7 +346,7 @@ pinconf_gpio35 { power-source = ; }; }; - dragon_veth_gpios: veth-gpios { + dragon_veth_gpios: veth-state { pinconf { pins = "gpio40"; function = "normal"; diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts index e068a8d0adf0..7e57a0750320 100644 --- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts +++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts @@ -196,8 +196,8 @@ v3p3_fixed: v3p3 { qcom,ssbi@500000 { pmic@0 { gpio@150 { - wlan_default_gpios: wlan-gpios { - pios { + wlan_default_gpios: wlan-gpios-state { + pinconf { pins = "gpio43"; function = "normal"; bias-disable; diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 2638b380be20..77e841243646 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -291,8 +291,8 @@ pci@1b500000 { qcom,ssbi@500000 { pmic@0 { gpio@150 { - wlan_default_gpios: wlan-gpios { - pios { + wlan_default_gpios: wlan-gpios-state { + pinconf { pins = "gpio43"; function = "normal"; bias-disable; @@ -300,8 +300,8 @@ pios { }; }; - notify_led: nled { - pios { + notify_led: nled-state { + pinconf { pins = "gpio18"; function = "normal"; bias-disable; diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts index 0cee62c7b8b0..3cf79cc5b539 100644 --- a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts +++ b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts @@ -334,7 +334,7 @@ ncp { qcom,ssbi@500000 { pmic@0 { gpio@150 { - gpio_keys_pin_a: gpio-keys-pin-active { + gpio_keys_pin_a: gpio-keys-active-state { pins = "gpio3", "gpio4", "gpio29", "gpio35"; function = "normal"; diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi index 10ad929759ed..49de1821ac3a 100644 --- a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi @@ -114,7 +114,7 @@ pins { }; &pmicgpio { - usb_vbus_5v_pins: usb_vbus_5v_pins { + usb_vbus_5v_pins: usb-vbus-5v-state { pins = "gpio4"; function = "normal"; output-high; diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 9493886a5c0d..4d8fc8689d24 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -272,7 +272,7 @@ phy@a { }; &pm8941_gpios { - gpio_keys_pin_a: gpio-keys-active { + gpio_keys_pin_a: gpio-keys-active-state { pins = "gpio2", "gpio3"; function = "normal"; @@ -280,7 +280,7 @@ gpio_keys_pin_a: gpio-keys-active { power-source = ; }; - fuelgauge_pin: fuelgauge-int { + fuelgauge_pin: fuelgauge-int-state { pins = "gpio9"; function = "normal"; @@ -289,7 +289,7 @@ fuelgauge_pin: fuelgauge-int { power-source = ; }; - wlan_sleep_clk_pin: wl-sleep-clk { + wlan_sleep_clk_pin: wl-sleep-clk-state { pins = "gpio16"; function = "func2"; @@ -297,7 +297,7 @@ wlan_sleep_clk_pin: wl-sleep-clk { power-source = ; }; - wlan_regulator_pin: wl-reg-active { + wlan_regulator_pin: wl-reg-active-state { pins = "gpio17"; function = "normal"; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi index 1d21de46f85c..a4fec2d0d158 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi @@ -163,7 +163,7 @@ &pm8941_coincell { }; &pm8941_gpios { - gpio_keys_pin_a: gpio-keys-active { + gpio_keys_pin_a: gpio-keys-active-state { pins = "gpio2", "gpio3", "gpio4", "gpio5"; function = "normal"; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts index 58cb2ce1e4df..1c9f04322672 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts @@ -110,7 +110,7 @@ phy@a { }; &pm8941_gpios { - gpio_keys_pin_a: gpio-keys-active { + gpio_keys_pin_a: gpio-keys-active-state { pins = "gpio1", "gpio2", "gpio5"; function = "normal"; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts index d6b2300a8223..90f7a399f40b 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts @@ -398,7 +398,7 @@ phy@a { }; &pma8084_gpios { - gpio_keys_pin_a: gpio-keys-active { + gpio_keys_pin_a: gpio-keys-active-state { pins = "gpio2", "gpio3", "gpio5"; function = "normal"; @@ -406,7 +406,7 @@ gpio_keys_pin_a: gpio-keys-active { power-source = ; }; - touchkey_pin: touchkey-int-pin { + touchkey_pin: touchkey-int-state { pins = "gpio6"; function = "normal"; bias-disable; @@ -414,7 +414,7 @@ touchkey_pin: touchkey-int-pin { power-source = ; }; - touch_pin: touchscreen-int-pin { + touch_pin: touchscreen-int-state { pins = "gpio8"; function = "normal"; bias-disable; @@ -422,7 +422,7 @@ touch_pin: touchscreen-int-pin { power-source = ; }; - panel_en_pin: panel-en-pin { + panel_en_pin: panel-en-state { pins = "gpio14"; function = "normal"; bias-pull-up; @@ -430,7 +430,7 @@ panel_en_pin: panel-en-pin { qcom,drive-strength = ; }; - wlan_sleep_clk_pin: wlan-sleep-clk-pin { + wlan_sleep_clk_pin: wlan-sleep-clk-state { pins = "gpio16"; function = "func2"; @@ -439,7 +439,7 @@ wlan_sleep_clk_pin: wlan-sleep-clk-pin { qcom,drive-strength = ; }; - panel_rst_pin: panel-rst-pin { + panel_rst_pin: panel-rst-state { pins = "gpio17"; function = "normal"; bias-disable; @@ -447,7 +447,7 @@ panel_rst_pin: panel-rst-pin { qcom,drive-strength = ; }; - fuelgauge_pin: fuelgauge-int-pin { + fuelgauge_pin: fuelgauge-int-state { pins = "gpio21"; function = "normal"; bias-disable; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts index 9bd8faea61a5..e9bcd3b4ebb3 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -244,7 +244,7 @@ &pm8941_coincell { }; &pm8941_gpios { - gpio_keys_pin_a: gpio-keys-active { + gpio_keys_pin_a: gpio-keys-active-state { pins = "gpio2", "gpio5"; function = "normal"; @@ -252,7 +252,7 @@ gpio_keys_pin_a: gpio-keys-active { power-source = ; }; - bt_reg_on_pin: bt-reg-on { + bt_reg_on_pin: bt-reg-on-state { pins = "gpio16"; function = "normal"; @@ -260,7 +260,7 @@ bt_reg_on_pin: bt-reg-on { power-source = ; }; - wlan_sleep_clk_pin: wl-sleep-clk { + wlan_sleep_clk_pin: wl-sleep-clk-state { pins = "gpio17"; function = "func2"; @@ -268,7 +268,7 @@ wlan_sleep_clk_pin: wl-sleep-clk { power-source = ; }; - wlan_regulator_pin: wl-reg-active { + wlan_regulator_pin: wl-reg-active-state { pins = "gpio18"; function = "normal"; @@ -276,7 +276,7 @@ wlan_regulator_pin: wl-reg-active { power-source = ; }; - lcd_dcdc_en_pin_a: lcd-dcdc-en-active { + lcd_dcdc_en_pin_a: lcd-dcdc-en-active-state { pins = "gpio20"; function = "normal"; diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi index cdd2bdb77b32..a68634397938 100644 --- a/arch/arm/boot/dts/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom-pm8941.dtsi @@ -68,7 +68,7 @@ pm8941_gpios: gpios@c000 { interrupt-controller; #interrupt-cells = <2>; - boost_bypass_n_pin: boost-bypass { + boost_bypass_n_pin: boost-bypass-state { pins = "gpio21"; function = "normal"; }; From dc590cdc31f636ea15658f1206c3e380a53fb78e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 7 May 2022 21:49:12 +0200 Subject: [PATCH 18/48] ARM: dts: qcom: mdm9615: add missing PMIC GPIO reg 'reg' property is required in SSBI children: qcom-mdm9615-wp8548-mangoh-green.dtb: gpio@150: 'reg' is a required property Fixes: 2c5e596524e7 ("ARM: dts: Add MDM9615 dtsi") Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220507194913.261121-11-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-mdm9615.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index 8f0752ce1c7b..0ce0d04bd994 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -321,6 +321,7 @@ rtc@11d { pmicgpio: gpio@150 { compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio"; + reg = <0x150>; interrupt-controller; #interrupt-cells = <2>; gpio-controller; From 255889f4baf51e887c83333d82ac8470a11246e4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 7 May 2022 21:49:13 +0200 Subject: [PATCH 19/48] ARM: dts: qcom: pmx65: add fallback compatible to PMIC GPIO The bindings require all PMIC GPIO nodes to have two compatibles - specific followed by SPMI or SSBI fallback. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220507194913.261121-12-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-pmx65.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-pmx65.dtsi b/arch/arm/boot/dts/qcom-pmx65.dtsi index 5411b833d26e..8701396fe1f2 100644 --- a/arch/arm/boot/dts/qcom-pmx65.dtsi +++ b/arch/arm/boot/dts/qcom-pmx65.dtsi @@ -21,7 +21,7 @@ pmx65_temp: temp-alarm@a00 { }; pmx65_gpios: pinctrl@8800 { - compatible = "qcom,pmx65-gpio"; + compatible = "qcom,pmx65-gpio", "qcom,spmi-gpio"; reg = <0x8800>; gpio-controller; #gpio-cells = <2>; From eea939a0da869e00f40e41182edbcd911ee11fd4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 8 May 2022 15:59:32 +0200 Subject: [PATCH 20/48] ARM: dts: qcom: add missing gpio-ranges in PMIC GPIOs The new Qualcomm PMIC GPIO bindings require gpio-ranges property: qcom-sdx55-telit-fn980-tlb.dtb: gpio@c000: 'gpio-ranges' is a required property Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220508135932.132378-5-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-pmx55.dtsi | 1 + arch/arm/boot/dts/qcom-pmx65.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom-pmx55.dtsi b/arch/arm/boot/dts/qcom-pmx55.dtsi index 6571b88d018a..9de7578a4c5f 100644 --- a/arch/arm/boot/dts/qcom-pmx55.dtsi +++ b/arch/arm/boot/dts/qcom-pmx55.dtsi @@ -69,6 +69,7 @@ pmx55_gpios: gpio@c000 { compatible = "qcom,pmx55-gpio", "qcom,spmi-gpio"; reg = <0xc000>; gpio-controller; + gpio-ranges = <&pmx55_gpios 0 0 11>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; diff --git a/arch/arm/boot/dts/qcom-pmx65.dtsi b/arch/arm/boot/dts/qcom-pmx65.dtsi index 8701396fe1f2..abf229a8b75a 100644 --- a/arch/arm/boot/dts/qcom-pmx65.dtsi +++ b/arch/arm/boot/dts/qcom-pmx65.dtsi @@ -24,6 +24,7 @@ pmx65_gpios: pinctrl@8800 { compatible = "qcom,pmx65-gpio", "qcom,spmi-gpio"; reg = <0x8800>; gpio-controller; + gpio-ranges = <&pmx65_gpios 0 0 16>; #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; From eb9e93937756a05787977875830c0dc482cb57e0 Mon Sep 17 00:00:00 2001 From: Ansuel Smith Date: Sat, 30 Apr 2022 07:51:17 +0200 Subject: [PATCH 21/48] ARM: dts: qcom: replace gcc PXO with pxo_board fixed clock Replace gcc PXO phandle to pxo_board fixed clock declared in the dts. gcc driver doesn't provide PXO_SRC as it's a fixed-clock. This cause a kernel panic if any driver actually try to use it. Fixes: 40cf5c884a96 ("ARM: dts: qcom: add L2CC and RPM for IPQ8064") Signed-off-by: Ansuel Smith Reviewed-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220430055118.1947-2-ansuelsmth@gmail.com --- arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 808ea1862283..d09354ca100d 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -784,7 +784,7 @@ tcsr: syscon@1a400000 { l2cc: clock-controller@2011000 { compatible = "qcom,kpss-gcc", "syscon"; reg = <0x2011000 0x1000>; - clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>; + clocks = <&gcc PLL8_VOTE>, <&pxo_board>; clock-names = "pll8_vote", "pxo"; clock-output-names = "acpu_l2_aux"; }; From aaed15efce65c20951f573955e10b51c24ca6e4d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 5 May 2022 13:37:58 +0200 Subject: [PATCH 22/48] ARM: dts: qcom: use dedicated QFPROM compatibles Use dedicated compatibles for QFPROM on APQ8064, IPQ8064 and MSM9874, which is expected by the bindings. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220505113802.243301-2-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-apq8064.dtsi | 2 +- arch/arm/boot/dts/qcom-apq8084.dtsi | 2 +- arch/arm/boot/dts/qcom-ipq8064.dtsi | 2 +- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 34c0ba7fa358..3bf870b7de00 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -796,7 +796,7 @@ ref_muxoff: adc-channel@f { }; qfprom: qfprom@700000 { - compatible = "qcom,qfprom"; + compatible = "qcom,apq8064-qfprom", "qcom,qfprom"; reg = <0x00700000 0x1000>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index da50a1a0197f..503b4ae9fb1a 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -242,7 +242,7 @@ apcs: syscon@f9011000 { qfprom: qfprom@fc4bc000 { #address-cells = <1>; #size-cells = <1>; - compatible = "qcom,qfprom"; + compatible = "qcom,apq8084-qfprom", "qcom,qfprom"; reg = <0xfc4bc000 0x1000>; tsens_calib: calib@d0 { reg = <0xd0 0x18>; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index d09354ca100d..4022ed9df988 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -723,7 +723,7 @@ qcom,ssbi@500000 { }; qfprom: qfprom@700000 { - compatible = "qcom,qfprom"; + compatible = "qcom,ipq8064-qfprom", "qcom,qfprom"; reg = <0x00700000 0x1000>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 814ad0b46232..5d2ab5ceb65c 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1120,7 +1120,7 @@ restart@fc4ab000 { qfprom: qfprom@fc4bc000 { #address-cells = <1>; #size-cells = <1>; - compatible = "qcom,qfprom"; + compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; reg = <0xfc4bc000 0x1000>; tsens_calib: calib@d0 { reg = <0xd0 0x18>; From 10193ad6d487e0abdc73c704306ebe8d15d4ab74 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 5 May 2022 13:37:59 +0200 Subject: [PATCH 23/48] ARM: dts: qcom: cleanup QFPROM nodes Cleanup coding style of QFPROM nodes - put compatible as first property and drop tabs before '=' character. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220505113802.243301-3-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-apq8064.dtsi | 6 +++--- arch/arm/boot/dts/qcom-apq8084.dtsi | 4 ++-- arch/arm/boot/dts/qcom-msm8974.dtsi | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 3bf870b7de00..d3cb099cb691 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -797,9 +797,9 @@ ref_muxoff: adc-channel@f { qfprom: qfprom@700000 { compatible = "qcom,apq8064-qfprom", "qcom,qfprom"; - reg = <0x00700000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; ranges; tsens_calib: calib { reg = <0x404 0x10>; diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 503b4ae9fb1a..cb01faa23eb7 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -240,10 +240,10 @@ apcs: syscon@f9011000 { }; qfprom: qfprom@fc4bc000 { - #address-cells = <1>; - #size-cells = <1>; compatible = "qcom,apq8084-qfprom", "qcom,qfprom"; reg = <0xfc4bc000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; tsens_calib: calib@d0 { reg = <0xd0 0x18>; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 5d2ab5ceb65c..df49be66d0b8 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1118,10 +1118,10 @@ restart@fc4ab000 { }; qfprom: qfprom@fc4bc000 { - #address-cells = <1>; - #size-cells = <1>; compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; reg = <0xfc4bc000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; tsens_calib: calib@d0 { reg = <0xd0 0x18>; }; From 7b7e501f7a7293db0f66d27f0f3f191502faaad9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 5 May 2022 13:38:00 +0200 Subject: [PATCH 24/48] ARM: dts: qcom: apq8064: add unit addresses to QFPROM regions QFPROM children have 'reg' so they must have unit address. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220505113802.243301-4-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-apq8064.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index d3cb099cb691..028d52b5d075 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -801,10 +801,10 @@ qfprom: qfprom@700000 { #address-cells = <1>; #size-cells = <1>; ranges; - tsens_calib: calib { + tsens_calib: calib@404 { reg = <0x404 0x10>; }; - tsens_backup: backup_calib { + tsens_backup: backup_calib@414 { reg = <0x414 0x10>; }; }; From 7afef282d7453ded3b31f71771a31b34dda51aff Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 21 May 2022 18:45:48 +0200 Subject: [PATCH 25/48] ARM: dts: qcom: ipq4019: fix Micron SPI NOR compatible The proper compatible for Micron n25q128a11 SPI NOR flash should include vendor-prefix and use jedec,spi-nor fallback. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220521164550.91115-10-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 2 +- arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi index faeaa6bf0def..44a9597d8bfd 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi @@ -93,7 +93,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0>; - compatible = "n25q128a11"; + compatible = "micron,n25q128a11", "jedec,spi-nor"; spi-max-frequency = <24000000>; }; }; diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts index d596dd1180ae..c7a6e77da272 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts @@ -56,7 +56,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0>; - compatible = "n25q128a11"; + compatible = "micron,n25q128a11", "jedec,spi-nor"; spi-max-frequency = <24000000>; }; }; From 31b2edcab4d153145354c4333a6be5209e185598 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 26 May 2022 22:42:48 +0200 Subject: [PATCH 26/48] ARM: dts: qcom: adjust whitespace around '=' Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220526204248.832139-2-krzysztof.kozlowski@linaro.org --- .../boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 16 +-- arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts | 10 +- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 14 +- arch/arm/boot/dts/qcom-apq8064.dtsi | 136 +++++++++--------- arch/arm/boot/dts/qcom-ipq8064.dtsi | 32 ++--- arch/arm/boot/dts/qcom-mdm9615.dtsi | 6 +- arch/arm/boot/dts/qcom-msm8660.dtsi | 110 +++++++------- arch/arm/boot/dts/qcom-msm8960.dtsi | 54 +++---- .../dts/qcom-msm8974pro-fairphone-fp2.dts | 6 +- 9 files changed, 192 insertions(+), 192 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index ca9f73528196..beb2058fd116 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -24,9 +24,9 @@ reserved-memory { ramoops@88d00000{ compatible = "ramoops"; reg = <0x88d00000 0x100000>; - record-size = <0x00020000>; - console-size = <0x00020000>; - ftrace-size = <0x00020000>; + record-size = <0x00020000>; + console-size = <0x00020000>; + ftrace-size = <0x00020000>; }; }; @@ -98,8 +98,8 @@ s3 { * tabla2x-slim-VDDIO_CDC */ s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; qcom,switch-mode-frequency = <3200000>; regulator-always-on; }; @@ -349,9 +349,9 @@ reboot-mode { compatible = "syscon-reboot-mode"; offset = <0x65c>; - mode-normal = <0x77665501>; - mode-bootloader = <0x77665500>; - mode-recovery = <0x77665502>; + mode-normal = <0x77665501>; + mode-bootloader = <0x77665500>; + mode-recovery = <0x77665502>; }; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts index 7e57a0750320..e3bf57cd7423 100644 --- a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts +++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts @@ -82,8 +82,8 @@ s3 { }; s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; qcom,switch-mode-frequency = <3200000>; }; @@ -230,9 +230,9 @@ sdcc1: mmc@12400000 { sdcc3: mmc@12180000 { status = "okay"; vmmc-supply = <&v3p3_fixed>; - pinctrl-names = "default"; - pinctrl-0 = <&card_detect>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&card_detect>; + cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; }; /* WLAN */ sdcc4: mmc@121c0000 { diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 77e841243646..24eacf5afbf6 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -108,8 +108,8 @@ s3 { }; s4 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; qcom,switch-mode-frequency = <3200000>; }; @@ -240,8 +240,8 @@ sata_phy0: phy@1b400000 { }; sata0: sata@29000000 { - status = "okay"; - target-supply = <&pm8921_s4>; + status = "okay"; + target-supply = <&pm8921_s4>; }; /* OTG */ @@ -324,9 +324,9 @@ sdcc1: mmc@12400000 { sdcc3: mmc@12180000 { status = "okay"; vmmc-supply = <&pm8921_l6>; - pinctrl-names = "default"; - pinctrl-0 = <&card_detect>; - cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&card_detect>; + cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>; }; /* WLAN */ sdcc4: mmc@121c0000 { diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 028d52b5d075..452afcacd64d 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -430,8 +430,8 @@ saw3: power-controller@20b9000 { }; sps_sic_non_secure: sps-sic-non-secure@12100000 { - compatible = "syscon"; - reg = <0x12100000 0x10000>; + compatible = "syscon"; + reg = <0x12100000 0x10000>; }; gsbi1: gsbi@12440000 { @@ -836,22 +836,22 @@ mmcc: clock-controller@4000000 { }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; - reg = <0x2011000 0x1000>; + compatible = "qcom,kpss-gcc", "syscon"; + reg = <0x2011000 0x1000>; }; rpm@108000 { - compatible = "qcom,rpm-apq8064"; - reg = <0x108000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; + compatible = "qcom,rpm-apq8064"; + reg = <0x108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; - interrupts = , - , - ; - interrupt-names = "ack", "err", "wakeup"; + interrupts = , + , + ; + interrupt-names = "ack", "err", "wakeup"; rpmcc: clock-controller { - compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; + compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; #clock-cells = <1>; }; @@ -1004,39 +1004,39 @@ usb_hs4_phy: phy { }; sata_phy0: phy@1b400000 { - compatible = "qcom,apq8064-sata-phy"; - status = "disabled"; - reg = <0x1b400000 0x200>; - reg-names = "phy_mem"; - clocks = <&gcc SATA_PHY_CFG_CLK>; - clock-names = "cfg"; - #phy-cells = <0>; + compatible = "qcom,apq8064-sata-phy"; + status = "disabled"; + reg = <0x1b400000 0x200>; + reg-names = "phy_mem"; + clocks = <&gcc SATA_PHY_CFG_CLK>; + clock-names = "cfg"; + #phy-cells = <0>; }; sata0: sata@29000000 { - compatible = "qcom,apq8064-ahci", "generic-ahci"; - status = "disabled"; - reg = <0x29000000 0x180>; - interrupts = ; + compatible = "qcom,apq8064-ahci", "generic-ahci"; + status = "disabled"; + reg = <0x29000000 0x180>; + interrupts = ; - clocks = <&gcc SFAB_SATA_S_H_CLK>, - <&gcc SATA_H_CLK>, - <&gcc SATA_A_CLK>, - <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - clock-names = "slave_iface", - "iface", - "bus", - "rxoob", - "core_pmalive"; + clocks = <&gcc SFAB_SATA_S_H_CLK>, + <&gcc SATA_H_CLK>, + <&gcc SATA_A_CLK>, + <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + clock-names = "slave_iface", + "iface", + "bus", + "rxoob", + "core_pmalive"; - assigned-clocks = <&gcc SATA_RXOOB_CLK>, - <&gcc SATA_PMALIVE_CLK>; - assigned-clock-rates = <100000000>, <100000000>; + assigned-clocks = <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + assigned-clock-rates = <100000000>, <100000000>; - phys = <&sata_phy0>; - phy-names = "sata-phy"; - ports-implemented = <0x1>; + phys = <&sata_phy0>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; }; /* Temporary fixed regulator */ @@ -1076,18 +1076,18 @@ amba { #size-cells = <1>; ranges; sdcc1: mmc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; - pinctrl-names = "default"; - pinctrl-0 = <&sdcc1_pins>; + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + pinctrl-names = "default"; + pinctrl-0 = <&sdcc1_pins>; arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x2000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; + reg = <0x12400000 0x2000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; non-removable; cap-sd-highspeed; cap-mmc-highspeed; @@ -1096,36 +1096,36 @@ sdcc1: mmc@12400000 { }; sdcc3: mmc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x2000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; + status = "disabled"; + reg = <0x12180000 0x2000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <192000000>; + max-frequency = <192000000>; no-1-8-v; dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; dma-names = "tx", "rx"; }; sdcc4: mmc@121c0000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x121c0000 0x2000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; + status = "disabled"; + reg = <0x121c0000 0x2000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <48000000>; + max-frequency = <48000000>; dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; dma-names = "tx", "rx"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 4022ed9df988..4b475d98343c 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -1184,16 +1184,16 @@ amba: amba { ranges; sdcc1: mmc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x2000>; - interrupts = ; + reg = <0x12400000 0x2000>; + interrupts = ; interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; non-removable; cap-sd-highspeed; cap-mmc-highspeed; @@ -1204,18 +1204,18 @@ sdcc1: mmc@12400000 { }; sdcc3: mmc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x2000>; - interrupts = ; + status = "disabled"; + reg = <0x12180000 0x2000>; + interrupts = ; interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <192000000>; + max-frequency = <192000000>; sd-uhs-sdr104; sd-uhs-ddr50; vqmmc-supply = <&vsdcc_fixed>; diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index 0ce0d04bd994..b47c86412de2 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -362,7 +362,7 @@ sdcc1: mmc@12180000 { arm,primecell-periphid = <0x00051180>; reg = <0x12180000 0x2000>; interrupts = ; - interrupt-names = "cmd_irq"; + interrupt-names = "cmd_irq"; clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; clock-names = "mclk", "apb_pclk"; bus-width = <8>; @@ -382,7 +382,7 @@ sdcc2: mmc@12140000 { status = "disabled"; reg = <0x12140000 0x2000>; interrupts = ; - interrupt-names = "cmd_irq"; + interrupt-names = "cmd_irq"; clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; clock-names = "mclk", "apb_pclk"; bus-width = <4>; @@ -412,7 +412,7 @@ rpm: rpm@108000 { interrupts = , , ; - interrupt-names = "ack", "err", "wakeup"; + interrupt-names = "ack", "err", "wakeup"; regulators { compatible = "qcom,rpm-pm8018-regulators"; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 47b97daecef1..b9cded35b1cc 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -392,24 +392,24 @@ vibrator@4a { }; l2cc: clock-controller@2082000 { - compatible = "qcom,kpss-gcc", "syscon"; - reg = <0x02082000 0x1000>; + compatible = "qcom,kpss-gcc", "syscon"; + reg = <0x02082000 0x1000>; }; rpm: rpm@104000 { - compatible = "qcom,rpm-msm8660"; - reg = <0x00104000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; + compatible = "qcom,rpm-msm8660"; + reg = <0x00104000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; - interrupts = , - , - ; - interrupt-names = "ack", "err", "wakeup"; + interrupts = , + , + ; + interrupt-names = "ack", "err", "wakeup"; clocks = <&gcc RPM_MSG_RAM_H_CLK>; clock-names = "ram"; rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; + compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; #clock-cells = <1>; }; @@ -486,80 +486,80 @@ amba { #size-cells = <1>; ranges; sdcc1: mmc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <48000000>; + reg = <0x12400000 0x8000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; non-removable; cap-sd-highspeed; cap-mmc-highspeed; }; sdcc2: mmc@12140000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - reg = <0x12140000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <48000000>; + reg = <0x12140000 0x8000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; cap-sd-highspeed; cap-mmc-highspeed; }; sdcc3: mmc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; + status = "disabled"; + reg = <0x12180000 0x8000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <48000000>; + max-frequency = <48000000>; no-1-8-v; }; sdcc4: mmc@121c0000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x121c0000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; - max-frequency = <48000000>; + status = "disabled"; + reg = <0x121c0000 0x8000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + max-frequency = <48000000>; cap-sd-highspeed; cap-mmc-highspeed; }; sdcc5: mmc@12200000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12200000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; + status = "disabled"; + reg = <0x12200000 0x8000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <48000000>; + max-frequency = <48000000>; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 4a2d74cf01d2..19554f3b5196 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -148,19 +148,19 @@ clock-controller@4000000 { }; l2cc: clock-controller@2011000 { - compatible = "qcom,kpss-gcc", "syscon"; - reg = <0x2011000 0x1000>; + compatible = "qcom,kpss-gcc", "syscon"; + reg = <0x2011000 0x1000>; }; rpm@108000 { - compatible = "qcom,rpm-msm8960"; - reg = <0x108000 0x1000>; - qcom,ipc = <&l2cc 0x8 2>; + compatible = "qcom,rpm-msm8960"; + reg = <0x108000 0x1000>; + qcom,ipc = <&l2cc 0x8 2>; - interrupts = , - , - ; - interrupt-names = "ack", "err", "wakeup"; + interrupts = , + , + ; + interrupt-names = "ack", "err", "wakeup"; regulators { compatible = "qcom,rpm-pm8921-regulators"; @@ -268,16 +268,16 @@ amba { #size-cells = <1>; ranges; sdcc1: mmc@12400000 { - status = "disabled"; - compatible = "arm,pl18x", "arm,primecell"; + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - reg = <0x12400000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <8>; - max-frequency = <96000000>; + reg = <0x12400000 0x8000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; non-removable; cap-sd-highspeed; cap-mmc-highspeed; @@ -285,18 +285,18 @@ sdcc1: mmc@12400000 { }; sdcc3: mmc@12180000 { - compatible = "arm,pl18x", "arm,primecell"; + compatible = "arm,pl18x", "arm,primecell"; arm,primecell-periphid = <0x00051180>; - status = "disabled"; - reg = <0x12180000 0x8000>; - interrupts = ; - interrupt-names = "cmd_irq"; - clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; - clock-names = "mclk", "apb_pclk"; - bus-width = <4>; + status = "disabled"; + reg = <0x12180000 0x8000>; + interrupts = ; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; cap-sd-highspeed; cap-mmc-highspeed; - max-frequency = <192000000>; + max-frequency = <192000000>; no-1-8-v; vmmc-supply = <&vsdcc_fixed>; }; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts index 1c9f04322672..21d2c55c0465 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts @@ -78,9 +78,9 @@ &blsp1_uart2 { &imem { reboot-mode { - mode-normal = <0x77665501>; - mode-bootloader = <0x77665500>; - mode-recovery = <0x77665502>; + mode-normal = <0x77665501>; + mode-bootloader = <0x77665500>; + mode-recovery = <0x77665502>; }; }; From 9c17baaa97c89379cbd89e36115b7fb6aba43518 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 15 Jun 2022 17:53:18 -0700 Subject: [PATCH 27/48] ARM: dts: qcom: align gpio-key node names with dtschema The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220616005333.18491-25-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 4 ++-- arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts | 8 ++++---- arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi | 2 +- arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 4 ++-- arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 6 +++--- arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 4 ++-- arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi | 8 ++++---- arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts | 6 +++--- arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts | 6 +++--- .../dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts | 8 ++++---- 10 files changed, 28 insertions(+), 28 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index beb2058fd116..799cd0f8de40 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -44,12 +44,12 @@ ext_3p3v: regulator-fixed@1 { gpio-keys { compatible = "gpio-keys"; - volume_up { + key-volume-up { label = "Volume Up"; gpios = <&pm8921_gpio 4 GPIO_ACTIVE_HIGH>; linux,code = ; }; - volume_down { + key-volume-down { label = "Volume Down"; gpios = <&pm8921_gpio 38 GPIO_ACTIVE_HIGH>; linux,code = ; diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts index 3cf79cc5b539..c07c5474750d 100644 --- a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts +++ b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-lagan-yuga.dts @@ -23,28 +23,28 @@ gpio-keys { pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; - camera-focus { + key-camera-focus { label = "camera_focus"; gpios = <&pm8921_gpio 3 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = ; }; - camera-snapshot { + key-camera-snapshot { label = "camera_snapshot"; gpios = <&pm8921_gpio 4 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = ; }; - volume-down { + key-volume-down { label = "volume_down"; gpios = <&pm8921_gpio 29 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = ; }; - volume-up { + key-volume-up { label = "volume_up"; gpios = <&pm8921_gpio 35 GPIO_ACTIVE_LOW>; linux,input-type = <1>; diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi index 1f3b1ce82108..af9a26fb5d4a 100644 --- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dtsi @@ -11,7 +11,7 @@ / { keys { compatible = "gpio-keys"; - reset { + key-reset { label = "reset"; gpios = <&tlmm 63 GPIO_ACTIVE_LOW>; linux,code = ; diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts index 596d129d4a95..760151b52add 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts +++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts @@ -187,12 +187,12 @@ partition@0 { }; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-0 = <&buttons_pins>; pinctrl-names = "default"; - button@1 { + button { label = "reset"; linux,code = ; gpios = <&qcom_pinmux 66 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi index 5c802b99e15f..ccebb7d56113 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi @@ -65,19 +65,19 @@ sata@29000000 { status = "okay"; }; - gpio_keys { + gpio-keys { compatible = "gpio-keys"; pinctrl-0 = <&buttons_pins>; pinctrl-names = "default"; - button@1 { + button-1 { label = "reset"; linux,code = ; gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>; linux,input-type = <1>; debounce-interval = <60>; }; - button@2 { + button-2 { label = "wps"; linux,code = ; gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 4d8fc8689d24..b994474f83e6 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -24,14 +24,14 @@ gpio-keys { pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; - volume-up { + key-volume-up { label = "volume_up"; gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = ; }; - volume-down { + key-volume-down { label = "volume_down"; gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; linux,input-type = <1>; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi index a4fec2d0d158..d42b85bda33a 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi @@ -20,28 +20,28 @@ gpio-keys { pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; - volume-down { + key-volume-down { label = "volume_down"; gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = ; }; - camera-snapshot { + key-camera-snapshot { label = "camera_snapshot"; gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = ; }; - camera-focus { + key-camera-focus { label = "camera_focus"; gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = ; }; - volume-up { + key-volume-up { label = "volume_up"; gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; linux,input-type = <1>; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts index 21d2c55c0465..e1ae99579596 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-fairphone-fp2.dts @@ -25,7 +25,7 @@ gpio-keys { pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; - camera-snapshot { + key-camera-snapshot { label = "camera_snapshot"; gpios = <&pm8941_gpios 1 GPIO_ACTIVE_LOW>; linux,code = ; @@ -33,7 +33,7 @@ camera-snapshot { debounce-interval = <15>; }; - volume-down { + key-volume-down { label = "volume_down"; gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; linux,code = ; @@ -41,7 +41,7 @@ volume-down { debounce-interval = <15>; }; - volume-up { + key-volume-up { label = "volume_up"; gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; linux,code = ; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts index 90f7a399f40b..aa609312caf9 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts @@ -25,7 +25,7 @@ gpio-keys { pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; - volume-down { + key-volume-down { label = "volume_down"; gpios = <&pma8084_gpios 2 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -33,7 +33,7 @@ volume-down { debounce-interval = <15>; }; - home-key { + key-home { label = "home_key"; gpios = <&pma8084_gpios 3 GPIO_ACTIVE_LOW>; linux,input-type = <1>; @@ -42,7 +42,7 @@ home-key { debounce-interval = <15>; }; - volume-up { + key-volume-up { label = "volume_up"; gpios = <&pma8084_gpios 5 GPIO_ACTIVE_LOW>; linux,input-type = <1>; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts index e9bcd3b4ebb3..9fc696a7399a 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -24,28 +24,28 @@ gpio-keys { pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pin_a>; - volume-down { + key-volume-down { label = "volume_down"; gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = ; }; - camera-snapshot { + key-camera-snapshot { label = "camera_snapshot"; gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = ; }; - camera-focus { + key-camera-focus { label = "camera_focus"; gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; linux,input-type = <1>; linux,code = ; }; - volume-up { + key-volume-up { label = "volume_up"; gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; linux,input-type = <1>; From 4eb1560259de4fd5f89ec5e7faf5d4c6a83bae9c Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Tue, 17 May 2022 22:34:51 +0200 Subject: [PATCH 28/48] ARM: dts: qcom: msm8974: Add BAM DMUX Ethernet/IP device BAM DMUX is used as the network interface to the modem. Signed-off-by: Luca Weiss Reviewed-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220517203450.1155696-1-luca@z3ntu.xyz --- arch/arm/boot/dts/qcom-msm8974.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index df49be66d0b8..3ebcf08499f9 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1146,6 +1146,18 @@ spmi_bus: spmi@fc4cf000 { #interrupt-cells = <4>; }; + bam_dmux_dma: dma-controller@fc834000 { + compatible = "qcom,bam-v1.4.0"; + reg = <0xfc834000 0x7000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + + num-channels = <6>; + qcom,num-ees = <1>; + qcom,powered-remotely; + }; + remoteproc_mss: remoteproc@fc880000 { compatible = "qcom,msm8974-mss-pil"; reg = <0xfc880000 0x100>, <0xfc820000 0x020>; @@ -1180,6 +1192,20 @@ mpss { memory-region = <&mpss_region>; }; + bam_dmux: bam-dmux { + compatible = "qcom,bam-dmux"; + + interrupt-parent = <&modem_smsm>; + interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "pc", "pc-ack"; + + qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; + qcom,smem-state-names = "pc", "pc-ack"; + + dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; + dma-names = "tx", "rx"; + }; + smd-edge { interrupts = ; From ab1489017aa7a9f02e24bee73cf9ec8079cd3909 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Sun, 22 May 2022 10:36:18 +0200 Subject: [PATCH 29/48] ARM: dts: qcom-msm8974: fix irq type on blsp2_uart1 IRQ_TYPE_NONE is invalid, so use the correct interrupt type. Signed-off-by: Luca Weiss Fixes: b05f82b152c9 ("ARM: dts: qcom: msm8974: Add blsp2_uart7 for bluetooth on sirius") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220522083618.17894-1-luca@z3ntu.xyz --- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 3ebcf08499f9..96525f383d84 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -578,7 +578,7 @@ blsp2_dma: dma-controller@f9944000 { blsp2_uart1: serial@f995d000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf995d000 0x1000>; - interrupts = ; + interrupts = ; clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; status = "disabled"; From ae500b351ab0006d933d804a2b7507fe1e98cecc Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Mon, 30 May 2022 13:38:40 +0530 Subject: [PATCH 30/48] ARM: dts: qcom: sdx55: Fix the IRQ trigger type for UART The trigger type should be LEVEL_HIGH. So fix it! Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220530080842.37024-2-manivannan.sadhasivam@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index 1c2b208a5670..ef1da28f567c 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -206,7 +206,7 @@ gcc: clock-controller@100000 { blsp1_uart3: serial@831000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x00831000 0x200>; - interrupts = ; + interrupts = ; clocks = <&gcc 30>, <&gcc 9>; clock-names = "core", "iface"; From b8f9cae583c46ef6df0e643ec0022084d39769e7 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Jun 2022 12:29:22 +0200 Subject: [PATCH 31/48] ARM: dts: qcom: apq8060-dragonboard: add function and color to LED nodes Add common LED properties - the function and color - to LED nodes. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220607102931.102805-1-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-apq8060-dragonboard.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index a104acbfee05..70a1dd629c7a 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) #include #include +#include #include #include #include "qcom-msm8660.dtsi" @@ -416,6 +417,7 @@ led@131 { compatible = "qcom,pm8058-led"; reg = <0x131>; label = "pm8058:red"; + color = ; default-state = "off"; }; led@132 { @@ -426,6 +428,7 @@ led@132 { compatible = "qcom,pm8058-led"; reg = <0x132>; label = "pm8058:yellow"; + color = ; default-state = "off"; linux,default-trigger = "mmc0"; }; @@ -433,6 +436,8 @@ led@133 { compatible = "qcom,pm8058-led"; reg = <0x133>; label = "pm8058:green"; + function = LED_FUNCTION_HEARTBEAT; + color = ; default-state = "on"; linux,default-trigger = "heartbeat"; }; From 966d7e9c35cf3a759b51a490308ca5d83727569f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Jun 2022 12:29:23 +0200 Subject: [PATCH 32/48] ARM: dts: qcom: apq8060-ifc6410: add color to LED node Add common LED property - the color - to LED node. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220607102931.102805-2-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 24eacf5afbf6..dd534e303c8f 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-apq8064-v2.0.dtsi" #include +#include #include / { @@ -39,6 +40,7 @@ leds { led@1 { label = "apq8064:green:user1"; + color = ; gpios = <&pm8921_gpio 18 GPIO_ACTIVE_HIGH>; default-state = "on"; }; From 47e889d3d9a7da9542fd5d6f76c2b1ab2d22fcaa Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Jun 2022 12:29:24 +0200 Subject: [PATCH 33/48] ARM: dts: qcom: ipq4018-ap120c-ac: add function and color to LED nodes Add common LED properties - the function and color - to LED nodes. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220607102931.102805-3-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts | 6 ++++++ arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts | 7 +++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts index 028ac8e24797..cf7da1ab177c 100644 --- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts +++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dts @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT +#include #include "qcom-ipq4018-ap120c-ac.dtsi" / { @@ -10,17 +11,22 @@ leds { power { label = "ap120c-ac:green:power"; + function = LED_FUNCTION_POWER; + color = ; gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; default-state = "on"; }; wlan { label = "ap120c-ac:green:wlan"; + function = LED_FUNCTION_WLAN; + color = ; gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; }; support { label = "ap120c-ac:green:support"; + color = ; gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; panic-indicator; }; diff --git a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts index b7916fc26d68..c4f89b712fd9 100644 --- a/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts +++ b/arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dts @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT +#include #include "qcom-ipq4018-ap120c-ac.dtsi" / { @@ -8,18 +9,24 @@ leds { status: status { label = "ap120c-ac:blue:status"; + function = LED_FUNCTION_STATUS; + color = ; gpios = <&tlmm 5 GPIO_ACTIVE_LOW>; default-state = "keep"; }; wlan2g { label = "ap120c-ac:green:wlan2g"; + function = LED_FUNCTION_WLAN; + color = ; gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy0tpt"; }; wlan5g { label = "ap120c-ac:red:wlan5g"; + function = LED_FUNCTION_WLAN; + color = ; gpios = <&tlmm 2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "phy1tpt"; }; From 445c44e25342564326384640453d26d1655ebc44 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Jun 2022 12:29:25 +0200 Subject: [PATCH 34/48] ARM: dts: qcom: ipq8064-rb3011: add color to LED node Add common LED property - the color - to LED node. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220607102931.102805-4-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts index 760151b52add..9034f00f2bd8 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts +++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-ipq8064.dtsi" #include +#include / { model = "MikroTik RB3011UiAS-RM"; @@ -208,6 +209,7 @@ leds { led@7 { label = "rb3011:green:user"; + color = ; gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>; default-state = "off"; }; From 69b1142baeab4e1603a94b5e8c1676ecc911c9b5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Jun 2022 12:29:26 +0200 Subject: [PATCH 35/48] ARM: dts: qcom: ipq8064: add function to LED nodes Add common LED property - the function - to LED nodes. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220607102931.102805-5-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi index ccebb7d56113..411c8d63c38e 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 #include "qcom-ipq8064.dtsi" #include +#include / { model = "Qualcomm Technologies, Inc. IPQ8064-v1.0"; @@ -107,6 +108,7 @@ led@8 { led@9 { label = "status_led_fail"; + function = LED_FUNCTION_STATUS; gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>; default-state = "off"; }; @@ -119,6 +121,7 @@ led@26 { led@53 { label = "status_led_pass"; + function = LED_FUNCTION_STATUS; gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>; default-state = "off"; }; From 230b5edaa34b81d0f1de675ff17d8777f9f2d02b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Jun 2022 19:18:37 +0200 Subject: [PATCH 36/48] ARM: dts: qcom: use generic sram as name for imem and ocmem nodes According to Devicetree specification, the device nodes should be generic, reflecting the function of the device. The typical name for memory regions is "sram". Signed-off-by: Krzysztof Kozlowski Reviewed-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220607171848.535128-3-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 2 +- arch/arm/boot/dts/qcom-msm8974.dtsi | 4 ++-- arch/arm/boot/dts/qcom-sdx55.dtsi | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index 799cd0f8de40..f3618826f530 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -341,7 +341,7 @@ mmc@12400000 { }; }; - imem@2a03f000 { + sram@2a03f000 { compatible = "syscon", "simple-mfd"; reg = <0x2a03f000 0x1000>; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 96525f383d84..b834401fbae0 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1629,7 +1629,7 @@ opp-27000000 { }; }; - ocmem@fdd00000 { + sram@fdd00000 { compatible = "qcom,msm8974-ocmem"; reg = <0xfdd00000 0x2000>, <0xfec00000 0x180000>; @@ -1676,7 +1676,7 @@ smd-edge { }; }; - imem: imem@fe805000 { + imem: sram@fe805000 { compatible = "syscon", "simple-mfd"; reg = <0xfe805000 0x1000>; diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index ef1da28f567c..a6c50ca29bf7 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -561,7 +561,7 @@ tlmm: pinctrl@f100000 { #interrupt-cells = <2>; }; - imem@1468f000 { + sram@1468f000 { compatible = "simple-mfd"; reg = <0x1468f000 0x1000>; From 626a60292a8eb345df71b40ecaea54395ca8e618 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Jun 2022 19:18:38 +0200 Subject: [PATCH 37/48] ARM: dts: qcom: apq8064-asus-nexus7: add dedicated IMEM compatible syscon compatible must be preceded with a specific compatible, to accurately describe the device. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220607171848.535128-4-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index f3618826f530..fee278e32cb6 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -342,7 +342,7 @@ mmc@12400000 { }; sram@2a03f000 { - compatible = "syscon", "simple-mfd"; + compatible = "qcom,apq8064-imem", "syscon", "simple-mfd"; reg = <0x2a03f000 0x1000>; reboot-mode { From f19be941efd19b6c68eef87a2d4a1942e4ebd493 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Jun 2022 19:18:39 +0200 Subject: [PATCH 38/48] ARM: dts: qcom: msm8974: add dedicated IMEM compatible syscon compatible must be preceded with a specific compatible, to accurately describe the device. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220607171848.535128-5-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index b834401fbae0..ce8a5207579b 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1677,7 +1677,7 @@ smd-edge { }; imem: sram@fe805000 { - compatible = "syscon", "simple-mfd"; + compatible = "qcom,msm8974-imem", "syscon", "simple-mfd"; reg = <0xfe805000 0x1000>; reboot-mode { From def2565bc66da3e9643f71b2be5f8e707cbdebd0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Jun 2022 19:18:40 +0200 Subject: [PATCH 39/48] ARM: dts: qcom: sdx55: add dedicated IMEM and syscon compatibles Add proper compatibles to the IMEM device node: 1. syscon to allow accessing memory from other devices, 2. dedicated compatible as required for syscon and simple-mfd nodes. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220607171848.535128-6-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-sdx55.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index a6c50ca29bf7..f37091143ac5 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -562,7 +562,7 @@ tlmm: pinctrl@f100000 { }; sram@1468f000 { - compatible = "simple-mfd"; + compatible = "qcom,sdx55-imem", "syscon", "simple-mfd"; reg = <0x1468f000 0x1000>; #address-cells = <1>; From 7a16ea7f3a5ec0f30b146b058c273b7a9c8ceadf Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Jun 2022 19:18:41 +0200 Subject: [PATCH 40/48] ARM: dts: qcom: msm8974: add required ranges to OCMEM The OCMEM bindings require ranges property. Fixes: a2cc991ed634 ("ARM: dts: qcom: msm8974: add ocmem node") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Luca Weiss Tested-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220607171848.535128-7-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-msm8974.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index ce8a5207579b..5e3ad97c579e 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1634,6 +1634,7 @@ sram@fdd00000 { reg = <0xfdd00000 0x2000>, <0xfec00000 0x180000>; reg-names = "ctrl", "mem"; + ranges = <0 0xfec00000 0x180000>; clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, <&mmcc OCMEMCX_OCMEMNOC_CLK>; clock-names = "core", "iface"; From e2759fa0676c9a32bbddb9aff955b54bb35066ad Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 8 Jun 2022 13:27:02 +0200 Subject: [PATCH 41/48] ARM: dts: qcom: pm8841: add required thermal-sensor-cells The PM8841 temperature sensor has to define thermal-sensor-cells. Fixes: dab8134ca072 ("ARM: dts: qcom: Add PM8841 functions device nodes") Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220608112702.80873-2-krzysztof.kozlowski@linaro.org --- arch/arm/boot/dts/qcom-pm8841.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom-pm8841.dtsi b/arch/arm/boot/dts/qcom-pm8841.dtsi index 2caf71eacb52..b5cdde034d18 100644 --- a/arch/arm/boot/dts/qcom-pm8841.dtsi +++ b/arch/arm/boot/dts/qcom-pm8841.dtsi @@ -24,6 +24,7 @@ temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; interrupts = <4 0x24 0 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; }; }; From 6ac2799c3096dc2fe6d65026efa8a6cf212976bd Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 9 Jun 2022 15:23:40 +0300 Subject: [PATCH 42/48] ARM: dts: qcom: apq8064-ifc6410: drop hdmi-mux-supply The HDMI circuitry on the IFC6410 is not powered by the 3v3. Drop the hdmi-mux-supply property. Reviewed-by: Stephen Boyd Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220609122350.3157529-5-dmitry.baryshkov@linaro.org --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index dd534e303c8f..0322cb88d448 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -343,7 +343,6 @@ hdmi-tx@4a00000 { status = "okay"; core-vdda-supply = <&pm8921_hdmi_switch>; - hdmi-mux-supply = <&ext_3p3v>; hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>; From fe5651cc8e33b5fcdc351e36cd0cd4bff2f6192f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 9 Jun 2022 15:23:49 +0300 Subject: [PATCH 43/48] ARM: dts: qcom: apq8064: drop phy-names from HDMI device node The HDMI driver doesn't use the phy-names to identify the PHY. Different Qualcomm platforms have used different names for the PHY. So, we are deprecating phy-names propertty of the HDMI device and dropping them from existing DTs. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220609122350.3157529-14-dmitry.baryshkov@linaro.org --- arch/arm/boot/dts/qcom-apq8064.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 452afcacd64d..91adcbd54b17 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1420,7 +1420,6 @@ hdmi: hdmi-tx@4a00000 { "slave_iface"; phys = <&hdmi_phy>; - phy-names = "hdmi-phy"; ports { #address-cells = <1>; From 2477d81901a23ad80045798edbeb7f91b5ff6143 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sun, 15 May 2022 03:24:19 +0530 Subject: [PATCH 44/48] ARM: dts: qcom: Fix sdhci node names - use 'mmc@' Since the Qualcomm sdhci-msm device-tree binding has been converted to yaml format, 'make dtbs_check' reports issues with inconsistent 'sdhci@' convention used for specifying the sdhci nodes. The generic mmc bindings expect 'mmc@' format instead. Fix the same. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma [bjorn: Extracted from combined arm64 patch] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220514215424.1007718-2-bhupesh.sharma@linaro.org --- arch/arm/boot/dts/qcom-apq8084.dtsi | 4 ++-- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +- arch/arm/boot/dts/qcom-msm8226.dtsi | 6 +++--- arch/arm/boot/dts/qcom-msm8974.dtsi | 6 +++--- arch/arm/boot/dts/qcom-sdx55.dtsi | 2 +- arch/arm/boot/dts/qcom-sdx65.dtsi | 2 +- 6 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index cb01faa23eb7..3e8bded2b5c8 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -419,7 +419,7 @@ blsp2_uart2: serial@f995e000 { status = "disabled"; }; - sdhci@f9824900 { + mmc@f9824900 { compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -432,7 +432,7 @@ sdhci@f9824900 { status = "disabled"; }; - sdhci@f98a4900 { + mmc@f98a4900 { compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc_mem", "core_mem"; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index c5da723f7674..a2632349cec4 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -221,7 +221,7 @@ vqmmc: regulator@1948000 { status = "disabled"; }; - sdhci: sdhci@7824900 { + sdhci: mmc@7824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0x7824900 0x11c>, <0x7824000 0x800>; interrupts = , ; diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index 28eca15b5712..0b5effdb269a 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -134,7 +134,7 @@ apcs: syscon@f9011000 { reg = <0xf9011000 0x1000>; }; - sdhc_1: sdhci@f9824900 { + sdhc_1: mmc@f9824900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -150,7 +150,7 @@ sdhc_1: sdhci@f9824900 { status = "disabled"; }; - sdhc_2: sdhci@f98a4900 { + sdhc_2: mmc@f98a4900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -166,7 +166,7 @@ sdhc_2: sdhci@f98a4900 { status = "disabled"; }; - sdhc_3: sdhci@f9864900 { + sdhc_3: mmc@f9864900 { compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; reg-names = "hc_mem", "core_mem"; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 5e3ad97c579e..8131d3e222cb 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -436,7 +436,7 @@ acc3: clock-controller@f90b8000 { reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; }; - sdhc_1: sdhci@f9824900 { + sdhc_1: mmc@f9824900 { compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -453,7 +453,7 @@ sdhc_1: sdhci@f9824900 { status = "disabled"; }; - sdhc_3: sdhci@f9864900 { + sdhc_3: mmc@f9864900 { compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -472,7 +472,7 @@ sdhc_3: sdhci@f9864900 { status = "disabled"; }; - sdhc_2: sdhci@f98a4900 { + sdhc_2: mmc@f98a4900 { compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc_mem", "core_mem"; diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index f37091143ac5..c72540223fa9 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -388,7 +388,7 @@ tcsr: syscon@1fcb000 { reg = <0x01fc0000 0x1000>; }; - sdhc_1: sdhci@8804000 { + sdhc_1: mmc@8804000 { compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>; interrupts = , diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 1881b6d2485b..7a193678b4f5 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -331,7 +331,7 @@ glink-edge { }; }; - sdhc_1: sdhci@8804000 { + sdhc_1: mmc@8804000 { compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; reg = <0x08804000 0x1000>; reg-names = "hc_mem"; From 363c1b04cfce5615f2dc1b7f19e4456937ed2068 Mon Sep 17 00:00:00 2001 From: David Heidelberg Date: Sun, 26 Jun 2022 20:32:45 +0200 Subject: [PATCH 45/48] ARM: dts: qcom: extend scm compatible to match dt-schema First device specific compatible, then general one. Reviewed-by: Krzysztof Kozlowski Signed-off-by: David Heidelberg Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220626183247.142776-1-david@ixit.cz --- arch/arm/boot/dts/qcom-apq8064.dtsi | 2 +- arch/arm/boot/dts/qcom-apq8084.dtsi | 2 +- arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 91adcbd54b17..38f6077d4c66 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -315,7 +315,7 @@ dsps_smsm: dsps@4 { firmware { scm { - compatible = "qcom,scm-apq8064"; + compatible = "qcom,scm-apq8064", "qcom,scm"; clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; clock-names = "core"; diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 3e8bded2b5c8..72f9255855a1 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -95,7 +95,7 @@ memory { firmware { scm { - compatible = "qcom,scm"; + compatible = "qcom,scm-apq8084", "qcom,scm"; clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; clock-names = "core", "bus", "iface"; }; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index a2632349cec4..bb307b8f678c 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -156,7 +156,7 @@ xo: xo { firmware { scm { - compatible = "qcom,scm-ipq4019"; + compatible = "qcom,scm-ipq4019", "qcom,scm"; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 8131d3e222cb..af318c104cdd 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -96,7 +96,7 @@ CPU_SPC: spc { firmware { scm { - compatible = "qcom,scm"; + compatible = "qcom,scm-msm8974", "qcom,scm"; clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; clock-names = "core", "bus", "iface"; }; From 9c10bb43db82bc9289af50c39cc940aff79b7aed Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 6 Jul 2022 17:54:10 +0300 Subject: [PATCH 46/48] ARM: dts: qcom: apq8064: rename DSI PHY iface clock Follow the usual scheme and use name 'iface' rather than 'iface_clk' for the interface clock. The DSI PHY driver can cope with both of them, so there is no breakage. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220706145412.1566011-4-dmitry.baryshkov@linaro.org --- arch/arm/boot/dts/qcom-apq8064.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 38f6077d4c66..298df0813969 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1299,7 +1299,7 @@ dsi0_phy: dsi-phy@4700200 { <0x04700300 0x200>, <0x04700500 0x5c>; reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; - clock-names = "iface_clk", "ref"; + clock-names = "iface", "ref"; clocks = <&mmcc DSI_M_AHB_CLK>, <&pxo_board>; }; From d8e51f13c31c585caf6a9497627ecad14e78211b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 6 Jul 2022 17:54:11 +0300 Subject: [PATCH 47/48] ARM: dts: qcom: apq8064: disable DSI and DSI PHY by default Disable DSI and DSI PHY devices by default. The only actual user, Nexus 7, already contains `status = "okay"` property in the respective devices nodes. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220706145412.1566011-5-dmitry.baryshkov@linaro.org --- arch/arm/boot/dts/qcom-apq8064.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 298df0813969..cc3882977483 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -1271,6 +1271,8 @@ dsi0: dsi@4700000 { syscon-sfpb = <&mmss_sfpb>; phys = <&dsi0_phy>; phy-names = "dsi"; + status = "disabled"; + ports { #address-cells = <1>; #size-cells = <0>; @@ -1302,6 +1304,7 @@ dsi0_phy: dsi-phy@4700200 { clock-names = "iface", "ref"; clocks = <&mmcc DSI_M_AHB_CLK>, <&pxo_board>; + status = "disabled"; }; From 864cfdeb76735909a9afcc314416ccaa1ce82a1a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Wed, 6 Jul 2022 17:54:12 +0300 Subject: [PATCH 48/48] ARM: dts: qcom: msm8974: rename GPU's OPP table node Rename the GPU's opp table node to make it follow the display/msm/gpu.yaml schema. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220706145412.1566011-6-dmitry.baryshkov@linaro.org --- arch/arm/boot/dts/qcom-msm8974.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index af318c104cdd..d944c6272c37 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1612,7 +1612,7 @@ gpu: adreno@fdb00000 { status = "disabled"; - gpu_opp_table: opp_table { + gpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-320000000 {