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drm/i915/dram: Sort SKL+ DIMM register bits

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Use the customary big endian order when defining the
SKL/ICL DIMM registers.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patch.msgid.link/20251029204215.12292-3-ville.syrjala@linux.intel.com
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
This commit is contained in:
Ville Syrjälä 2025-10-29 22:42:14 +02:00
parent 5b23aa423a
commit 8c171a9b8c
1 changed files with 9 additions and 9 deletions
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18
drivers/gpu/drm/i915/intel_mchbar_regs.h
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@ -161,24 +161,24 @@
#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
#define SKL_DRAM_S_SHIFT 16
#define SKL_DRAM_SIZE_MASK REG_GENMASK(5, 0)
#define SKL_DRAM_RANK_MASK REG_GENMASK(10, 10)
#define SKL_DRAM_RANK_1 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 0)
#define SKL_DRAM_RANK_2 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 1)
#define SKL_DRAM_WIDTH_MASK REG_GENMASK(9, 8)
#define SKL_DRAM_WIDTH_X8 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 0)
#define SKL_DRAM_WIDTH_X16 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 1)
#define SKL_DRAM_WIDTH_X32 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 2)
#define SKL_DRAM_RANK_MASK REG_GENMASK(10, 10)
#define SKL_DRAM_RANK_1 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 0)
#define SKL_DRAM_RANK_2 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 1)
#define ICL_DRAM_SIZE_MASK REG_GENMASK(6, 0)
#define ICL_DRAM_WIDTH_MASK REG_GENMASK(8, 7)
#define ICL_DRAM_WIDTH_X8 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 0)
#define ICL_DRAM_WIDTH_X16 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 1)
#define ICL_DRAM_WIDTH_X32 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 2)
#define SKL_DRAM_SIZE_MASK REG_GENMASK(5, 0)
#define ICL_DRAM_RANK_MASK REG_GENMASK(10, 9)
#define ICL_DRAM_RANK_1 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 0)
#define ICL_DRAM_RANK_2 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 1)
#define ICL_DRAM_RANK_3 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 2)
#define ICL_DRAM_RANK_4 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 3)
#define ICL_DRAM_WIDTH_MASK REG_GENMASK(8, 7)
#define ICL_DRAM_WIDTH_X8 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 0)
#define ICL_DRAM_WIDTH_X16 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 1)
#define ICL_DRAM_WIDTH_X32 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 2)
#define ICL_DRAM_SIZE_MASK REG_GENMASK(6, 0)
#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
#define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2)