From 9b663b34c94a78f39fa2c7a8271b1f828b546e16 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Wed, 18 Aug 2021 09:02:08 +0200 Subject: [PATCH 01/42] ARM: dts: imx6dl-yapp4: Fix lp5562 LED driver probe MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since the LED multicolor framework support was added in commit 92a81562e695 ("leds: lp55xx: Add multicolor framework support to lp55xx") LEDs on this platform stopped working. Author of the framework attempted to accommodate this DT to the framework in commit b86d3d21cd4c ("ARM: dts: imx6dl-yapp4: Add reg property to the lp5562 channel node") but that is not sufficient. A color property is now required even if the multicolor framework is not used, otherwise the driver probe fails: lp5562: probe of 1-0030 failed with error -22 Add the color property to fix this. Fixes: 92a81562e695 ("leds: lp55xx: Add multicolor framework support to lp55xx") Cc: Cc: linux-leds@vger.kernel.org Signed-off-by: Michal Vokáč Acked-by: Pavel Machek Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-yapp4-common.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi index cb8b539eb29d..e5c4dc65fbab 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi +++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi @@ -5,6 +5,7 @@ #include #include #include +#include #include / { @@ -277,6 +278,7 @@ chan@0 { led-cur = /bits/ 8 <0x20>; max-cur = /bits/ 8 <0x60>; reg = <0>; + color = ; }; chan@1 { @@ -284,6 +286,7 @@ chan@1 { led-cur = /bits/ 8 <0x20>; max-cur = /bits/ 8 <0x60>; reg = <1>; + color = ; }; chan@2 { @@ -291,6 +294,7 @@ chan@2 { led-cur = /bits/ 8 <0x20>; max-cur = /bits/ 8 <0x60>; reg = <2>; + color = ; }; chan@3 { @@ -298,6 +302,7 @@ chan@3 { led-cur = /bits/ 8 <0x0>; max-cur = /bits/ 8 <0x0>; reg = <3>; + color = ; }; }; From 417a9845706f81dbed71db380edd48c2118a048f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michal=20Vok=C3=A1=C4=8D?= Date: Wed, 18 Aug 2021 09:02:09 +0200 Subject: [PATCH 02/42] ARM: dts: imx6dl-yapp4: Remove the unused white LED channel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since the reg property was added to each channel node in commit b86d3d21cd4c ("ARM: dts: imx6dl-yapp4: Add reg property to the lp5562 channel node") it is possible to skip unused channels. Remove the actually unused white LED channel. Signed-off-by: Michal Vokáč Acked-by: Pavel Machek Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-yapp4-common.dtsi | 8 -------- 1 file changed, 8 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi index e5c4dc65fbab..674af39c884a 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi +++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi @@ -296,14 +296,6 @@ chan@2 { reg = <2>; color = ; }; - - chan@3 { - chan-name = "W"; - led-cur = /bits/ 8 <0x0>; - max-cur = /bits/ 8 <0x0>; - reg = <3>; - color = ; - }; }; eeprom@57 { From 97eb19d884831c5b2ebe423cd54137ba9793ea6c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 16 Jul 2021 10:36:56 -0300 Subject: [PATCH 03/42] ARM: dts: imx6dl-alti6p: Fix the SPI chipselect polarity The conversion of the spi-imx driver to use GPIO descriptors in commit 8cdcd8aeee28 ("spi: imx/fsl-lpspi: Convert to GPIO descriptors") helped to detect the following SPI chipselect polarity mismatch on an imx6q-sabresd for example: [ 4.854337] m25p80@0 enforce active low on chipselect handle Prior to the above commit, the chipselect polarity passed via cs-gpios property was ignored and considered active-low. The reason for such mismatch is clearly explained in the comments inside drivers/gpio/gpiolib-of.c: * SPI children have active low chip selects * by default. This can be specified negatively * by just omitting "spi-cs-high" in the * device node, or actively by tagging on * GPIO_ACTIVE_LOW as flag in the device * tree. If the line is simultaneously * tagged as active low in the device tree * and has the "spi-cs-high" set, we get a * conflict and the "spi-cs-high" flag will * take precedence. To properly represent the SPI chipselect polarity, change it to active-low when the "spi-cs-high" property is absent. Signed-off-by: Fabio Estevam Reviewed-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-alti6p.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-alti6p.dts b/arch/arm/boot/dts/imx6dl-alti6p.dts index 4329b372d8cb..e8325fd680d9 100644 --- a/arch/arm/boot/dts/imx6dl-alti6p.dts +++ b/arch/arm/boot/dts/imx6dl-alti6p.dts @@ -192,7 +192,7 @@ &can1 { }; &ecspi1 { - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; From 70b211ddcf9df5df288fcf648a032394cb3b84f0 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 16 Jul 2021 10:36:57 -0300 Subject: [PATCH 04/42] ARM: dts: imx6qp-prtwd3: Fix the SPI chipselect polarity The conversion of the spi-imx driver to use GPIO descriptors in commit 8cdcd8aeee28 ("spi: imx/fsl-lpspi: Convert to GPIO descriptors") helped to detect the following SPI chipselect polarity mismatch on an imx6q-sabresd for example: [ 4.854337] m25p80@0 enforce active low on chipselect handle Prior to the above commit, the chipselect polarity passed via cs-gpios property was ignored and considered active-low. The reason for such mismatch is clearly explained in the comments inside drivers/gpio/gpiolib-of.c: * SPI children have active low chip selects * by default. This can be specified negatively * by just omitting "spi-cs-high" in the * device node, or actively by tagging on * GPIO_ACTIVE_LOW as flag in the device * tree. If the line is simultaneously * tagged as active low in the device tree * and has the "spi-cs-high" set, we get a * conflict and the "spi-cs-high" flag will * take precedence. To properly represent the SPI chipselect polarity, change it to active-low when the "spi-cs-high" property is absent. Signed-off-by: Fabio Estevam Reviewed-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qp-prtwd3.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qp-prtwd3.dts b/arch/arm/boot/dts/imx6qp-prtwd3.dts index b92e0f2748a5..7648e8a02000 100644 --- a/arch/arm/boot/dts/imx6qp-prtwd3.dts +++ b/arch/arm/boot/dts/imx6qp-prtwd3.dts @@ -123,7 +123,7 @@ &can1 { }; &ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio2 26 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; status = "okay"; @@ -189,7 +189,7 @@ fixed-link { }; &ecspi3 { - cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; status = "okay"; From e40d0706bff5737f9ebe553cc8e88cec8c96bec0 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 16 Jul 2021 10:36:58 -0300 Subject: [PATCH 05/42] ARM: dts: imx6qdl-tqma6: Fix the SPI chipselect polarity The conversion of the spi-imx driver to use GPIO descriptors in commit 8cdcd8aeee28 ("spi: imx/fsl-lpspi: Convert to GPIO descriptors") helped to detect the following SPI chipselect polarity mismatch on an imx6q-sabresd for example: [ 4.854337] m25p80@0 enforce active low on chipselect handle Prior to the above commit, the chipselect polarity passed via cs-gpios property was ignored and considered active-low. The reason for such mismatch is clearly explained in the comments inside drivers/gpio/gpiolib-of.c: * SPI children have active low chip selects * by default. This can be specified negatively * by just omitting "spi-cs-high" in the * device node, or actively by tagging on * GPIO_ACTIVE_LOW as flag in the device * tree. If the line is simultaneously * tagged as active low in the device tree * and has the "spi-cs-high" set, we get a * conflict and the "spi-cs-high" flag will * take precedence. To properly represent the SPI chipselect polarity, change it to active-low when the "spi-cs-high" property is absent. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-tqma6.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-tqma6.dtsi b/arch/arm/boot/dts/imx6qdl-tqma6.dtsi index b18b83ac6aee..51a3a5392c95 100644 --- a/arch/arm/boot/dts/imx6qdl-tqma6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tqma6.dtsi @@ -20,7 +20,7 @@ reg_3p3v: regulator-3p3v { &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; status = "okay"; m25p80: flash@0 { From 6c4183287a7376e2da4087ccdca1118ca8e34b69 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 16 Jul 2021 10:36:59 -0300 Subject: [PATCH 06/42] ARM: dts: imx7d-sdb: Fix the SPI chipselect polarity The following warning is seen when the SPI GPIO driver probes: gpio-expander@0 enforce active low on chipselect handle The reason for this warning is clearly explained in the comments inside drivers/gpio/gpiolib-of.c: * SPI children have active low chip selects * by default. This can be specified negatively * by just omitting "spi-cs-high" in the * device node, or actively by tagging on * GPIO_ACTIVE_LOW as flag in the device * tree. If the line is simultaneously * tagged as active low in the device tree * and has the "spi-cs-high" set, we get a * conflict and the "spi-cs-high" flag will * take precedence. To properly represent the SPI chipselect polarity, change it to active-low when the "spi-cs-high" property is absent. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d-sdb.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 4a0d83784d7d..7813ef960f6e 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -45,7 +45,7 @@ spi4 { pinctrl-0 = <&pinctrl_spi4>; gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>; gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; num-chipselects = <1>; #address-cells = <1>; #size-cells = <0>; From 63651ef23f76fd5b1add4221e61677cccb2e203e Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Fri, 27 Aug 2021 14:42:59 +0800 Subject: [PATCH 07/42] ARM: dts: imx: fix the schema check errors - ranges property should be grouped by region, with no functional changes. Otherwise, schema dtbs_check would report the following errors. "linux-imx/arch/arm/boot/dts/imx6qp-vicutp.dt.yaml: pcie@1ffc000: ranges: 'oneOf' conditional failed, one must be fixed: linux-imx/arch/arm/boot/dts/imx6qp-vicutp.dt.yaml: pcie@1ffc000: ranges: 'oneOf' conditional failed, one must be fixed: [[2164260864, 0, 0, 33030144, 0, 65536, 2181038080, 0, 16777216, 16777216, 0, 15728640]] is not of type 'boolean' True was expected [[2164260864, 0, 0, 33030144, 0, 65536, 2181038080, 0, 16777216, 16777216, 0, 15728640]] is not of type 'null' [2164260864, 0, 0, 33030144, 0, 65536, 2181038080, 0, 16777216, 16777216, 0, 15728640] is too long From schema: linux-imx/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml" - refer to commit 281f1f99cf3a ("PCI: dwc: Detect number of iATU windows"). The num-viewport is not required anymore, remove them totally. - dt_binding_check complains "compatible: ['fsl,imx6qp-pcie', 'snps,dw-pcie'] is too long", remove "snps,dw-pcie" from the compatible string. Signed-off-by: Richard Zhu Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 7 +++---- arch/arm/boot/dts/imx6qp.dtsi | 2 +- arch/arm/boot/dts/imx6sx.dtsi | 6 +++--- arch/arm/boot/dts/imx7d.dtsi | 7 +++---- 4 files changed, 10 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 89c342f3a7c2..f5de5def876d 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -264,7 +264,7 @@ L2: cache-controller@a02000 { }; pcie: pcie@1ffc000 { - compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; + compatible = "fsl,imx6q-pcie"; reg = <0x01ffc000 0x04000>, <0x01f00000 0x80000>; reg-names = "dbi", "config"; @@ -272,10 +272,9 @@ pcie: pcie@1ffc000 { #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0 0 0x01f80000 0 0x00010000>, /* downstream I/O */ + <0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>; - num-viewport = <4>; interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi index b310f13a53f2..050365513836 100644 --- a/arch/arm/boot/dts/imx6qp.dtsi +++ b/arch/arm/boot/dts/imx6qp.dtsi @@ -110,5 +110,5 @@ &mmdc0 { }; &pcie { - compatible = "fsl,imx6qp-pcie", "snps,dw-pcie"; + compatible = "fsl,imx6qp-pcie"; }; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 8516730778df..fc6334336b3d 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -1395,15 +1395,15 @@ pwm8: pwm@22b0000 { }; pcie: pcie@8ffc000 { - compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; + compatible = "fsl,imx6sx-pcie"; reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>; reg-names = "dbi", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0 0 0x08f80000 0 0x00010000>, /* downstream I/O */ + <0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>; interrupts = ; interrupt-names = "msi"; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index b0bcfa9094a3..b7735979b7e4 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -164,7 +164,7 @@ fec2: ethernet@30bf0000 { }; pcie: pcie@33800000 { - compatible = "fsl,imx7d-pcie", "snps,dw-pcie"; + compatible = "fsl,imx7d-pcie"; reg = <0x33800000 0x4000>, <0x4ff00000 0x80000>; reg-names = "dbi", "config"; @@ -172,10 +172,9 @@ pcie: pcie@33800000 { #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */ - 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000>, /* downstream I/O */ + <0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ num-lanes = <1>; - num-viewport = <4>; interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; From d555a229025de569afe071751ec2d06565cbac06 Mon Sep 17 00:00:00 2001 From: Yunus Bas Date: Thu, 9 Sep 2021 19:25:55 +0200 Subject: [PATCH 08/42] ARM: dts: imx6: phycore-som: Disable micro-SD write protection The micro-SD card doesn't feature a write-protect pin. Set the corresponding property in the devicetree to handle this behavior correctly and suppress driver warnings. Signed-off-by: Yunus Bas Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi | 1 + arch/arm/boot/dts/imx6ul-phytec-segin.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi index 019938562aa9..0873f53ea275 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi @@ -256,6 +256,7 @@ &usdhc1 { pinctrl-0 = <&pinctrl_usdhc1>; cd-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>; no-1-8-v; + disable-wp; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi index 95e4080dd0a6..0d4ba9494cf2 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-segin.dtsi @@ -191,6 +191,7 @@ &usdhc1 { no-1-8-v; keep-power-in-suspend; wakeup-source; + disable-wp; status = "disabled"; }; From 23b72e1340996da0a7021b2395a58d94ab09090e Mon Sep 17 00:00:00 2001 From: Max Krummenacher Date: Mon, 20 Sep 2021 16:49:37 +0200 Subject: [PATCH 09/42] ARM: dts: colibri-imx6ull-emmc: add device tree Add a device tree for a Colibri iMX6ULL 1GB which has a eMMC instead of the raw NAND used on other SKUs. Signed-off-by: Max Krummenacher Signed-off-by: Marcel Ziswiler Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/imx6ull-colibri-emmc-eval-v3.dts | 17 ++ .../dts/imx6ull-colibri-emmc-nonwifi.dtsi | 185 ++++++++++++++++++ arch/arm/boot/dts/imx6ull-colibri.dtsi | 32 ++- 4 files changed, 233 insertions(+), 2 deletions(-) create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-eval-v3.dts create mode 100644 arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7e0934180724..f88ddcc40b6a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -671,6 +671,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ imx6ull-14x14-evk.dtb \ + imx6ull-colibri-emmc-eval-v3.dtb \ imx6ull-colibri-eval-v3.dtb \ imx6ull-colibri-wifi-eval-v3.dtb \ imx6ull-myir-mys-6ulx-eval.dtb \ diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-emmc-eval-v3.dts new file mode 100644 index 000000000000..61b93cb040c7 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-eval-v3.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2021 Toradex + */ + +/dts-v1/; + +#include "imx6ull-colibri-emmc-nonwifi.dtsi" +#include "imx6ull-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 1GB (eMMC) on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx6ull-emmc-eval", + "toradex,colibri-imx6ull-emmc", + "toradex,colibri-imx6ull", + "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi new file mode 100644 index 000000000000..a099abfdfa27 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-emmc-nonwifi.dtsi @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2021 Toradex + */ + +#include "imx6ull-colibri.dtsi" + +/ { + aliases { + mmc0 = &usdhc2; /* eMMC */ + mmc1 = &usdhc1; /* MMC 4bit slot */ + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + +&gpio1 { + gpio-line-names = "SODIMM_8", + "SODIMM_6", + "SODIMM_129", + "SODIMM_89", + "SODIMM_19", + "SODIMM_21", + "UNUSABLE_SODIMM_180", + "UNUSABLE_SODIMM_184", + "SODIMM_4", + "SODIMM_2", + "SODIMM_106", + "SODIMM_71", + "SODIMM_23", + "SODIMM_31", + "SODIMM_99", + "SODIMM_102", + "SODIMM_33", + "SODIMM_35", + "SODIMM_25", + "SODIMM_27", + "SODIMM_36", + "SODIMM_38", + "SODIMM_32", + "SODIMM_34", + "SODIMM_135", + "SODIMM_77", + "SODIMM_100", + "SODIMM_186", + "SODIMM_196", + "SODIMM_194"; +}; + +&gpio2 { + gpio-line-names = "SODIMM_55", + "SODIMM_63", + "SODIMM_178", + "SODIMM_188", + "SODIMM_73", + "SODIMM_30", + "SODIMM_67", + "SODIMM_104", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_190", + "SODIMM_47", + "SODIMM_192", + "SODIMM_49", + "SODIMM_51", + "SODIMM_53"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_56", + "SODIMM_44", + "SODIMM_68", + "SODIMM_82", + "", + "SODIMM_76", + "SODIMM_70", + "SODIMM_60", + "SODIMM_58", + "SODIMM_78", + "SODIMM_72", + "SODIMM_80", + "SODIMM_46", + "SODIMM_62", + "SODIMM_48", + "SODIMM_74", + "SODIMM_50", + "SODIMM_52", + "SODIMM_54", + "SODIMM_66", + "SODIMM_64", + "SODIMM_57", + "SODIMM_61", + "SODIMM_29", + "SODIMM_37", + "SODIMM_88", + "SODIMM_86", + "SODIMM_92", + "SODIMM_90"; +}; + +&gpio4 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_140", + "SODIMM_59", + "SODIMM_142", + "SODIMM_144", + "SODIMM_133", + "SODIMM_146", + "SODIMM_28", + "SODIMM_75", + "SODIMM_96", + "SODIMM_81", + "SODIMM_94", + "SODIMM_101", + "SODIMM_103", + "SODIMM_79", + "SODIMM_97", + "SODIMM_69", + "SODIMM_98", + "SODIMM_85", + "SODIMM_65"; +}; + +&gpio5 { + gpio-line-names = "SODIMM_43", + "SODIMM_45", + "SODIMM_137", + "SODIMM_95", + "SODIMM_107", + "SODIMM_131", + "SODIMM_93", + "", + "SODIMM_138", + "", + "SODIMM_105", + "SODIMM_127"; +}; + +&gpmi { + status = "disabled"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 + &pinctrl_gpio4 &pinctrl_gpio6 &pinctrl_gpio7 + &pinctrl_gpmi_gpio>; +}; + +&iomuxc_snvs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio3>; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2emmc>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; + bus-width = <8>; + keep-power-in-suspend; + no-1-8-v; + non-removable; + vmmc-supply = <®_module_3v3>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 0cdbf7b6e728..7f35a06dff95 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -1,6 +1,6 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright 2018 Toradex AG + * Copyright 2018-2021 Toradex */ #include "imx6ull.dtsi" @@ -345,6 +345,19 @@ MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */ >; }; + /* + * With an eMMC instead of a raw NAND device the following pins + * are available at SODIMM pins + */ + pinctrl_gpmi_gpio: gpmi-gpio-grp { + fsl,pins = < + MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x10b0 /* SODIMM 140 */ + MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x10b0 /* SODIMM 144 */ + MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x10b0 /* SODIMM 146 */ + MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x10b0 /* SODIMM 142 */ + >; + }; + pinctrl_gpmi_nand: gpmi-nand-grp { fsl,pins = < MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 @@ -533,6 +546,21 @@ MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x10 >; }; + pinctrl_usdhc2emmc: usdhc2emmcgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + pinctrl_wdog: wdog-grp { fsl,pins = < MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 From 03edccceaed20a66b262b430814ae9fb3d9a931a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 20 Sep 2021 20:22:27 +0200 Subject: [PATCH 10/42] ARM: dts: imx6dl-b1x5v2: drop unsupported vcc-supply for MPL3115A2 The MPL3115A2 I2C pressure sensor driver does not take a VCC regulator. The bindings are so far trivial, but the datasheet does not have a VCC pin. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Sebastian Reichel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-b1x5v2.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi b/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi index a326a331508e..f028b6a191df 100644 --- a/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi +++ b/arch/arm/boot/dts/imx6dl-b1x5v2.dtsi @@ -47,7 +47,6 @@ &i2c5 { mpl3115a2: pressure-sensor@60 { compatible = "fsl,mpl3115"; reg = <0x60>; - vcc-supply = <®_3v3_acm>; /* * The MPL3115 interrupts are connected to pin 22 and 23 From bac185ef0b9d1a5a4137948767ecbce8b3db28b0 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Wed, 22 Sep 2021 15:00:52 +0200 Subject: [PATCH 11/42] ARM: dts: imx7-tqma7/mba7: correct spelling of "TQ-Systems" "TQ-Systems" is written with a dash. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 4 ++-- arch/arm/boot/dts/imx7-tqma7.dtsi | 4 ++-- arch/arm/boot/dts/imx7d-mba7.dts | 6 +++--- arch/arm/boot/dts/imx7d-tqma7.dtsi | 4 ++-- arch/arm/boot/dts/imx7s-mba7.dts | 6 +++--- arch/arm/boot/dts/imx7s-tqma7.dtsi | 4 ++-- 6 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 5e6bef230dc7..0212962b2189 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 OR X11 /* - * Device Tree Include file for TQ Systems MBa7 carrier board. + * Device Tree Include file for TQ-Systems MBa7 carrier board. * - * Copyright (C) 2016 TQ Systems GmbH + * Copyright (C) 2016 TQ-Systems GmbH * Author: Markus Niebel * Copyright (C) 2019 Bruno Thomsen * diff --git a/arch/arm/boot/dts/imx7-tqma7.dtsi b/arch/arm/boot/dts/imx7-tqma7.dtsi index 8773344b54aa..065e1668e280 100644 --- a/arch/arm/boot/dts/imx7-tqma7.dtsi +++ b/arch/arm/boot/dts/imx7-tqma7.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 OR X11 /* - * Device Tree Include file for TQ Systems TQMa7x boards with full mounted PCB. + * Device Tree Include file for TQ-Systems TQMa7x boards with full mounted PCB. * - * Copyright (C) 2016 TQ Systems GmbH + * Copyright (C) 2016 TQ-Systems GmbH * Author: Markus Niebel * Copyright (C) 2019 Bruno Thomsen */ diff --git a/arch/arm/boot/dts/imx7d-mba7.dts b/arch/arm/boot/dts/imx7d-mba7.dts index 36ef6a3cdb0b..32bf9fa9d00e 100644 --- a/arch/arm/boot/dts/imx7d-mba7.dts +++ b/arch/arm/boot/dts/imx7d-mba7.dts @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 OR X11 /* - * Device Tree Source for TQ Systems TQMa7D board on MBa7 carrier board. + * Device Tree Source for TQ-Systems TQMa7D board on MBa7 carrier board. * - * Copyright (C) 2016 TQ Systems GmbH + * Copyright (C) 2016 TQ-Systems GmbH * Author: Markus Niebel * Copyright (C) 2019 Bruno Thomsen */ @@ -13,7 +13,7 @@ #include "imx7-mba7.dtsi" / { - model = "TQ Systems TQMa7D board on MBa7 carrier board"; + model = "TQ-Systems TQMa7D board on MBa7 carrier board"; compatible = "tq,imx7d-mba7", "tq,imx7d-tqma7", "fsl,imx7d"; }; diff --git a/arch/arm/boot/dts/imx7d-tqma7.dtsi b/arch/arm/boot/dts/imx7d-tqma7.dtsi index 598aed1ffd99..3ee2017c1ab3 100644 --- a/arch/arm/boot/dts/imx7d-tqma7.dtsi +++ b/arch/arm/boot/dts/imx7d-tqma7.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 OR X11 /* - * Device Tree Include file for TQ Systems TQMa7D board with NXP i.MX7Dual SoC. + * Device Tree Include file for TQ-Systems TQMa7D board with NXP i.MX7Dual SoC. * - * Copyright (C) 2016 TQ Systems GmbH + * Copyright (C) 2016 TQ-Systems GmbH * Author: Markus Niebel * Copyright (C) 2019 Bruno Thomsen */ diff --git a/arch/arm/boot/dts/imx7s-mba7.dts b/arch/arm/boot/dts/imx7s-mba7.dts index d7d3f530f843..8e4cf589c92c 100644 --- a/arch/arm/boot/dts/imx7s-mba7.dts +++ b/arch/arm/boot/dts/imx7s-mba7.dts @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 OR X11 /* - * Device Tree Source for TQ Systems TQMa7S board on MBa7 carrier board. + * Device Tree Source for TQ-Systems TQMa7S board on MBa7 carrier board. * - * Copyright (C) 2016 TQ Systems GmbH + * Copyright (C) 2016 TQ-Systems GmbH * Author: Markus Niebel * Copyright (C) 2019 Bruno Thomsen */ @@ -13,6 +13,6 @@ #include "imx7-mba7.dtsi" / { - model = "TQ Systems TQMa7S board on MBa7 carrier board"; + model = "TQ-Systems TQMa7S board on MBa7 carrier board"; compatible = "tq,imx7s-mba7", "tq,imx7s-tqma7", "fsl,imx7s"; }; diff --git a/arch/arm/boot/dts/imx7s-tqma7.dtsi b/arch/arm/boot/dts/imx7s-tqma7.dtsi index 5f5433eb7dd7..7a190fdb2d30 100644 --- a/arch/arm/boot/dts/imx7s-tqma7.dtsi +++ b/arch/arm/boot/dts/imx7s-tqma7.dtsi @@ -1,8 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 OR X11 /* - * Device Tree Include file for TQ Systems TQMa7S board with NXP i.MX7Solo SoC. + * Device Tree Include file for TQ-Systems TQMa7S board with NXP i.MX7Solo SoC. * - * Copyright (C) 2016 TQ Systems GmbH + * Copyright (C) 2016 TQ-Systems GmbH * Author: Markus Niebel * Copyright (C) 2019 Bruno Thomsen */ From 61b2f7b15839f5d6b4838a44b6faaff9957e98e7 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Wed, 22 Sep 2021 15:00:53 +0200 Subject: [PATCH 12/42] ARM: dts: imx7-tqma7: add SPI-NOR flash The SPI-NOR flash on the SoM was missing from the device tree. The TQMa7 as a designated QSPI_RESET# pin, however depending on the hardware configuration the pin may be unconnected, or be used for a different purpose. With this in mind, we mux the pin as a pullup and define an input hog for it, but keep it a separate pin group, so that it is easy for dependent Device Trees to modify the configuration. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-tqma7.dtsi | 43 +++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/imx7-tqma7.dtsi b/arch/arm/boot/dts/imx7-tqma7.dtsi index 065e1668e280..fe42b0a46831 100644 --- a/arch/arm/boot/dts/imx7-tqma7.dtsi +++ b/arch/arm/boot/dts/imx7-tqma7.dtsi @@ -19,6 +19,16 @@ &cpu0 { cpu-supply = <&sw1a_reg>; }; +&gpio2 { + /* Configured as pullup by QSPI pin group */ + qspi-reset-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + input; + line-name = "qspi-reset"; + }; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; @@ -160,6 +170,25 @@ MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C >; }; + pinctrl_qspi: qspigrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A + MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A + MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A + MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A + MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11 + MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54 + MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54 + >; + }; + + pinctrl_qspi_reset: qspi_resetgrp { + fsl,pins = < + /* #QSPI_RESET */ + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x59 @@ -217,6 +246,20 @@ MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 }; }; +&qspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi &pinctrl_qspi_reset>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <29000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + &sdma { status = "okay"; }; From 4259da06be5021511bdd6d345e311aa0606cf4d3 Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Wed, 22 Sep 2021 15:00:54 +0200 Subject: [PATCH 13/42] ARM: dts: imx7-mba7: add default SPI-NOR flash partition layout Add the partition layout also used by the bootloader. Signed-off-by: Matthias Schiffer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 38 ++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 0212962b2189..49086c6b6a0a 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -236,6 +236,44 @@ ethphy1_0: ethernet-phy@0 { }; }; +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + uboot@0 { + label = "U-Boot"; + reg = <0x0 0xd0000>; + }; + + env1@d0000 { + label = "ENV1"; + reg = <0xd0000 0x10000>; + }; + + env2@e0000 { + label = "ENV2"; + reg = <0xe0000 0x10000>; + }; + + dtb@f0000 { + label = "DTB"; + reg = <0xf0000 0x10000>; + }; + + linux@100000 { + label = "Linux"; + reg = <0x100000 0x700000>; + }; + + rootfs@800000 { + label = "RootFS"; + reg = <0x800000 0x3800000>; + }; + }; +}; + &flexcan1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; From 3bb3fd8565050350db081bba7b4976fd9bcd4436 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Fri, 24 Sep 2021 10:58:30 +0200 Subject: [PATCH 14/42] ARM: dts: add Netronix E70K02 board common file The Netronix board E70K02 can be found some several Ebook-Readers, at least the Kobo Libra H2O and the Tolino Vision 5. The board is equipped with different SoCs requiring different pinmuxes. For now the following peripherals are included: - LED - Power Key - Cover (gpio via hall sensor) - RC5T619 PMIC - Backlight via lm3630a - Wifi sdio chip detection (mmc-powerseq and stuff) It is based on vendor kernel but heavily reworked due to many changed bindings. Known limitations: cold colored backlight does not work due to incompatible hard coded overvoltage setting in the driver. Signed-off-by: Andreas Kemnade Signed-off-by: Shawn Guo --- arch/arm/boot/dts/e70k02.dtsi | 320 ++++++++++++++++++++++++++++++++++ 1 file changed, 320 insertions(+) create mode 100644 arch/arm/boot/dts/e70k02.dtsi diff --git a/arch/arm/boot/dts/e70k02.dtsi b/arch/arm/boot/dts/e70k02.dtsi new file mode 100644 index 000000000000..156de653f2cd --- /dev/null +++ b/arch/arm/boot/dts/e70k02.dtsi @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2021 Andreas Kemnade + * based on works + * Copyright 2016 Freescale Semiconductor, Inc. + * and + * Copyright (C) 2014 Ricoh Electronic Devices Co., Ltd + * + * Netronix E70K02 board common. + * This board is equipped with different SoCs and + * found in ebook-readers like the Kobo Clara HD (with i.MX6SLL) and + * the Tolino Shine 3 (with i.MX6SL) + */ +#include + +/ { + aliases { + mmc0 = &usdhc1; + mmc1 = &usdhc3; + }; + + chosen { + stdout-path = &uart1; + }; + + gpio_keys: gpio-keys { + compatible = "gpio-keys"; + + power { + label = "Power"; + gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + + cover { + label = "Cover"; + gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + wakeup-source; + }; + + pageup { + label = "PageUp"; + gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + pagedown { + label = "PageDown"; + gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + + led { + label = "e70k02:white:on"; + gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + linux,default-trigger = "timer"; + }; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reg_wifi: regulator-wifi { + compatible = "regulator-fixed"; + regulator-name = "SD3_SPWR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <20>; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + status = "okay"; + + lm3630a: backlight@36 { + reg = <0x36>; + compatible = "ti,lm3630a"; + enable-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + led-sources = <0>; + label = "backlight_warm"; + default-brightness = <0>; + max-brightness = <255>; + }; + + led@1 { + reg = <1>; + led-sources = <1>; + label = "backlight_cold"; + default-brightness = <0>; + max-brightness = <255>; + }; + }; + + /* TODO: KX122 acceleration sensor a 0x1e */ + +}; + +&i2c2 { + clock-frequency = <100000>; + status = "okay"; + + /* TODO: CYTTSP5 touch controller at 0x24 */ + + /* TODO: SY7636 PMIC for E Ink at 0x62 */ + +}; + +&i2c3 { + clock-frequency = <100000>; + status = "okay"; + + ricoh619: pmic@32 { + compatible = "ricoh,rc5t619"; + reg = <0x32>; + interrupt-parent = <&gpio4>; + interrupts = <19 IRQ_TYPE_EDGE_FALLING>; + system-power-controller; + + regulators { + dcdc1_reg: DCDC1 { + regulator-name = "DCDC1"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <900000>; + regulator-suspend-min-microvolt = <900000>; + }; + }; + + /* Core3_3V3 */ + dcdc2_reg: DCDC2 { + regulator-name = "DCDC2"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <3300000>; + regulator-suspend-min-microvolt = <3300000>; + }; + }; + + dcdc3_reg: DCDC3 { + regulator-name = "DCDC3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1875000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1140000>; + regulator-suspend-min-microvolt = <1140000>; + }; + }; + + /* Core4_1V2 */ + dcdc4_reg: DCDC4 { + regulator-name = "DCDC4"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1140000>; + regulator-suspend-min-microvolt = <1140000>; + }; + }; + + /* Core4_1V8 */ + dcdc5_reg: DCDC5 { + regulator-name = "DCDC5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <1700000>; + regulator-suspend-min-microvolt = <1700000>; + }; + }; + + ldo1_reg: LDO1 { + regulator-name = "LDO1"; + regulator-boot-on; + }; + + /* Core1_3V3 */ + ldo2_reg: LDO2 { + regulator-name = "LDO2"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <3000000>; + regulator-suspend-min-microvolt = <3000000>; + }; + }; + + /* Core5_1V2 */ + ldo3_reg: LDO3 { + regulator-name = "LDO3"; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "LDO4"; + regulator-boot-on; + }; + + /* SPD_3V3 */ + ldo5_reg: LDO5 { + regulator-name = "LDO5"; + regulator-always-on; + regulator-boot-on; + }; + + /* DDR_0V6 */ + ldo6_reg: LDO6 { + regulator-name = "LDO6"; + regulator-always-on; + regulator-boot-on; + }; + + /* VDD_PWM */ + ldo7_reg: LDO7 { + regulator-name = "LDO7"; + regulator-boot-on; + }; + + /* ldo_1v8 */ + ldo8_reg: LDO8 { + regulator-name = "LDO8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "LDO9"; + regulator-boot-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "LDO10"; + regulator-boot-on; + }; + + ldortc1_reg: LDORTC1 { + regulator-name = "LDORTC1"; + regulator-boot-on; + }; + }; + }; +}; + +&snvs_rtc { + /* we are using the rtc in the pmic, not disabled in imx6sll.dtsi */ + status = "disabled"; +}; + +&uart1 { + status = "okay"; +}; + +&usdhc1 { + non-removable; + no-1-8-v; + status = "okay"; +}; + +&usdhc3 { + vmmc-supply = <®_wifi>; + mmc-pwrseq = <&wifi_pwrseq>; + cap-power-off-card; + non-removable; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; From 982ba1cbf5d0d79d1d4e0075d6a1fca92a5d029d Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Fri, 24 Sep 2021 10:58:31 +0200 Subject: [PATCH 15/42] ARM: dts: imx: add devicetree for Kobo Libra H2O This adds a devicetree for the Kobo Libra H2O Ebook reader. It is based on boards called e70k02. It is equipped with an imx6sll SoC. Signed-off-by: Andreas Kemnade Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx6sll-kobo-librah2o.dts | 339 ++++++++++++++++++++ 2 files changed, 341 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/imx6sll-kobo-librah2o.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f88ddcc40b6a..596082cd6b0c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -638,7 +638,8 @@ dtb-$(CONFIG_SOC_IMX6SL) += \ imx6sl-warp.dtb dtb-$(CONFIG_SOC_IMX6SLL) += \ imx6sll-evk.dtb \ - imx6sll-kobo-clarahd.dtb + imx6sll-kobo-clarahd.dtb \ + imx6sll-kobo-librah2o.dtb dtb-$(CONFIG_SOC_IMX6SX) += \ imx6sx-nitrogen6sx.dtb \ imx6sx-sabreauto.dtb \ diff --git a/arch/arm/boot/dts/imx6sll-kobo-librah2o.dts b/arch/arm/boot/dts/imx6sll-kobo-librah2o.dts new file mode 100644 index 000000000000..a8b0e88064d9 --- /dev/null +++ b/arch/arm/boot/dts/imx6sll-kobo-librah2o.dts @@ -0,0 +1,339 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * Device tree for the Kobo Libra H2O ebook reader + * + * Name on mainboard is: 37NB-E70K0M+6A3 + * Serials start with: E70K02 (a number also seen in + * vendor kernel sources) + * + * This mainboard seems to be equipped with different SoCs. + * In the Kobo Libra H2O ebook reader it is an i.MX6SLL + * + * Copyright 2021 Andreas Kemnade + * based on works + * Copyright 2016 Freescale Semiconductor, Inc. + */ + +/dts-v1/; + +#include +#include +#include "imx6sll.dtsi" +#include "e70k02.dtsi" + +/ { + model = "Kobo Libra H2O"; + compatible = "kobo,librah2o", "fsl,imx6sll"; +}; + +&clks { + assigned-clocks = <&clks IMX6SLL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <393216000>; +}; + +&cpu0 { + arm-supply = <&dcdc3_reg>; + soc-supply = <&dcdc1_reg>; +}; + +&gpio_keys { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; +}; + +&i2c1 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_sleep>; +}; + +&i2c2 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_sleep>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < + MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x17059 /* PWR_SW */ + MX6SLL_PAD_GPIO4_IO23__GPIO4_IO23 0x17059 /* HALL_EN */ + MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059 /* PAGE_UP */ + MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059 /* PAGE_DOWN */ + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SLL_PAD_LCD_DATA01__GPIO2_IO21 0x79 + MX6SLL_PAD_LCD_DATA04__GPIO2_IO24 0x79 + MX6SLL_PAD_LCD_DATA05__GPIO2_IO25 0x79 + MX6SLL_PAD_LCD_DATA06__GPIO2_IO26 0x79 + MX6SLL_PAD_LCD_DATA07__GPIO2_IO27 0x79 + MX6SLL_PAD_LCD_DATA08__GPIO2_IO28 0x79 + MX6SLL_PAD_LCD_DATA09__GPIO2_IO29 0x79 + MX6SLL_PAD_LCD_DATA10__GPIO2_IO30 0x79 + MX6SLL_PAD_LCD_DATA11__GPIO2_IO31 0x79 + MX6SLL_PAD_LCD_DATA12__GPIO3_IO00 0x79 + MX6SLL_PAD_LCD_DATA13__GPIO3_IO01 0x79 + MX6SLL_PAD_LCD_DATA14__GPIO3_IO02 0x79 + MX6SLL_PAD_LCD_DATA15__GPIO3_IO03 0x79 + MX6SLL_PAD_LCD_DATA16__GPIO3_IO04 0x79 + MX6SLL_PAD_LCD_DATA17__GPIO3_IO05 0x79 + MX6SLL_PAD_LCD_DATA18__GPIO3_IO06 0x79 + MX6SLL_PAD_LCD_DATA19__GPIO3_IO07 0x79 + MX6SLL_PAD_LCD_DATA20__GPIO3_IO08 0x79 + MX6SLL_PAD_LCD_DATA21__GPIO3_IO09 0x79 + MX6SLL_PAD_LCD_DATA22__GPIO3_IO10 0x79 + MX6SLL_PAD_LCD_DATA23__GPIO3_IO11 0x79 + MX6SLL_PAD_LCD_CLK__GPIO2_IO15 0x79 + MX6SLL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 + MX6SLL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 + MX6SLL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 + MX6SLL_PAD_LCD_RESET__GPIO2_IO19 0x79 + MX6SLL_PAD_GPIO4_IO21__GPIO4_IO21 0x79 + MX6SLL_PAD_GPIO4_IO26__GPIO4_IO26 0x79 + MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x79 + MX6SLL_PAD_KEY_ROW7__GPIO4_IO07 0x79 + MX6SLL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 + MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c1_sleep: i2c1grp-sleep { + fsl,pins = < + MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 + MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 + MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c2_sleep: i2c2grp-sleep { + fsl,pins = < + MX6SLL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 + MX6SLL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 + MX6SLL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6SLL_PAD_GPIO4_IO17__GPIO4_IO17 0x10059 + >; + }; + + pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_CTRL3__GPIO2_IO10 0x10059 /* HWEN */ + >; + }; + + pinctrl_ricoh_gpio: ricoh-gpiogrp { + fsl,pins = < + MX6SLL_PAD_GPIO4_IO20__GPIO4_IO20 0x1b8b1 /* ricoh619 chg */ + MX6SLL_PAD_GPIO4_IO19__GPIO4_IO19 0x1b8b1 /* ricoh619 irq */ + MX6SLL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SLL_PAD_UART1_TXD__UART1_DCE_TX 0x1b0b1 + MX6SLL_PAD_UART1_RXD__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x17059 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x17059 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x17059 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x17059 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x17059 + MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x17059 + MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x17059 + MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x17059 + MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170b9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170b9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170b9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170b9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170b9 + MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x170b9 + MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x170b9 + MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x170b9 + MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x170f9 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x170f9 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x170f9 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x170f9 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x170f9 + MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x170b9 + MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x170b9 + MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x170b9 + MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_sleep: usdhc1-sleepgrp { + fsl,pins = < + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x10059 + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6SLL_PAD_SD1_DATA0__SD1_DATA0 0x10059 + MX6SLL_PAD_SD1_DATA1__SD1_DATA1 0x10059 + MX6SLL_PAD_SD1_DATA2__SD1_DATA2 0x10059 + MX6SLL_PAD_SD1_DATA3__SD1_DATA3 0x10059 + MX6SLL_PAD_SD1_DATA4__SD1_DATA4 0x10059 + MX6SLL_PAD_SD1_DATA5__SD1_DATA5 0x10059 + MX6SLL_PAD_SD1_DATA6__SD1_DATA6 0x10059 + MX6SLL_PAD_SD1_DATA7__SD1_DATA7 0x10059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x11059 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x11059 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x11059 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x11059 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x11059 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x11059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170b9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170b9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170b9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SLL_PAD_SD3_CLK__SD3_CLK 0x170f9 + MX6SLL_PAD_SD3_DATA0__SD3_DATA0 0x170f9 + MX6SLL_PAD_SD3_DATA1__SD3_DATA1 0x170f9 + MX6SLL_PAD_SD3_DATA2__SD3_DATA2 0x170f9 + MX6SLL_PAD_SD3_DATA3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc3_sleep: usdhc3-sleepgrp { + fsl,pins = < + MX6SLL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 + MX6SLL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 + MX6SLL_PAD_SD3_DATA0__GPIO5_IO19 0x100c1 + MX6SLL_PAD_SD3_DATA1__GPIO5_IO20 0x100c1 + MX6SLL_PAD_SD3_DATA2__GPIO5_IO16 0x100c1 + MX6SLL_PAD_SD3_DATA3__GPIO5_IO17 0x100c1 + >; + }; + + pinctrl_wifi_power: wifi-powergrp { + fsl,pins = < + MX6SLL_PAD_SD2_DATA6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ + >; + }; + + pinctrl_wifi_reset: wifi-resetgrp { + fsl,pins = < + MX6SLL_PAD_SD2_DATA7__GPIO5_IO00 0x10059 /* WIFI_RST */ + >; + }; +}; + +&leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; +}; + +&lm3630a { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>; +}; + +®_wifi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_power>; +}; + +&ricoh619 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ricoh_gpio>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1_sleep>; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; +}; + +&wifi_pwrseq { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_reset>; +}; From 5cbd3a6396d9eeedda1bba8d45291ae31cbe4b63 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Fri, 24 Sep 2021 10:58:32 +0200 Subject: [PATCH 16/42] ARM: dts: imx: add devicetree for Tolino Vision 5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds a devicetree for the Tolino Vision 5 Ebook reader. It is based on boards called ¨e70k02¨. It is equipped with an imx6sl SoC. Signed-off-by: Andreas Kemnade Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6sl-tolino-vision5.dts | 349 ++++++++++++++++++++ 2 files changed, 350 insertions(+) create mode 100644 arch/arm/boot/dts/imx6sl-tolino-vision5.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 596082cd6b0c..936aa3e65ce7 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -635,6 +635,7 @@ dtb-$(CONFIG_SOC_IMX6SL) += \ imx6sl-evk.dtb \ imx6sl-tolino-shine2hd.dtb \ imx6sl-tolino-shine3.dtb \ + imx6sl-tolino-vision5.dtb \ imx6sl-warp.dtb dtb-$(CONFIG_SOC_IMX6SLL) += \ imx6sll-evk.dtb \ diff --git a/arch/arm/boot/dts/imx6sl-tolino-vision5.dts b/arch/arm/boot/dts/imx6sl-tolino-vision5.dts new file mode 100644 index 000000000000..ff6118df3946 --- /dev/null +++ b/arch/arm/boot/dts/imx6sl-tolino-vision5.dts @@ -0,0 +1,349 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * Device tree for the Tolino Vision 5 ebook reader + * + * Name on mainboard is: 37NB-E70K0M+6A3 + * Serials start with: E70K02 (a number also seen in + * vendor kernel sources) + * + * This mainboard seems to be equipped with different SoCs. + * In the Tolino Vision 5 ebook reader it is a i.MX6SL + * + * Copyright 2021 Andreas Kemnade + * based on works + * Copyright 2016 Freescale Semiconductor, Inc. + */ + +/dts-v1/; + +#include +#include +#include "imx6sl.dtsi" +#include "e70k02.dtsi" + +/ { + model = "Tolino Vision 5"; + compatible = "kobo,tolino-vision5", "fsl,imx6sl"; +}; + +&gpio_keys { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; +}; + +&i2c1 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_sleep>; +}; + +&i2c2 { + pinctrl-names = "default","sleep"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_sleep>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_gpio_keys: gpio-keysgrp { + fsl,pins = < + MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x17059 /* PWR_SW */ + MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x17059 /* HALL_EN */ + MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x17059 /* PAGE_UP */ + MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x17059 /* PAGE_DOWN */ + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6SL_PAD_LCD_DAT1__GPIO2_IO21 0x79 + MX6SL_PAD_LCD_DAT4__GPIO2_IO24 0x79 + MX6SL_PAD_LCD_DAT5__GPIO2_IO25 0x79 + MX6SL_PAD_LCD_DAT6__GPIO2_IO26 0x79 + MX6SL_PAD_LCD_DAT7__GPIO2_IO27 0x79 + MX6SL_PAD_LCD_DAT8__GPIO2_IO28 0x79 + MX6SL_PAD_LCD_DAT9__GPIO2_IO29 0x79 + MX6SL_PAD_LCD_DAT10__GPIO2_IO30 0x79 + MX6SL_PAD_LCD_DAT11__GPIO2_IO31 0x79 + MX6SL_PAD_LCD_DAT12__GPIO3_IO00 0x79 + MX6SL_PAD_LCD_DAT13__GPIO3_IO01 0x79 + MX6SL_PAD_LCD_DAT14__GPIO3_IO02 0x79 + MX6SL_PAD_LCD_DAT15__GPIO3_IO03 0x79 + MX6SL_PAD_LCD_DAT16__GPIO3_IO04 0x79 + MX6SL_PAD_LCD_DAT17__GPIO3_IO05 0x79 + MX6SL_PAD_LCD_DAT18__GPIO3_IO06 0x79 + MX6SL_PAD_LCD_DAT19__GPIO3_IO07 0x79 + MX6SL_PAD_LCD_DAT20__GPIO3_IO08 0x79 + MX6SL_PAD_LCD_DAT21__GPIO3_IO09 0x79 + MX6SL_PAD_LCD_DAT22__GPIO3_IO10 0x79 + MX6SL_PAD_LCD_DAT23__GPIO3_IO11 0x79 + MX6SL_PAD_LCD_CLK__GPIO2_IO15 0x79 + MX6SL_PAD_LCD_ENABLE__GPIO2_IO16 0x79 + MX6SL_PAD_LCD_HSYNC__GPIO2_IO17 0x79 + MX6SL_PAD_LCD_VSYNC__GPIO2_IO18 0x79 + MX6SL_PAD_LCD_RESET__GPIO2_IO19 0x79 + MX6SL_PAD_FEC_TX_CLK__GPIO4_IO21 0x79 + MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x79 + MX6SL_PAD_KEY_COL3__GPIO3_IO30 0x79 + MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x79 + MX6SL_PAD_ECSPI2_MOSI__GPIO4_IO13 0x79 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001f8b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c1_sleep: i2c1grp-sleep { + fsl,pins = < + MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x400108b1 + MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x400108b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001f8b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001f8b1 + >; + }; + + pinctrl_i2c2_sleep: i2c2grp-sleep { + fsl,pins = < + MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x400108b1 + MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x400108b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6SL_PAD_REF_CLK_24M__I2C3_SCL 0x4001f8b1 + MX6SL_PAD_REF_CLK_32K__I2C3_SDA 0x4001f8b1 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x10059 + >; + }; + + pinctrl_lm3630a_bl_gpio: lm3630a-bl-gpiogrp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCTRL3__GPIO2_IO10 0x10059 /* HWEN */ + >; + }; + + pinctrl_ricoh_gpio: ricoh-gpiogrp { + fsl,pins = < + MX6SL_PAD_FEC_MDIO__GPIO4_IO20 0x1b8b1 /* ricoh619 chg */ + MX6SL_PAD_FEC_RX_ER__GPIO4_IO19 0x1b8b1 /* ricoh619 irq */ + MX6SL_PAD_KEY_COL2__GPIO3_IO28 0x1b8b1 /* ricoh619 bat_low_int */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1 + MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x17059 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x170b9 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x170f9 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc1_sleep: usdhc1-sleepgrp { + fsl,pins = < + MX6SL_PAD_SD1_CMD__SD1_CMD 0x10059 + MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x10059 + MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x10059 + MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x10059 + MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x10059 + MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x10059 + MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x10059 + MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x10059 + MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x10059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x11059 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x11059 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x11059 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x11059 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x11059 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x11059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x170b9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6SL_PAD_SD3_CLK__SD3_CLK 0x170f9 + MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc3_sleep: usdhc3-sleepgrp { + fsl,pins = < + MX6SL_PAD_SD3_CMD__GPIO5_IO21 0x100c1 + MX6SL_PAD_SD3_CLK__GPIO5_IO18 0x100c1 + MX6SL_PAD_SD3_DAT0__GPIO5_IO19 0x100c1 + MX6SL_PAD_SD3_DAT1__GPIO5_IO20 0x100c1 + MX6SL_PAD_SD3_DAT2__GPIO5_IO16 0x100c1 + MX6SL_PAD_SD3_DAT3__GPIO5_IO17 0x100c1 + >; + }; + + pinctrl_wifi_power: wifi-powergrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x10059 /* WIFI_3V3_ON */ + >; + }; + + pinctrl_wifi_reset: wifi-resetgrp { + fsl,pins = < + MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x10059 /* WIFI_RST */ + >; + }; +}; + +&leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; +}; + +&lm3630a { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lm3630a_bl_gpio>; +}; + +®_wifi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_power>; +}; + +®_vdd1p1 { + vin-supply = <&dcdc2_reg>; +}; + +®_vdd2p5 { + vin-supply = <&dcdc2_reg>; +}; + +®_arm { + vin-supply = <&dcdc3_reg>; +}; + +®_soc { + vin-supply = <&dcdc1_reg>; +}; + +®_pu { + vin-supply = <&dcdc1_reg>; +}; + +&ricoh619 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ricoh_gpio>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-3 = <&pinctrl_usdhc1_sleep>; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz","sleep"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + pinctrl-3 = <&pinctrl_usdhc3_sleep>; +}; + +&wifi_pwrseq { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_reset>; +}; From 31ffe01e8200f05041da519a7b371d02020a0ba3 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Fri, 24 Sep 2021 11:14:35 +0200 Subject: [PATCH 17/42] ARM: dts: imx: e60k02: correct led node name Only led-X or led are allowed according to bindings definition. Signed-off-by: Andreas Kemnade Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/e60k02.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/e60k02.dtsi b/arch/arm/boot/dts/e60k02.dtsi index cfb239d5186a..1a49f15f2df2 100644 --- a/arch/arm/boot/dts/e60k02.dtsi +++ b/arch/arm/boot/dts/e60k02.dtsi @@ -41,7 +41,7 @@ cover { leds: leds { compatible = "gpio-leds"; - on { + led { label = "e60k02:white:on"; gpios = <&gpio5 7 GPIO_ACTIVE_LOW>; linux,default-trigger = "timer"; From bea74c43602a96f4cce05990a27f6f9fdb0405b2 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Fri, 24 Sep 2021 11:14:36 +0200 Subject: [PATCH 18/42] ARM: dts: imx6sl: fixup of operating points Make operating point definitions comply with binding specifications. Signed-off-by: Andreas Kemnade Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 997b96c1c47b..c7d907c5c352 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -55,18 +55,16 @@ cpu@0 { device_type = "cpu"; reg = <0x0>; next-level-cache = <&L2>; - operating-points = < + operating-points = /* kHz uV */ - 996000 1275000 - 792000 1175000 - 396000 975000 - >; - fsl,soc-operating-points = < + <996000 1275000>, + <792000 1175000>, + <396000 975000>; + fsl,soc-operating-points = /* ARM kHz SOC-PU uV */ - 996000 1225000 - 792000 1175000 - 396000 1175000 - >; + <996000 1225000>, + <792000 1175000>, + <396000 1175000>; clock-latency = <61036>; /* two CLK32 periods */ #cooling-cells = <2>; clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, From 1875903019ea6e32e6e544c1631b119e4fd60b20 Mon Sep 17 00:00:00 2001 From: Andreas Kemnade Date: Fri, 24 Sep 2021 11:14:37 +0200 Subject: [PATCH 19/42] ARM: dts: imx6sll: fixup of operating points Make operating point definitions comply with binding specifications. Signed-off-by: Andreas Kemnade Reviewed-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll.dtsi | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index 04f8d637a501..d4a000c3dde7 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -51,20 +51,18 @@ cpu0: cpu@0 { device_type = "cpu"; reg = <0>; next-level-cache = <&L2>; - operating-points = < + operating-points = /* kHz uV */ - 996000 1275000 - 792000 1175000 - 396000 1075000 - 198000 975000 - >; - fsl,soc-operating-points = < + <996000 1275000>, + <792000 1175000>, + <396000 1075000>, + <198000 975000>; + fsl,soc-operating-points = /* ARM kHz SOC-PU uV */ - 996000 1175000 - 792000 1175000 - 396000 1175000 - 198000 1175000 - >; + <996000 1175000>, + <792000 1175000>, + <396000 1175000>, + <198000 1175000>; clock-latency = <61036>; /* two CLK32 periods */ #cooling-cells = <2>; clocks = <&clks IMX6SLL_CLK_ARM>, From 56086b5e804fcc98d1c699f7df6d42db12ed2977 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 24 Sep 2021 10:46:42 -0300 Subject: [PATCH 20/42] ARM: dts: imx6qdl-apalis: Avoid underscore in node name It is recommended not to use underscore in node names. Change it to dash. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 30fa349f9d05..7c6d9c75d2bf 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -313,7 +313,7 @@ stmpe811@41 { /* ADC converstion time: 80 clocks */ st,sample-time = <4>; - stmpe_touchscreen { + stmpe-touchscreen { compatible = "st,stmpe-ts"; /* 8 sample average control */ st,ave-ctrl = <3>; @@ -330,7 +330,7 @@ stmpe_touchscreen { st,touch-det-delay = <5>; }; - stmpe_adc { + stmpe-adc { compatible = "st,stmpe-adc"; /* forbid to use ADC channels 3-0 (touch) */ st,norequest-mask = <0x0F>; From cdbaba8d72dd68bab1185fe121f64bbf2d71eac2 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 24 Sep 2021 10:46:43 -0300 Subject: [PATCH 21/42] ARM: dts: imx6qdl-apalis: Pass 'io-channel-cells' to the ADC The STMPE811 ADC on the Apalis SoM board can be used as a provider of ADC capabilities to other devices, for example, when a custom baseboard has an SN74LV4051 analog mux. Pass the 'io-channel-cells' parameter to indicate such possibility. While at it, also pass a label for the adc device, so that it can be referenced in the custom baseboard. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 7c6d9c75d2bf..4092af5f6999 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -330,10 +330,11 @@ stmpe-touchscreen { st,touch-det-delay = <5>; }; - stmpe-adc { + stmpe_adc: stmpe-adc { compatible = "st,stmpe-adc"; /* forbid to use ADC channels 3-0 (touch) */ st,norequest-mask = <0x0F>; + #io-channel-cells = <1>; }; }; }; From 9904cd59fd823f55a951f93a4c9765bb408a6633 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 24 Sep 2021 10:46:44 -0300 Subject: [PATCH 22/42] ARM: dts: imx6qdl-apalis: Add a label for the touchscreen Add a label for the touchscreen to allow a custom baseboard to disable this node if needed. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 4092af5f6999..aae60ffac623 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -313,7 +313,7 @@ stmpe811@41 { /* ADC converstion time: 80 clocks */ st,sample-time = <4>; - stmpe-touchscreen { + stmpe_touchscreen: stmpe-touchscreen { compatible = "st,stmpe-ts"; /* 8 sample average control */ st,ave-ctrl = <3>; From ab3d84915f26e4740db4e2ac6ea93f73a9811c5d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 24 Sep 2021 10:46:45 -0300 Subject: [PATCH 23/42] ARM: dts: imx6qdl-apalis: Fix typo in ADC comment Fix the spelling of 'conversion'. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-apalis.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index aae60ffac623..ed2739e39085 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -310,7 +310,7 @@ stmpe811@41 { st,mod-12b = <1>; /* internal ADC reference */ st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ + /* ADC conversion time: 80 clocks */ st,sample-time = <4>; stmpe_touchscreen: stmpe-touchscreen { From 0fa8bc5df43f31522cd233dcb12230fd3c09bb64 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Thu, 30 Sep 2021 14:52:21 +0200 Subject: [PATCH 24/42] ARM: dts: imx6: skov: provide panel support for lt2 variants Add support for the Logic Technologies LTTD800x480 L2RT 7" 800x480 TFT Resistive Touch Module. Signed-off-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-skov-revc-lt2.dts | 1 + arch/arm/boot/dts/imx6q-skov-revc-lt2.dts | 1 + arch/arm/boot/dts/imx6qdl-skov-revc-lt2.dtsi | 99 ++++++++++++++++++++ 3 files changed, 101 insertions(+) create mode 100644 arch/arm/boot/dts/imx6qdl-skov-revc-lt2.dtsi diff --git a/arch/arm/boot/dts/imx6dl-skov-revc-lt2.dts b/arch/arm/boot/dts/imx6dl-skov-revc-lt2.dts index 667b8faa1807..b12b5aabe70a 100644 --- a/arch/arm/boot/dts/imx6dl-skov-revc-lt2.dts +++ b/arch/arm/boot/dts/imx6dl-skov-revc-lt2.dts @@ -6,6 +6,7 @@ #include "imx6dl.dtsi" #include "imx6qdl-skov-cpu.dtsi" #include "imx6qdl-skov-cpu-revc.dtsi" +#include "imx6qdl-skov-revc-lt2.dtsi" / { model = "SKOV IMX6 CPU SoloCore"; diff --git a/arch/arm/boot/dts/imx6q-skov-revc-lt2.dts b/arch/arm/boot/dts/imx6q-skov-revc-lt2.dts index f00add7b3048..ff97d22eb09f 100644 --- a/arch/arm/boot/dts/imx6q-skov-revc-lt2.dts +++ b/arch/arm/boot/dts/imx6q-skov-revc-lt2.dts @@ -6,6 +6,7 @@ #include "imx6q.dtsi" #include "imx6qdl-skov-cpu.dtsi" #include "imx6qdl-skov-cpu-revc.dtsi" +#include "imx6qdl-skov-revc-lt2.dtsi" / { model = "SKOV IMX6 CPU QuadCore"; diff --git a/arch/arm/boot/dts/imx6qdl-skov-revc-lt2.dtsi b/arch/arm/boot/dts/imx6qdl-skov-revc-lt2.dtsi new file mode 100644 index 000000000000..48c9ce051f47 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-skov-revc-lt2.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Copyright (C) 2021 Pengutronix, Oleksij Rempel + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + enable-gpios = <&gpio6 23 GPIO_ACTIVE_LOW>; + pwms = <&pwm2 0 20000 0>; + brightness-levels = <0 255>; + num-interpolated-steps = <17>; + default-brightness-level = <8>; + power-supply = <®_24v0>; + }; + + display { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "fsl,imx-parallel-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1>; + + port@0 { + reg = <0>; + + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + + display0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + + panel { + compatible = "logictechno,lttd800480070-l2rt"; + backlight = <&backlight>; + power-supply = <®_3v3>; + + port { + panel_in: endpoint { + remote-endpoint = <&display0_out>; + }; + }; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&iomuxc { + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x58 + >; + }; + + pinctrl_ipu1: ipu1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 + >; + }; +}; From 4fb0b9309c9f3f7959fc5f796893da908e1f30d0 Mon Sep 17 00:00:00 2001 From: Yunus Bas Date: Mon, 4 Oct 2021 08:48:22 +0200 Subject: [PATCH 25/42] ARM: dts: imx6: phytec: Add gpio pinctrl for i2c bus recovery Make use of the i2c bus recovery feature and enable it on PHYTEC phyCORE-based modules and boards. Signed-off-by: Yunus Bas Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi | 30 +++++++++++++++---- .../boot/dts/imx6qdl-phytec-phycore-som.dtsi | 12 +++++++- .../boot/dts/imx6ul-phytec-phycore-som.dtsi | 12 +++++++- 3 files changed, 47 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi index 0873f53ea275..120d6e997a4c 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi @@ -145,8 +145,11 @@ &hdmi { }; &i2c1 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <400000>; status = "disabled"; @@ -185,8 +188,11 @@ i2c_rtc: rtc@68 { }; &i2c2 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <100000>; status = "disabled"; }; @@ -300,6 +306,20 @@ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 >; }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 @@ -307,10 +327,10 @@ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 >; }; - pinctrl_i2c1: i2c1grp { + pinctrl_i2c2_gpio: i2c2gpiogrp { fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi index a80aa08a37cb..94b254bfd054 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi @@ -78,8 +78,11 @@ &gpmi { }; &i2c3 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <400000>; status = "okay"; @@ -259,6 +262,13 @@ MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 >; }; + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1 + >; + }; + pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi index 19a062635ff6..3cddc68917a0 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi @@ -68,8 +68,11 @@ &gpmi { }; &i2c1 { - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; clock-frequency = <100000>; status = "okay"; @@ -147,6 +150,13 @@ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 >; }; + pinctrl_i2c1_gpio: i2cgpiogrp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 From c49d461648e5943215098a085690a9852b24a5ae Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 10 Oct 2021 15:32:15 +0200 Subject: [PATCH 26/42] ARM: dts: imx6dl-prtrvt: drop undocumented TRF7970A NFC properties Neither the bindings nor the device driver use/document "vin-voltage-override" and "t5t-rmb-extra-byte-quirk" properties. Cc: Oleksij Rempel Signed-off-by: Krzysztof Kozlowski Reviewed-by: Oleksij Rempel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-prtrvt.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-prtrvt.dts b/arch/arm/boot/dts/imx6dl-prtrvt.dts index 5ac84445e9cc..56bb1ca56a2d 100644 --- a/arch/arm/boot/dts/imx6dl-prtrvt.dts +++ b/arch/arm/boot/dts/imx6dl-prtrvt.dts @@ -67,11 +67,9 @@ nfc@0 { ti,enable-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>, <&gpio5 11 GPIO_ACTIVE_LOW>; vin-supply = <®_3v3>; - vin-voltage-override = <3100000>; autosuspend-delay = <30000>; irq-status-read-quirk; en2-rf-quirk; - t5t-rmb-extra-byte-quirk; status = "okay"; }; }; From 113dc42b03e352e4d8b3ff9425e26aa52ae61832 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Tue, 12 Oct 2021 18:58:08 -0500 Subject: [PATCH 27/42] ARM: dts: ls1021a: remove clock-names property for i2c nodes The property is optional and not used in matching the clock in driver. Remove it to avoid dtbs_check issues. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 4fce81422943..77f983b589fa 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -394,7 +394,6 @@ i2c0: i2c@2180000 { #size-cells = <0>; reg = <0x0 0x2180000 0x0 0x10000>; interrupts = ; - clock-names = "i2c"; clocks = <&clockgen 4 1>; dma-names = "tx", "rx"; dmas = <&edma0 1 39>, <&edma0 1 38>; @@ -407,7 +406,6 @@ i2c1: i2c@2190000 { #size-cells = <0>; reg = <0x0 0x2190000 0x0 0x10000>; interrupts = ; - clock-names = "i2c"; clocks = <&clockgen 4 1>; dma-names = "tx", "rx"; dmas = <&edma0 1 37>, <&edma0 1 36>; @@ -420,7 +418,6 @@ i2c2: i2c@21a0000 { #size-cells = <0>; reg = <0x0 0x21a0000 0x0 0x10000>; interrupts = ; - clock-names = "i2c"; clocks = <&clockgen 4 1>; dma-names = "tx", "rx"; dmas = <&edma0 1 35>, <&edma0 1 34>; From ca8a261617c7ff478335de071cd26cb8a82f845a Mon Sep 17 00:00:00 2001 From: Li Yang Date: Tue, 12 Oct 2021 18:58:09 -0500 Subject: [PATCH 28/42] ARM: dts: ls1021a: change dma channels order to match schema Although the ordering of DMA channels was not relevant in the txt binding, it is defined as ordered in the converted yaml schema. Update the dts to match the order. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 77f983b589fa..960de957f0b4 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -395,8 +395,8 @@ i2c0: i2c@2180000 { reg = <0x0 0x2180000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>; - dma-names = "tx", "rx"; - dmas = <&edma0 1 39>, <&edma0 1 38>; + dma-names = "rx", "tx"; + dmas = <&edma0 1 38>, <&edma0 1 39>; status = "disabled"; }; @@ -407,8 +407,8 @@ i2c1: i2c@2190000 { reg = <0x0 0x2190000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>; - dma-names = "tx", "rx"; - dmas = <&edma0 1 37>, <&edma0 1 36>; + dma-names = "rx", "tx"; + dmas = <&edma0 1 36>, <&edma0 1 37>; status = "disabled"; }; @@ -419,8 +419,8 @@ i2c2: i2c@21a0000 { reg = <0x0 0x21a0000 0x0 0x10000>; interrupts = ; clocks = <&clockgen 4 1>; - dma-names = "tx", "rx"; - dmas = <&edma0 1 35>, <&edma0 1 34>; + dma-names = "rx", "tx"; + dmas = <&edma0 1 34>, <&edma0 1 35>; status = "disabled"; }; From 784bdc6f2697cf64d8841bc5fe02456016d6c399 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Tue, 12 Oct 2021 18:58:10 -0500 Subject: [PATCH 29/42] ARM: dts: ls1021a: change to use SPDX identifiers Replace the license text with SPDX identifiers. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a-qds.dts | 44 +------------------------------ arch/arm/boot/dts/ls1021a-twr.dts | 44 +------------------------------ arch/arm/boot/dts/ls1021a.dtsi | 44 +------------------------------ 3 files changed, 3 insertions(+), 129 deletions(-) diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts index 74a67604876c..e2aa569ff404 100644 --- a/arch/arm/boot/dts/ls1021a-qds.dts +++ b/arch/arm/boot/dts/ls1021a-qds.dts @@ -1,49 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright 2013-2014 Freescale Semiconductor, Inc. * Copyright 2018 NXP - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts index 5edf001f6138..e162a1599264 100644 --- a/arch/arm/boot/dts/ls1021a-twr.dts +++ b/arch/arm/boot/dts/ls1021a-twr.dts @@ -1,49 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright 2013-2014 Freescale Semiconductor, Inc. * Copyright 2018 NXP - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 960de957f0b4..2f9ea0beac7a 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -1,48 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright 2013-2014 Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public - * License along with this file; if not, write to the Free - * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include From 7cd2f9a59f34c4bdfd2a4b85f6a7d16deb29c8ee Mon Sep 17 00:00:00 2001 From: Li Yang Date: Tue, 12 Oct 2021 18:58:11 -0500 Subject: [PATCH 30/42] ARM: dts: ls1021a-qds: Add node for QSPI flash Add the missing node for qspi flash. Signed-off-by: Li Yang Reviewed-by: Kuldeep Singh Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a-qds.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts index e2aa569ff404..8982ba2c14c2 100644 --- a/arch/arm/boot/dts/ls1021a-qds.dts +++ b/arch/arm/boot/dts/ls1021a-qds.dts @@ -286,6 +286,20 @@ tbi0: tbi-phy@8 { }; }; +&qspi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + reg = <0>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + &sai2 { status = "okay"; }; From 74c7b4593798def8293aeb2b4562c116f410ab60 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Tue, 12 Oct 2021 18:58:12 -0500 Subject: [PATCH 31/42] ARM: dts: ls1021a: update pcie nodes for dt-schema check Break up long values to pass dt-schema checks. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 2f9ea0beac7a..fa4adfdf4abd 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -839,8 +839,8 @@ usb3: usb@3100000 { pcie@3400000 { compatible = "fsl,ls1021a-pcie"; - reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03400000 0x0 0x00010000>, /* controller registers */ + <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = ; /* controller interrupt */ fsl,pcie-scfg = <&scfg 0>; @@ -849,8 +849,8 @@ pcie@3400000 { device_type = "pci"; num-viewport = <6>; bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000>, /* downstream I/O */ + <0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ msi-parent = <&msi1>, <&msi2>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; @@ -863,8 +863,8 @@ pcie@3400000 { pcie@3500000 { compatible = "fsl,ls1021a-pcie"; - reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */ - 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ + reg = <0x00 0x03500000 0x0 0x00010000>, /* controller registers */ + <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; interrupts = ; fsl,pcie-scfg = <&scfg 1>; @@ -873,8 +873,8 @@ pcie@3500000 { device_type = "pci"; num-viewport = <6>; bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000>, /* downstream I/O */ + <0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ msi-parent = <&msi1>, <&msi2>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; From 44c4072033137437537905cf55743df29a364d16 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Tue, 12 Oct 2021 18:58:13 -0500 Subject: [PATCH 32/42] ARM: dts: ls1021a: fix board compatible to follow binding schema Align the compatible strings with the board binding defined in schema file. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a-tsn.dts | 1 + arch/arm/boot/dts/ls1021a.dtsi | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts b/arch/arm/boot/dts/ls1021a-tsn.dts index 9d8f0c2a8aba..ce470ebfb2c0 100644 --- a/arch/arm/boot/dts/ls1021a-tsn.dts +++ b/arch/arm/boot/dts/ls1021a-tsn.dts @@ -8,6 +8,7 @@ / { model = "NXP LS1021A-TSN Board"; + compatible = "fsl,ls1021a-tsn", "fsl,ls1021a"; sys_mclk: clock-mclk { compatible = "fixed-clock"; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index fa4adfdf4abd..3f1cd7e55091 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -9,7 +9,6 @@ / { #address-cells = <2>; #size-cells = <2>; - compatible = "fsl,ls1021a"; interrupt-parent = <&gic>; aliases { From d41488bc0b65cc5ead5c4f9b45683531c2cc65a3 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Tue, 12 Oct 2021 18:58:14 -0500 Subject: [PATCH 33/42] ARM: dts: ls1021a: breakup long values in thermal node Breakup long values to pass the schema check. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 66 +++++++++++++++++----------------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 3f1cd7e55091..4a7d06a14946 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -247,42 +247,42 @@ tmu: tmu@1f00000 { reg = <0x0 0x1f00000 0x0 0x10000>; interrupts = ; fsl,tmu-range = <0xb0000 0x9002c 0x6004e 0x30066>; - fsl,tmu-calibration = <0x00000000 0x00000020 - 0x00000001 0x00000024 - 0x00000002 0x0000002a - 0x00000003 0x00000032 - 0x00000004 0x00000038 - 0x00000005 0x0000003e - 0x00000006 0x00000043 - 0x00000007 0x0000004a - 0x00000008 0x00000050 - 0x00000009 0x00000059 - 0x0000000a 0x0000005f - 0x0000000b 0x00000066 + fsl,tmu-calibration = <0x00000000 0x00000020>, + <0x00000001 0x00000024>, + <0x00000002 0x0000002a>, + <0x00000003 0x00000032>, + <0x00000004 0x00000038>, + <0x00000005 0x0000003e>, + <0x00000006 0x00000043>, + <0x00000007 0x0000004a>, + <0x00000008 0x00000050>, + <0x00000009 0x00000059>, + <0x0000000a 0x0000005f>, + <0x0000000b 0x00000066>, - 0x00010000 0x00000023 - 0x00010001 0x0000002b - 0x00010002 0x00000033 - 0x00010003 0x0000003a - 0x00010004 0x00000042 - 0x00010005 0x0000004a - 0x00010006 0x00000054 - 0x00010007 0x0000005c - 0x00010008 0x00000065 - 0x00010009 0x0000006f + <0x00010000 0x00000023>, + <0x00010001 0x0000002b>, + <0x00010002 0x00000033>, + <0x00010003 0x0000003a>, + <0x00010004 0x00000042>, + <0x00010005 0x0000004a>, + <0x00010006 0x00000054>, + <0x00010007 0x0000005c>, + <0x00010008 0x00000065>, + <0x00010009 0x0000006f>, - 0x00020000 0x00000029 - 0x00020001 0x00000033 - 0x00020002 0x0000003d - 0x00020003 0x00000048 - 0x00020004 0x00000054 - 0x00020005 0x00000060 - 0x00020006 0x0000006c + <0x00020000 0x00000029>, + <0x00020001 0x00000033>, + <0x00020002 0x0000003d>, + <0x00020003 0x00000048>, + <0x00020004 0x00000054>, + <0x00020005 0x00000060>, + <0x00020006 0x0000006c>, - 0x00030000 0x00000025 - 0x00030001 0x00000033 - 0x00030002 0x00000043 - 0x00030003 0x00000055>; + <0x00030000 0x00000025>, + <0x00030001 0x00000033>, + <0x00030002 0x00000043>, + <0x00030003 0x00000055>; #thermal-sensor-cells = <1>; }; From 61761d3eeb4367c98d4f479033cc19064cd529e4 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Tue, 12 Oct 2021 18:58:15 -0500 Subject: [PATCH 34/42] ARM: dts: ls1021a: disable ifc node by default Disable the bus in the SoC dtsi file to be enabled only in board dts files. Also breakup long values in the ifc node to fix dtbs_check. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a-qds.dts | 6 +++--- arch/arm/boot/dts/ls1021a.dtsi | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts index 8982ba2c14c2..6db6604e7a18 100644 --- a/arch/arm/boot/dts/ls1021a-qds.dts +++ b/arch/arm/boot/dts/ls1021a-qds.dts @@ -189,9 +189,9 @@ &ifc { #address-cells = <2>; #size-cells = <1>; /* NOR, NAND Flashes and FPGA on board */ - ranges = <0x0 0x0 0x0 0x60000000 0x08000000 - 0x2 0x0 0x0 0x7e800000 0x00010000 - 0x3 0x0 0x0 0x7fb00000 0x00000100>; + ranges = <0x0 0x0 0x0 0x60000000 0x08000000>, + <0x2 0x0 0x0 0x7e800000 0x00010000>, + <0x3 0x0 0x0 0x7fb00000 0x00000100>; status = "okay"; nor@0,0 { diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 4a7d06a14946..e6677721263b 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -126,6 +126,7 @@ ifc: ifc@1530000 { compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x1530000 0x0 0x10000>; interrupts = ; + status = "disabled"; }; dcfg: dcfg@1ee0000 { From 8611083250e801c8bdf8b9d7abe2e96767e9bd62 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Tue, 12 Oct 2021 18:58:16 -0500 Subject: [PATCH 35/42] ARM: dts: ls1021a: remove regulators simple-bus There is no regulator bus in hardware. So move the regulator nodes out and remove the regulators simple-bus. This also make the dts align with the simple-bus schema. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a-qds.dts | 19 ++++++------------- arch/arm/boot/dts/ls1021a-twr.dts | 19 ++++++------------- 2 files changed, 12 insertions(+), 26 deletions(-) diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts index 6db6604e7a18..6e469b46229f 100644 --- a/arch/arm/boot/dts/ls1021a-qds.dts +++ b/arch/arm/boot/dts/ls1021a-qds.dts @@ -25,19 +25,12 @@ sys_mclk: clock-mclk { clock-frequency = <24576000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3p3v: regulator { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; }; sound { diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts index e162a1599264..f5c03871b205 100644 --- a/arch/arm/boot/dts/ls1021a-twr.dts +++ b/arch/arm/boot/dts/ls1021a-twr.dts @@ -23,19 +23,12 @@ sys_mclk: clock-mclk { clock-frequency = <24576000>; }; - regulators { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - reg = <0>; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; + reg_3p3v: regulator { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; }; sound { From e11f309660e1d9be9e74d9eb571a234b8c59f756 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Tue, 12 Oct 2021 18:58:17 -0500 Subject: [PATCH 36/42] ARM: dts: ls1021a: fix memory node for schema check Fix the following error from "make dtbs_check" memory: False schema does not allow ... Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index e6677721263b..76c181602399 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -47,7 +47,7 @@ cpu1: cpu@f01 { }; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0 0x0>; }; From 39a1d8d2fbda4d3f49920358571b91eb5aa5ac76 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Tue, 12 Oct 2021 18:58:18 -0500 Subject: [PATCH 37/42] ARM: dts: ls1021a: add #dma-cells to qdma node Add the #dma-cells to align with the dma schema. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 76c181602399..bf583a0cc237 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -947,6 +947,7 @@ qdma: dma-controller@8390000 { ; interrupt-names = "qdma-error", "qdma-queue0", "qdma-queue1"; + #dma-cells = <2>; dma-channels = <8>; block-number = <1>; block-offset = <0x1000>; From 8bcf67b8d893b37646161080f8a67b5105f77687 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Tue, 12 Oct 2021 18:58:19 -0500 Subject: [PATCH 38/42] ARM: dts: ls1021a: add #power-domain-cells for power-controller node Add the #power-domain-cells for power-controller node as required by the schema. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index bf583a0cc237..cc7445e47641 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -961,6 +961,7 @@ rcpm: power-controller@1ee2140 { compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+"; reg = <0x0 0x1ee2140 0x0 0x8>; #fsl,rcpm-wakeup-cells = <2>; + #power-domain-cells = <0>; }; ftm_alarm0: timer0@29d0000 { From 6aae6c49690c9f425ee23dfb9d3d80b310f90d4b Mon Sep 17 00:00:00 2001 From: Li Yang Date: Tue, 12 Oct 2021 18:58:20 -0500 Subject: [PATCH 39/42] ARM: dts: ls1021a-qds: change fpga to simple-mfd device The FPGA is not really a bus but more like an MFD device. Change the compatible string from "simple-bus" to "simple-mfd". This also fix a node name issue with simple-bus schema. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a-qds.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts index 6e469b46229f..f1acb97aee69 100644 --- a/arch/arm/boot/dts/ls1021a-qds.dts +++ b/arch/arm/boot/dts/ls1021a-qds.dts @@ -205,7 +205,7 @@ nand@2,0 { fpga: board-control@3,0 { #address-cells = <1>; #size-cells = <1>; - compatible = "simple-bus"; + compatible = "simple-mfd"; reg = <0x3 0x0 0x0000100>; bank-width = <1>; device-width = <1>; From 08dc4d0c9535063d4a523b863746ed016a7b6a77 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Tue, 12 Oct 2021 18:58:21 -0500 Subject: [PATCH 40/42] ARM: dts: ls1021a-tsn: remove undocumented property "position" from mma8452 node Property "postion" is not documented in the mma8452 binding. Remove it to resolve the error in "make dtbs_check" Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a-tsn.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts b/arch/arm/boot/dts/ls1021a-tsn.dts index ce470ebfb2c0..8005efc5c812 100644 --- a/arch/arm/boot/dts/ls1021a-tsn.dts +++ b/arch/arm/boot/dts/ls1021a-tsn.dts @@ -137,7 +137,6 @@ &i2c0 { /* 3 axis accelerometer */ accelerometer@1e { compatible = "fsl,fxls8471"; - position = <0>; reg = <0x1e>; }; From 1ee1500ef717eefb5d9bdaf97905cb81b4e69aa4 Mon Sep 17 00:00:00 2001 From: Li Yang Date: Tue, 12 Oct 2021 18:58:22 -0500 Subject: [PATCH 41/42] ARM: dts: ls1021a: move thermal-zones node out of soc/ This fixes dtbs-check error from simple-bus schema: soc: thermal-zones: {'type': 'object'} is not allowed for {'cpu-thermal': ..... } From schema: /home/leo/.local/lib/python3.8/site-packages/dtschema/schemas/simple-bus.yaml Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a.dtsi | 66 +++++++++++++++++----------------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index cc7445e47641..2e69d6eab4d1 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -287,39 +287,6 @@ tmu: tmu@1f00000 { #thermal-sensor-cells = <1>; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <1000>; - polling-delay = <5000>; - - thermal-sensors = <&tmu 0>; - - trips { - cpu_alert: cpu-alert { - temperature = <85000>; - hysteresis = <2000>; - type = "passive"; - }; - cpu_crit: cpu-crit { - temperature = <95000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; - }; - }; - dspi0: spi@2100000 { compatible = "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; @@ -973,4 +940,37 @@ ftm_alarm0: timer0@29d0000 { big-endian; }; }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <5000>; + + thermal-sensors = <&tmu 0>; + + trips { + cpu_alert: cpu-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit: cpu-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + }; }; From 05e63b48b20fa70726be505a7660d1a07bc1cffb Mon Sep 17 00:00:00 2001 From: Li Yang Date: Tue, 12 Oct 2021 18:58:23 -0500 Subject: [PATCH 42/42] ARM: dts: ls1021a-tsn: use generic "jedec,spi-nor" compatible for flash We cannot list all the possible chips used in different board revisions, just use the generic "jedec,spi-nor" compatible instead. This also fixes dtbs_check error: ['jedec,spi-nor', 's25fl256s1', 's25fl512s'] is too long Signed-off-by: Li Yang Reviewed-by: Kuldeep Singh Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a-tsn.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ls1021a-tsn.dts b/arch/arm/boot/dts/ls1021a-tsn.dts index 8005efc5c812..ff0ffb22768b 100644 --- a/arch/arm/boot/dts/ls1021a-tsn.dts +++ b/arch/arm/boot/dts/ls1021a-tsn.dts @@ -251,7 +251,7 @@ &qspi { flash@0 { /* Rev. A uses 64MB flash, Rev. B & C use 32MB flash */ - compatible = "jedec,spi-nor", "s25fl256s1", "s25fl512s"; + compatible = "jedec,spi-nor"; spi-max-frequency = <20000000>; #address-cells = <1>; #size-cells = <1>;