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RDMA/ionic: add completion timestamp to CQE format

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Update the CQE structure to include hardware timestamp.
When firmware supports RDMA completion timestamps,
the hardware populates the timestamp field.

Co-developed-by: Allen Hubbe <allen.hubbe@amd.com>
Signed-off-by: Allen Hubbe <allen.hubbe@amd.com>
Signed-off-by: Abhijit Gangurde <abhijit.gangurde@amd.com>
Link: https://patch.msgid.link/20260610154216.712374-5-abhijit.gangurde@amd.com
Signed-off-by: Leon Romanovsky <leon@kernel.org>
This commit is contained in:
Abhijit Gangurde 2026-06-10 21:12:15 +05:30 committed by Leon Romanovsky
parent 7462d18889
commit 8ba0495046
2 changed files with 31 additions and 24 deletions
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43
drivers/infiniband/hw/ionic/ionic_datapath.c
View File

@ -32,6 +32,7 @@ static int ionic_flush_recv(struct ionic_qp *qp, struct ib_wc *wc)
{
struct ionic_rq_meta *meta;
struct ionic_v1_wqe *wqe;
u64 wqe_idx;
if (!qp->rq_flush)
return 0;
@ -40,21 +41,22 @@ static int ionic_flush_recv(struct ionic_qp *qp, struct ib_wc *wc)
return 0;
wqe = ionic_queue_at_cons(&qp->rq);
wqe_idx = le64_to_cpu(wqe->base.wqe_idx);
/* wqe_id must be a valid queue index */
if (unlikely(wqe->base.wqe_id >> qp->rq.depth_log2)) {
/* wqe_idx must be a valid queue index */
if (unlikely(wqe_idx >> qp->rq.depth_log2)) {
ibdev_warn(qp->ibqp.device,
"flush qp %u recv index %llu invalid\n",
qp->qpid, (unsigned long long)wqe->base.wqe_id);
qp->qpid, (unsigned long long)wqe_idx);
return -EIO;
}
/* wqe_id must indicate a request that is outstanding */
meta = &qp->rq_meta[wqe->base.wqe_id];
/* wqe_idx must indicate a request that is outstanding */
meta = &qp->rq_meta[wqe_idx];
if (unlikely(meta->next != IONIC_META_POSTED)) {
ibdev_warn(qp->ibqp.device,
"flush qp %u recv index %llu not posted\n",
qp->qpid, (unsigned long long)wqe->base.wqe_id);
qp->qpid, (unsigned long long)wqe_idx);
return -EIO;
}
@ -133,8 +135,8 @@ static int ionic_poll_recv(struct ionic_ibdev *dev, struct ionic_cq *cq,
{
struct ionic_qp *qp = NULL;
struct ionic_rq_meta *meta;
u16 vlan_tag, wqe_idx;
u32 src_qpn, st_len;
u16 vlan_tag;
u8 op;
if (cqe_qp->rq_flush)
@ -144,7 +146,7 @@ static int ionic_poll_recv(struct ionic_ibdev *dev, struct ionic_cq *cq,
st_len = be32_to_cpu(cqe->status_length);
/* ignore wqe_id in case of flush error */
/* ignore wqe_idx in case of flush error */
if (ionic_v1_cqe_error(cqe) && st_len == IONIC_STS_WQE_FLUSHED_ERR) {
cqe_qp->rq_flush = true;
cq->flush = true;
@ -160,20 +162,19 @@ static int ionic_poll_recv(struct ionic_ibdev *dev, struct ionic_cq *cq,
return -EIO;
}
/* wqe_id must be a valid queue index */
if (unlikely(cqe->recv.wqe_id >> qp->rq.depth_log2)) {
wqe_idx = le64_to_cpu(cqe->recv.wqe_idx_timestamp) & IONIC_V1_CQE_WQE_IDX_MASK;
/* wqe_idx must be a valid queue index */
if (unlikely(wqe_idx >> qp->rq.depth_log2)) {
ibdev_warn(&dev->ibdev,
"qp %u recv index %llu invalid\n",
qp->qpid, (unsigned long long)cqe->recv.wqe_id);
"qp %u recv index %u invalid\n", qp->qpid, wqe_idx);
return -EIO;
}
/* wqe_id must indicate a request that is outstanding */
meta = &qp->rq_meta[cqe->recv.wqe_id];
/* wqe_idx must indicate a request that is outstanding */
meta = &qp->rq_meta[wqe_idx];
if (unlikely(meta->next != IONIC_META_POSTED)) {
ibdev_warn(&dev->ibdev,
"qp %u recv index %llu not posted\n",
qp->qpid, (unsigned long long)cqe->recv.wqe_id);
"qp %u recv index %u not posted\n", qp->qpid, wqe_idx);
return -EIO;
}
@ -408,7 +409,7 @@ static int ionic_comp_msn(struct ionic_qp *qp, struct ionic_v1_cqe *cqe)
static int ionic_comp_npg(struct ionic_qp *qp, struct ionic_v1_cqe *cqe)
{
struct ionic_sq_meta *meta;
u16 cqe_idx;
u16 wqe_idx;
u32 st_len;
if (qp->sq_flush)
@ -430,8 +431,8 @@ static int ionic_comp_npg(struct ionic_qp *qp, struct ionic_v1_cqe *cqe)
return 0;
}
cqe_idx = cqe->send.npg_wqe_id & qp->sq.mask;
meta = &qp->sq_meta[cqe_idx];
wqe_idx = le64_to_cpu(cqe->send.npg_wqe_idx_timestamp) & qp->sq.mask;
meta = &qp->sq_meta[wqe_idx];
meta->local_comp = true;
if (ionic_v1_cqe_error(cqe)) {
@ -811,7 +812,7 @@ static void ionic_prep_base(struct ionic_qp *qp,
meta->signal = false;
meta->local_comp = false;
wqe->base.wqe_id = qp->sq.prod;
wqe->base.wqe_idx = cpu_to_le64(qp->sq.prod);
if (wr->send_flags & IB_SEND_FENCE)
wqe->base.flags |= cpu_to_be16(IONIC_V1_FLAG_FENCE);
@ -1205,7 +1206,7 @@ static int ionic_prep_recv(struct ionic_qp *qp,
meta->wrid = wr->wr_id;
wqe->base.wqe_id = meta - qp->rq_meta;
wqe->base.wqe_idx = cpu_to_le64(meta - qp->rq_meta);
wqe->base.num_sge_key = wr->num_sge;
/* total length for recv goes in base imm_data_key */

12
drivers/infiniband/hw/ionic/ionic_fw.h
View File

@ -332,7 +332,7 @@ struct ionic_v1_cqe {
__le16 old_rq_cq_cindex;
} admin;
struct {
__u64 wqe_id;
__le64 wqe_idx_timestamp;
__be32 src_qpn_op;
__u8 src_mac[6];
__be16 vlan_tag;
@ -342,13 +342,19 @@ struct ionic_v1_cqe {
__u8 rsvd[4];
__be32 msg_msn;
__u8 rsvd2[8];
__u64 npg_wqe_id;
__le64 npg_wqe_idx_timestamp;
} send;
};
__be32 status_length;
__be32 qid_type_flags;
};
/* bits for cqe wqe_idx and timestamp */
enum ionic_v1_cqe_wqe_idx_timestamp_bits {
IONIC_V1_CQE_WQE_IDX_MASK = 0xffff,
IONIC_V1_CQE_TIMESTAMP_SHIFT = 16,
};
/* bits for cqe recv */
enum ionic_v1_cqe_src_qpn_bits {
IONIC_V1_CQE_RECV_QPN_MASK = 0xffffff,
@ -423,7 +429,7 @@ static inline u32 ionic_v1_cqe_qtf_qid(u32 qtf)
/* v1 base wqe header */
struct ionic_v1_base_hdr {
__u64 wqe_id;
__le64 wqe_idx;
__u8 op;
__u8 num_sge_key;
__be16 flags;