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clk: tegra: Changes for v5.19-rc1
This contains a boot time optimization for Tegra chips with BPMP and a switch from .round_rate() to .determine_rate() to take into account any maximum rate that might have been set. Other than that this contains a fix for a DFLL regression on Tegra210 and kerneldoc fixups to avoid build warnings. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAmJ1KuUTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoXXwD/9Vs+njCehoJeiQno5fPMBzISFCrHka kP9R3NoTiaEfX8ujIqlBXJKFI8z7/C4j2z8lpgO/tcjoJLlv6B3Dt5KBak6WEThJ 511e9b1RCR4UlOb6gks1aq63ise1ZEBUBXXaOpwliC9l8WL6JiORunWRVqb7NQ2s v9lWBRhvBY5/GTotaBmn0E3zVc1b46m/GZ62xIgsj6RGoJQrN6QRPYsKHKMdgxz8 el9LKVN+8RJcRTG1DpXszJMdkW6WtuWgAS3+olXDA2gmGqvp6pcfMeWypGomvgBw 4sjBawd6ztxDgUo46K9xox81Bs479bHWO3CfFJiG54jVu7n092b85a52jH3RPkv7 X+sbEBs7sKVRJK0ce9BjpfqxfhV5bg59NaNKNZ/nPBOh9JjaqXxwKf+Iq8u3NuDx GVCTCIG3lz9zl4nSqoWskKg+YkopmZbp93mnKnRwyEd1lzY5qpPMfVYyZBGjm/xJ G8fLvOcvDmTUxHVnSEVxa+GFh6cRRRKNE7+VIrxwD5VaIB16yvoZ1notKrnoGvdS BsPsOHq8idQGqx8PqBtSI9utx4Y6szXwL3EJmE94zNdjgauMiW9vuszGVn9gQvb+ UvG8zAdc8P9GB52W76vU2U1KYtBuPWXEv6TiAdxboXxPZInQnFwISmh1GlFXRgM/ /WzebGRN8gfmLw== =fV6o -----END PGP SIGNATURE----- Merge tag 'for-5.19-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-tegra Pull Tegra clk driver updates from Thierry Reding: This contains a boot time optimization for Tegra chips with BPMP and a switch from .round_rate() to .determine_rate() to take into account any maximum rate that might have been set. Other than that this contains a fix for a DFLL regression on Tegra210 and kerneldoc fixups to avoid build warnings. * tag 'for-5.19-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: Update kerneldoc to match prototypes clk: tegra: Replace .round_rate() with .determine_rate() clk: tegra: Register clocks from root to leaf clk: tegra: Add missing reset deassertion
This commit is contained in:
Stephen Boyd
commit
8b9d9e9f8e
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@ -164,15 +164,18 @@ static unsigned long tegra_bpmp_clk_recalc_rate(struct clk_hw *hw,
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return response.rate;
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}
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static long tegra_bpmp_clk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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static int tegra_bpmp_clk_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *rate_req)
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{
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struct tegra_bpmp_clk *clk = to_tegra_bpmp_clk(hw);
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struct cmd_clk_round_rate_response response;
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struct cmd_clk_round_rate_request request;
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struct tegra_bpmp_clk_message msg;
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unsigned long rate;
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int err;
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rate = min(max(rate_req->rate, rate_req->min_rate), rate_req->max_rate);
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memset(&request, 0, sizeof(request));
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request.rate = min_t(u64, rate, S64_MAX);
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@ -188,7 +191,9 @@ static long tegra_bpmp_clk_round_rate(struct clk_hw *hw, unsigned long rate,
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if (err < 0)
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return err;
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return response.rate;
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rate_req->rate = (unsigned long)response.rate;
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return 0;
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}
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static int tegra_bpmp_clk_set_parent(struct clk_hw *hw, u8 index)
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@ -290,7 +295,7 @@ static const struct clk_ops tegra_bpmp_clk_rate_ops = {
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.unprepare = tegra_bpmp_clk_unprepare,
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.is_prepared = tegra_bpmp_clk_is_prepared,
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.recalc_rate = tegra_bpmp_clk_recalc_rate,
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.round_rate = tegra_bpmp_clk_round_rate,
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.determine_rate = tegra_bpmp_clk_determine_rate,
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.set_rate = tegra_bpmp_clk_set_rate,
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};
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@ -299,7 +304,7 @@ static const struct clk_ops tegra_bpmp_clk_mux_rate_ops = {
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.unprepare = tegra_bpmp_clk_unprepare,
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.is_prepared = tegra_bpmp_clk_is_prepared,
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.recalc_rate = tegra_bpmp_clk_recalc_rate,
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.round_rate = tegra_bpmp_clk_round_rate,
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.determine_rate = tegra_bpmp_clk_determine_rate,
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.set_parent = tegra_bpmp_clk_set_parent,
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.get_parent = tegra_bpmp_clk_get_parent,
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.set_rate = tegra_bpmp_clk_set_rate,
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@ -448,15 +453,29 @@ static int tegra_bpmp_probe_clocks(struct tegra_bpmp *bpmp,
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return count;
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}
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static unsigned int
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tegra_bpmp_clk_id_to_index(const struct tegra_bpmp_clk_info *clocks,
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unsigned int num_clocks, unsigned int id)
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{
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unsigned int i;
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for (i = 0; i < num_clocks; i++)
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if (clocks[i].id == id)
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return i;
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return UINT_MAX;
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}
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static const struct tegra_bpmp_clk_info *
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tegra_bpmp_clk_find(const struct tegra_bpmp_clk_info *clocks,
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unsigned int num_clocks, unsigned int id)
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{
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unsigned int i;
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for (i = 0; i < num_clocks; i++)
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if (clocks[i].id == id)
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return &clocks[i];
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i = tegra_bpmp_clk_id_to_index(clocks, num_clocks, id);
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if (i < num_clocks)
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return &clocks[i];
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return NULL;
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}
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@ -539,31 +558,57 @@ tegra_bpmp_clk_register(struct tegra_bpmp *bpmp,
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return clk;
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}
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static void tegra_bpmp_register_clocks_one(struct tegra_bpmp *bpmp,
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struct tegra_bpmp_clk_info *infos,
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unsigned int i,
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unsigned int count)
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{
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unsigned int j;
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struct tegra_bpmp_clk_info *info;
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struct tegra_bpmp_clk *clk;
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if (bpmp->clocks[i]) {
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/* already registered */
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return;
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}
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info = &infos[i];
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for (j = 0; j < info->num_parents; ++j) {
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unsigned int p_id = info->parents[j];
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unsigned int p_i = tegra_bpmp_clk_id_to_index(infos, count,
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p_id);
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if (p_i < count)
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tegra_bpmp_register_clocks_one(bpmp, infos, p_i, count);
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}
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clk = tegra_bpmp_clk_register(bpmp, info, infos, count);
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if (IS_ERR(clk)) {
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dev_err(bpmp->dev,
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"failed to register clock %u (%s): %ld\n",
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info->id, info->name, PTR_ERR(clk));
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/* intentionally store the error pointer to
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* bpmp->clocks[i] to avoid re-attempting the
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* registration later
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*/
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}
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bpmp->clocks[i] = clk;
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}
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static int tegra_bpmp_register_clocks(struct tegra_bpmp *bpmp,
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struct tegra_bpmp_clk_info *infos,
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unsigned int count)
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{
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struct tegra_bpmp_clk *clk;
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unsigned int i;
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bpmp->num_clocks = count;
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bpmp->clocks = devm_kcalloc(bpmp->dev, count, sizeof(clk), GFP_KERNEL);
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bpmp->clocks = devm_kcalloc(bpmp->dev, count, sizeof(struct tegra_bpmp_clk), GFP_KERNEL);
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if (!bpmp->clocks)
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return -ENOMEM;
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for (i = 0; i < count; i++) {
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struct tegra_bpmp_clk_info *info = &infos[i];
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clk = tegra_bpmp_clk_register(bpmp, info, infos, count);
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if (IS_ERR(clk)) {
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dev_err(bpmp->dev,
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"failed to register clock %u (%s): %ld\n",
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info->id, info->name, PTR_ERR(clk));
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continue;
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}
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bpmp->clocks[i] = clk;
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tegra_bpmp_register_clocks_one(bpmp, infos, i, count);
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}
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return 0;
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@ -271,6 +271,7 @@ struct tegra_dfll {
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struct clk *ref_clk;
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struct clk *i2c_clk;
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struct clk *dfll_clk;
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struct reset_control *dfll_rst;
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struct reset_control *dvco_rst;
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unsigned long ref_rate;
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unsigned long i2c_clk_rate;
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@ -666,7 +667,7 @@ static int dfll_force_output(struct tegra_dfll *td, unsigned int out_sel)
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}
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/**
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* dfll_load_lut - load the voltage lookup table
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* dfll_load_i2c_lut - load the voltage lookup table
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* @td: struct tegra_dfll *
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*
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* Load the voltage-to-PMIC register value lookup table into the DFLL
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@ -897,7 +898,7 @@ static void dfll_set_frequency_request(struct tegra_dfll *td,
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}
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/**
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* tegra_dfll_request_rate - set the next rate for the DFLL to tune to
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* dfll_request_rate - set the next rate for the DFLL to tune to
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* @td: DFLL instance
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* @rate: clock rate to target
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*
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@ -1005,7 +1006,7 @@ static void dfll_set_open_loop_config(struct tegra_dfll *td)
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}
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/**
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* tegra_dfll_lock - switch from open-loop to closed-loop mode
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* dfll_lock - switch from open-loop to closed-loop mode
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* @td: DFLL instance
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*
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* Switch from OPEN_LOOP state to CLOSED_LOOP state. Returns 0 upon success,
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@ -1046,7 +1047,7 @@ static int dfll_lock(struct tegra_dfll *td)
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}
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/**
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* tegra_dfll_unlock - switch from closed-loop to open-loop mode
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* dfll_unlock - switch from closed-loop to open-loop mode
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* @td: DFLL instance
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*
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* Switch from CLOSED_LOOP state to OPEN_LOOP state. Returns 0 upon success,
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@ -1464,6 +1465,7 @@ static int dfll_init(struct tegra_dfll *td)
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return -EINVAL;
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}
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reset_control_deassert(td->dfll_rst);
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reset_control_deassert(td->dvco_rst);
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ret = clk_prepare(td->ref_clk);
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@ -1509,6 +1511,7 @@ static int dfll_init(struct tegra_dfll *td)
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clk_unprepare(td->ref_clk);
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reset_control_assert(td->dvco_rst);
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reset_control_assert(td->dfll_rst);
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return ret;
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}
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@ -1530,6 +1533,7 @@ int tegra_dfll_suspend(struct device *dev)
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}
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reset_control_assert(td->dvco_rst);
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reset_control_assert(td->dfll_rst);
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return 0;
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}
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@ -1548,6 +1552,7 @@ int tegra_dfll_resume(struct device *dev)
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{
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struct tegra_dfll *td = dev_get_drvdata(dev);
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reset_control_deassert(td->dfll_rst);
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reset_control_deassert(td->dvco_rst);
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pm_runtime_get_sync(td->dev);
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@ -1951,6 +1956,12 @@ int tegra_dfll_register(struct platform_device *pdev,
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td->soc = soc;
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td->dfll_rst = devm_reset_control_get_optional(td->dev, "dfll");
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if (IS_ERR(td->dfll_rst)) {
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dev_err(td->dev, "couldn't get dfll reset\n");
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return PTR_ERR(td->dfll_rst);
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}
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td->dvco_rst = devm_reset_control_get(td->dev, "dvco");
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if (IS_ERR(td->dvco_rst)) {
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dev_err(td->dev, "couldn't get dvco reset\n");
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@ -2087,6 +2098,7 @@ struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev)
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clk_unprepare(td->i2c_clk);
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reset_control_assert(td->dvco_rst);
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reset_control_assert(td->dfll_rst);
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return td->soc;
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}
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