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perf vendor events intel: Update arrowlake events from 1.16 to 1.17

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The updated events were published in:

  90c505bcd9

Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andreas Färber <afaerber@suse.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Falcon <thomas.falcon@intel.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Ian Rogers 2026-05-28 21:51:45 -07:00 committed by Arnaldo Carvalho de Melo
parent 9996a23d31
commit 8a990b123b
4 changed files with 110 additions and 2 deletions
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53
tools/perf/pmu-events/arch/x86/arrowlake/cache.json
View File

@ -339,6 +339,16 @@
"UMask": "0x2",
"Unit": "cpu_atom"
},
{
"BriefDescription": "All requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x24",
"EventName": "L2_REQUEST.HIT",
"PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_RQSTS.HIT]",
"SampleAfterValue": "200003",
"UMask": "0x5f",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts the number of L2 Cache Accesses that resulted in a Hit from a front door request only (does not include rejects or recycles), per core event",
"Counter": "0,1,2,3,4,5,6,7",
@ -464,6 +474,16 @@
"UMask": "0x21",
"Unit": "cpu_core"
},
{
"BriefDescription": "All requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT]",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0x24",
"EventName": "L2_RQSTS.HIT",
"PublicDescription": "Counts all requests that hit L2 cache. [This event is alias to L2_REQUEST.HIT]",
"SampleAfterValue": "200003",
"UMask": "0x5f",
"Unit": "cpu_core"
},
{
"BriefDescription": "Read requests with true-miss in L2 cache [This event is alias to L2_REQUEST.MISS]",
"Counter": "0,1,2,3,4,5,6,7,8,9",
@ -1126,6 +1146,15 @@
"UMask": "0x20",
"Unit": "cpu_core"
},
{
"BriefDescription": "Counts the number of retired load ops that hit in the L3 cache in which a snoop was required and modified data was forwarded",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xd4",
"EventName": "MEM_LOAD_UOPS_MISC_RETIRED.L3_HIT_SNOOP_HITM",
"SampleAfterValue": "1000003",
"UMask": "0x8",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of retired load ops with an unknown source",
"Counter": "0,1,2,3,4,5,6,7",
@ -1393,6 +1422,18 @@
"UMask": "0x82",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024",
"MSRIndex": "0x3F6",
"MSRValue": "0x400",
"SampleAfterValue": "200003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 1024. Only counts with PEBS enabled.",
"Counter": "0,1",
@ -1453,6 +1494,18 @@
"UMask": "0x5",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048.",
"Counter": "0,1",
"Data_LA": "1",
"EventCode": "0xd0",
"EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048",
"MSRIndex": "0x3F6",
"MSRValue": "0x800",
"SampleAfterValue": "200003",
"UMask": "0x5",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold of 2048. Only counts with PEBS enabled.",
"Counter": "0,1",

9
tools/perf/pmu-events/arch/x86/arrowlake/floating-point.json
View File

@ -564,6 +564,15 @@
"UMask": "0x1",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of uops executed on floating point and vector integer store data port.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xb2",
"EventName": "FP_VINT_UOPS_EXECUTED.STD",
"SampleAfterValue": "1000003",
"UMask": "0x1",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
"Counter": "0,1,2,3,4,5,6,7",

48
tools/perf/pmu-events/arch/x86/arrowlake/pipeline.json
View File

@ -376,7 +376,7 @@
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of taken branch instructions retired",
"BriefDescription": "Counts the number of near taken branch instructions retired",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.NEAR_TAKEN",
@ -422,6 +422,15 @@
"UMask": "0xfd",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of relative JMP branch instructions retired.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.REL_JMP",
"SampleAfterValue": "200003",
"UMask": "0xdf",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of near relative JMP branch instructions retired.",
"Counter": "0,1,2,3,4,5,6,7",
@ -431,6 +440,25 @@
"UMask": "0xdf",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of taken branch instructions retired",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.TAKEN",
"SampleAfterValue": "200003",
"UMask": "0x80",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of taken branch instructions retired.",
"Counter": "0,1,2,3,4,5,6,7",
"Errata": "ARL011",
"EventCode": "0xc4",
"EventName": "BR_INST_RETIRED.TAKEN",
"SampleAfterValue": "200003",
"UMask": "0x80",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
"Counter": "0,1,2,3,4,5,6,7",
@ -1663,6 +1691,15 @@
"UMask": "0x88",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts number of virtual trap actually taken (e.g. highest priority event during retirement). It can count virtual trap from FPC port 0 or port 1 (x87/SSE) equally in a single counter.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.FPC_VIRTUAL_TRAP",
"SampleAfterValue": "20003",
"UMask": "0x40",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of nukes due to memory renaming",
"Counter": "0,1,2,3,4,5,6,7",
@ -1672,6 +1709,15 @@
"UMask": "0x10",
"Unit": "cpu_atom"
},
{
"BriefDescription": "Counts the number of machines clears due to memory renaming.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.MRN_NUKE",
"SampleAfterValue": "1000003",
"UMask": "0x80",
"Unit": "cpu_lowpower"
},
{
"BriefDescription": "Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode.",
"Counter": "0,1,2,3,4,5,6,7",

2
tools/perf/pmu-events/arch/x86/mapfile.csv
View File

@ -1,7 +1,7 @@
Family-model,Version,Filename,EventType
GenuineIntel-6-(97|9A|B7|BA|BF),v1.39,alderlake,core
GenuineIntel-6-BE,v1.39,alderlaken,core
GenuineIntel-6-C[56],v1.16,arrowlake,core
GenuineIntel-6-C[56],v1.17,arrowlake,core
GenuineIntel-6-(1C|26|27|35|36),v5,bonnell,core
GenuineIntel-6-(3D|47),v30,broadwell,core
GenuineIntel-6-56,v12,broadwellde,core

1 Family-model Version Filename EventType
2 GenuineIntel-6-(97|9A|B7|BA|BF) v1.39 alderlake core
3 GenuineIntel-6-BE v1.39 alderlaken core
4 GenuineIntel-6-C[56] v1.16 v1.17 arrowlake core
5 GenuineIntel-6-(1C|26|27|35|36) v5 bonnell core
6 GenuineIntel-6-(3D|47) v30 broadwell core
7 GenuineIntel-6-56 v12 broadwellde core