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soc: mediatek: mt8188-mmsys: Migrate to MMSYS_ROUTE() macro
Change the initialization data in the arrays of structure mtk_mmsys_routes to make use of the MMSYS_ROUTE() macro: this will make sure that each array entry's SEL value fits in its corresponding register mask with a compile time check. Link: https://lore.kernel.org/r/20250212100012.33001-5-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
This commit is contained in:
AngeloGioacchino Del Regno
parent
854ac9c888
commit
8a7b1efb2a
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@ -202,158 +202,117 @@ static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
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};
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static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
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{
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DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
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MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0,
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MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0
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}, {
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DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
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MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0,
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MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0
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}, {
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DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
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MT8188_VDO0_DISP_RDMA_SEL, MT8188_SEL_IN_DISP_RDMA0_FROM_MASK,
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MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0
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}, {
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
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MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK,
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MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0
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}, {
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_MERGE0,
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MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK,
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MT8188_SEL_IN_VPP_MERGE_FROM_DITHER0_OUT
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}, {
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
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MT8188_VDO0_DSC_WARP_SEL,
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MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK,
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MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0
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}, {
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0,
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MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK,
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MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0
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}, {
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DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
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MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK,
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MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
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}, {
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DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
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MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK,
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MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
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MT8188_VDO0_DISP_RDMA_SEL, MT8188_SOUT_DISP_RDMA0_TO_MASK,
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MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0
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}, {
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
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MT8188_VDO0_DISP_DITHER0_SEL_OUT,
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MT8188_SOUT_DISP_DITHER0_TO_MASK,
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MT8188_SOUT_DISP_DITHER0_TO_DSI0
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}, {
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DDP_COMPONENT_DITHER0, DDP_COMPONENT_DP_INTF0,
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MT8188_VDO0_DISP_DITHER0_SEL_OUT,
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MT8188_SOUT_DISP_DITHER0_TO_MASK,
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MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0
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}, {
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DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
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MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
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MT8188_SOUT_VPP_MERGE_TO_DP_INTF0
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}, {
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DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
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MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
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MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
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}, {
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DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA0,
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MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
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MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0
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}, {
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DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
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MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
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MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
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}, {
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DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
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MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK,
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MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0
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}, {
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DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
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MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK,
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MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
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},
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MMSYS_ROUTE(OVL0, RDMA0,
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MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0,
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MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0),
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MMSYS_ROUTE(OVL0, WDMA0,
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MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0,
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MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0),
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MMSYS_ROUTE(OVL0, RDMA0,
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MT8188_VDO0_DISP_RDMA_SEL, MT8188_SEL_IN_DISP_RDMA0_FROM_MASK,
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MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0),
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MMSYS_ROUTE(DITHER0, DSI0,
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MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK,
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MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0),
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MMSYS_ROUTE(DITHER0, MERGE0,
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MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK,
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MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0),
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MMSYS_ROUTE(DITHER0, DSC0,
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MT8188_VDO0_DSC_WARP_SEL, MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK,
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MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0),
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MMSYS_ROUTE(DITHER0, DP_INTF0,
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MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK,
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MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0),
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MMSYS_ROUTE(DSC0, MERGE0,
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MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK,
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MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT),
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MMSYS_ROUTE(DSC0, DSI0,
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MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK,
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MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT),
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MMSYS_ROUTE(RDMA0, COLOR0,
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MT8188_VDO0_DISP_RDMA_SEL, GENMASK(1, 0),
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MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0),
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MMSYS_ROUTE(DITHER0, DSI0,
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MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK,
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MT8188_SOUT_DISP_DITHER0_TO_DSI0),
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MMSYS_ROUTE(DITHER0, DP_INTF0,
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MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK,
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MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0),
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MMSYS_ROUTE(MERGE0, DP_INTF0,
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MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
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MT8188_SOUT_VPP_MERGE_TO_DP_INTF0),
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MMSYS_ROUTE(MERGE0, DPI0,
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MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
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MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0),
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MMSYS_ROUTE(MERGE0, WDMA0,
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MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
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MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0),
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MMSYS_ROUTE(MERGE0, DSC0,
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MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
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MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN),
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MMSYS_ROUTE(DSC0, DSI0,
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MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK,
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MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0),
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MMSYS_ROUTE(DSC0, MERGE0,
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MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK,
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MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE),
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};
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static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] = {
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{
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DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1,
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MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
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MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0
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}, {
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DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1,
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MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
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MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1
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}, {
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DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2,
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MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
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MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2
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}, {
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DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
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MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
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MT8188_SOUT_TO_MIXER_IN1_SEL
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}, {
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DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
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MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
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MT8188_SOUT_TO_MIXER_IN2_SEL
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}, {
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DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
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MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
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MT8188_SOUT_TO_MIXER_IN3_SEL
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}, {
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DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
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MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
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MT8188_SOUT_TO_MIXER_IN4_SEL
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}, {
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DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
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MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
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MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL
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}, {
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DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER,
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MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
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MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT
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}, {
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DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER,
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MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
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MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT
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}, {
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DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER,
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MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
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MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT
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}, {
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DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER,
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MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
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MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT
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}, {
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DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
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MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
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MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER
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}, {
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DDP_COMPONENT_ETHDR_MIXER, DDP_COMPONENT_MERGE5,
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MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
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MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT
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}, {
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DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
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MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
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MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT
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}, {
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DDP_COMPONENT_MERGE5, DDP_COMPONENT_DPI1,
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MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
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MT8188_MERGE4_SOUT_TO_DPI1_SEL
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}, {
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DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
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MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
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MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT
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}, {
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DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF1,
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MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
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MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL
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}
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MMSYS_ROUTE(MDP_RDMA0, MERGE1,
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MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
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MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0),
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MMSYS_ROUTE(MDP_RDMA1, MERGE1,
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MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
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MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1),
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MMSYS_ROUTE(MDP_RDMA2, MERGE2,
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MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
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MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2),
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MMSYS_ROUTE(MERGE1, ETHDR_MIXER,
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MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
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MT8188_SOUT_TO_MIXER_IN1_SEL),
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MMSYS_ROUTE(MERGE2, ETHDR_MIXER,
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MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
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MT8188_SOUT_TO_MIXER_IN2_SEL),
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MMSYS_ROUTE(MERGE3, ETHDR_MIXER,
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MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
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MT8188_SOUT_TO_MIXER_IN3_SEL),
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MMSYS_ROUTE(MERGE4, ETHDR_MIXER,
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MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
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MT8188_SOUT_TO_MIXER_IN4_SEL),
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MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
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MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
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MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL),
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MMSYS_ROUTE(MERGE1, ETHDR_MIXER,
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MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
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MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT),
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MMSYS_ROUTE(MERGE2, ETHDR_MIXER,
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MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
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MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT),
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MMSYS_ROUTE(MERGE3, ETHDR_MIXER,
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MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
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MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT),
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MMSYS_ROUTE(MERGE4, ETHDR_MIXER,
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MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
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MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT),
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MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
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MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
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MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER),
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MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
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MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
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MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT),
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MMSYS_ROUTE(MERGE5, DPI1,
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MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
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MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT),
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MMSYS_ROUTE(MERGE5, DPI1,
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MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
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MT8188_MERGE4_SOUT_TO_DPI1_SEL),
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MMSYS_ROUTE(MERGE5, DP_INTF1,
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MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
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MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT),
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MMSYS_ROUTE(MERGE5, DP_INTF1,
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MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
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MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL),
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};
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#endif /* __SOC_MEDIATEK_MT8188_MMSYS_H */
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