From 8a78168e98a93a6f4f2617347a83286f519ac247 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 24 Jul 2026 09:50:04 +0200 Subject: [PATCH] ARM: dts: ixp4xx: Drop the reg-offset hack The reg-offset hack only works when the IXP4xx platform is running in big endian mode, and it is there to byte-offset the byte where the serial registers appear in the BE config. This is clearly wrong, workarounds need to be in the drivers. Drop the reg-offset. Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20260724-ixp4xx-dts-fix-v1-1-09bf7111e94e@kernel.org Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi b/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi index 0adeccabd4fe..b0f98da8def4 100644 --- a/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp4xx.dtsi @@ -84,11 +84,6 @@ pci@c0000000 { uart0: serial@c8000000 { compatible = "intel,xscale-uart"; reg = <0xc8000000 0x1000>; - /* - * The reg-offset and reg-shift is a side effect - * of running the platform in big endian mode. - */ - reg-offset = <3>; reg-shift = <2>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <14745600>; @@ -98,11 +93,6 @@ uart0: serial@c8000000 { uart1: serial@c8001000 { compatible = "intel,xscale-uart"; reg = <0xc8001000 0x1000>; - /* - * The reg-offset and reg-shift is a side effect - * of running the platform in big endian mode. - */ - reg-offset = <3>; reg-shift = <2>; interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; clock-frequency = <14745600>;